EM643FV16FU Series Low Power, 256Kx16 SRAM

Transcription

1 Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft May 26, 2003 Preliminary nd Draft Add Pb-free part number February 13, 2004 Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : Tel : ~1766 Fax : / Homepage : The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1

2 FEATURES Process Technology : 0.18µm Full CMOS Organization : 256K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 44-TSOP2 GENERAL DESCRIPTION The EM643FV16FU families are fabricated by EMLSI s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby (I SB1, Typ.) Operating (I CC1.Max.) PKG Type EM643FV16FU Industrial (-40 ~ 85 o C) 2.7V~3.6V 55 1) /70ns 1 µa 2) 3 ma 44-TSOP2 1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A TSOP A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 A 0 A 1 A 2 A3 A4 A 5 A 6 A 7 A8 A9 A 10 I/O1 ~ I/O8 I/O9 ~ I/O16 Row Select Data Cont Data Cont Pre-charge Circuit Memory Array 2048 x 2048 I/O Circuit Column Select V CC V SS A11 A12 A13 A14 A15 A16 A 17 Name Function Name Function Chip select input Vcc Power Supply OE Output Enable input Vss Ground WE Write Enable input UB Upper Byte (I/O 9~16 ) WE OE UB LB Control Logic A 0 ~A 17 Address Inputs LB Lower Byte (I/O 1~8 ) I/O 1 ~I/O 16 Data Inputs/outputs NC No Connection 2

3 ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to Vcc+0.3(Max.4.0V) V Voltage on Vcc supply relative to Vss V CC -0.2 to 4.0V V Power Dissipation P D 1.0 W Operating Temperature T A -40 to 85 o C * Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION OE WE LB UB I/O 1-8 I/O 9-16 Mode Power H X X X X Deselected Stand by L H H X X Output Disabled Active L X X H H Output Disabled Active L L H L H Data Out Lower Byte Read Active L L H H L Data Out Upper Byte Read Active L L H L L Data Out Data Out Word Read Active L X L L H Data In Lower Byte Write Active L X L H L Data In Upper Byte Write Active L X L L L Data in Data In Word Write Active Note: X means don t care. (Must be low or high state) 3

4 RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit Supply voltage V CC V Ground V SS V Input high voltage V IH V CC ) V Input low voltage V IL ) V 1. TA= -40 to 85 o C, otherwise specified 2. Overshoot: VCC +2.0 V in case of pulse width < 20ns 3. Undershoot: -2.0 V in case of pulse width < 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, T A =25 o C) Item Symbol Test Condition Min Max Unit Input capacitance C IN V IN =0V - 8 pf Input/Ouput capacitance C IO V IO =0V - 10 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTI Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current I LI V IN =V SS to V CC -1-1 µa Output leakage current I LO =V IH or OE=V IH or WE=V IL, V IO =V SS to V CC -1-1 µa Operating power supply I CC I IO =0mA, =V IL, V IN =V IH or V IL ma Average operating current I CC1 I CC2 Cycle time=1µs, 100% duty, I IO =0mA, <0.2V, V IN <0.2V or V IN >V CC -0.2V ma Cycle time = Min, I IO =0mA, 100% duty, 55ns =V IL, V IN =V IL or V IH 70ns ma Output low voltage V OL I OL = 2.1mA V Output high voltage V OH I OH = -1.0mA V Standby Current (TTL) I SB =V IH, Other inputs=v IH or V IL ma Standby Current (CMOS) I SB1 (Typ. condition : V CC 25 o C) >V CC -0.2V, Other inputs=0~v CC (Max. condition : V CC 85 o C) LL LF - 1 1) 12 µa NOTES 1. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. 4

5 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R 1 =3070Ω, R 2 =3150Ω 3. V TM =2.8V CL 1) V TM 3) R 1 2) R 2 2) READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol 55ns 70ns Min Max Min Max Unit Read cycle time t RC ns Address access time t AA ns Chip select to output t CO ns Output enable to valid output t OE ns UB, LB acess time t BA ns Chip select to low-z output t LZ ns UB, LB enable to low-z output t BLZ ns Output enable to low-z output t OLZ ns Chip disable to high-z output t HZ ns UB, LB disable to high-z output t BHZ ns Output disable to high-z output t OHZ ns Output hold from address change t OH ns WRITE CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol 55ns 70ns Min Max Min Max Unit Write cycle time t WC ns Chip select to end of write t CW ns Address setup time t AS ns Address valid to end of write t AW ns UB, LB valid to end of write t BW ns Write pulse width t WP ns Write recovery time t WR ns Write to ouput high-z t WHZ ns Data to write time overlap t DW ns Data hold from write time t DH ns End write to output low-z t OW ns 5

6 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, =OE=V IL, WE=V IH, UB or/and LB = V IL ) Address t RC t OH t AA Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = V IH ) Address t RC t AA t OH t CO UB,LB t BA t HZ OE t OE t BHZ Data Out t OLZ Data Valid t OHZ t BLZ t LZ NOTES (READ CYCLE) 1. t HZ and t OHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection. 6

7 TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) Address t WC t CW (2) t WR (4) t AW UB,LB t BW t WP (1) WE t AS (3) t DW t DH Data in Data Valid t WHZ t OW Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) ( CONTROLLED) Address t WC tas(3) t CW (2) t WR (4) t AW UB,LB t BW t WP (1) WE Data in t DW Data Valid t DH Data out 7

8 TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED) Address t WC t CW (2) t WR (4) t AW UB,LB t BW t AS (3) t WP (1) WE Data in t DW Data Valid t DH Data out NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP ) of low and low WE. A write begins when goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when goes high and WE goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the going low to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as or WE going high. 8

9 DATA RETENTION CHARACTERISTI Parameter Symbol Test Condition Min Typ 2) Max Unit V CC for Data Retention V DR I SB1 Test Condition (Chip Disabled) 1) V Data Retention Current I DR V CC =1.5V, I SB1 Test Condition (Chip Disabled) 1) µa Chip Deselect to Data Retention Time t SDR See data retention wave form Operation Recovery Time t RDR t RC - - ns NOTES 1. See the I SB1 measurement condition of datasheet page Typical values are measured at T A =25 o C and not 100% tested. DATA RETENTION WAVE FORM t SDR Data Retention Mode t RDR V cc 2.7V 2.2V V DR GND > Vcc-0.2V 9

10 PACKAGE DIMENSION Unit: millimeters 10

11 MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Device Type 11. Power 10. Speed 3. Density 4. Option 5. Technology 6. Operating Voltage 9. Packages 8. Version 7. Orgainzation 1. Memory Component 2. Device Type Low Power SRAM STRAM 3. Density M M M M M M M 4. Mode Option Dual Single Multiplexed Address Single with LB,UB (tba=toe) Single with LB,UB (tba=tco) Dual with LB,UB (tba=toe) Dual with LB,UB (tba=tco) 5. Technology Blank CMOS F Full CMOS 6. Operating Voltage Blank V V V~3.6V U V S V R V P V 7. Orginzation x8 bit x16 bit x32 bit 8. Version Blank Mother Die A First revision B Second revision C Third revision D Fourth revision E Fifth revision F Sixth revision 9. Package Blank FPBGA S stsop1 T TSOP1 U TSOP2 W Wafer 10. Speed ns ns ns ns ns ns 11. Power LL Low Low Power LF Low Low Power (Pb-free) L Low Power S Standard Power 11