Thermal Design of SoC at the Micron Scale Rajit Chandra, Ph.D. Founder, CTO Gradient Design Automation Santa Clara, California

Transcription

1 Thermal Design of SoC at the Micron Scale Rajit Chandra, Ph.D. Founder, CTO Gradient Design Automation Santa Clara, California 3/19/ Gradient Design Automation 1

2 Electronic thermal management Package designs that meet T J-MAX specs, given the total chip power dissipation Designing effective chip-package cooling solutions Minimizing package costs 3/19/ Gradient Design Automation 2

3 Meeting the T J-MAX Specs Calculate the average temperature of packagedie interface: Total chip power Θ JC Constant temperature Area averaged power map Estimate the temperature variation within the die Geometry associated power map 3/19/ Gradient Design Automation 3

4 Transitioning from mm- to micron-scale 3/19/ Gradient Design Automation 4

5 Google Earth for chip temperature 3/19/ Gradient Design Automation 5

6 Micron-scale thermal profile 3/19/ Gradient Design Automation 6

7 Micron-scale thermal hazard T 8ºC 3/19/ Gradient Design Automation 7

8 Why micron-scale temperatures? Higher power densities on the chip Larger temperature variations Steeper thermal gradients on the chip 3/19/ Gradient Design Automation 8

9 Adding to SoC thermal challenges Miniature form factor increasing thermal resistance of IC packages (or the lack thereof) SiP, multi-die assemblies, stacked chips, CoF 3/19/ Gradient Design Automation 9

10 Coarse-grain analysis Fine-grain analysis T j-predicted T j-actual T j-max Temperature profile Coarse-grain Predicted margin Temperature profile Fine-grain Actual margin IC cross section IC cross section Distance Distance 3/19/ Gradient Design Automation 10

11 Micron-scale thermal modeling To get at all the micron-scale details, painlessly, the chip thermal tools must integrate with the Thermal chip design profile tools of RF and Power data Amp transistor segments 3/19/ Gradient Design Automation 11

12 Micron-scale modeling Standard cell Standard Cell Die stack-up, metal layers, standard cells and/or transistors are modeled explicitly from EDA data 3/19/ Gradient Design Automation 12

13 How hot are the metal lines? At 90, 65 and 45nm: Power densities are very high Metal line current densities can also be very high I 2 R self-heating in the metal lines can be significant Low-K dielectric has low heat conductivity Intel 65nm BEOL cross-section Source: Intel Corp. 3/19/ Gradient Design Automation 13

14 Visualization of hotspots on wires: Exposes signal wire electromigration 3/19/ Gradient Design Automation 14

15 3/19/ Gradient Design Automation 15

16 Gradient user quote: Managing heat is important in high-power design; too much heat can contribute to reliability problems like electromigration and thermal runaway. The thermal map of a circuit can be used as a floorplanning tool to reduce temperature deltas in sensitive areas of the design; this may translate to greater efficiency. [CircuitFire] runs successive simulations... A designer can then look at the thermal map and make decisions about how the heat producing elements can be placed, Using Thermal Analysis as a Tool to Aid Analog Floorplanning, David Schwan, Senior CAD and Layout Manager, Sirenza Microdevices Inc (now RF Micro Devices). 3/19/ Gradient Design Automation 16

17 Gradient user quote: During the initial design of our automotive chip, our engineers didn't find any problems with Spectre. During testing of fabricated parts, our part was found to have a serious problem It took 3 ECO s to figure out what was wrong When we simulated in Spectre the circuit in the same mode that caused it to fail on the test floor, the circuit functioned correctly! If we had run CircuitFire at the chip level *before* tape-out, we would have spotted the problem before going to silicon. ESNUG, One user s eval of the Gradient CircuitFire tool, Morgan Ercanbrack of AMI Semiconductor. 3/19/ Gradient Design Automation 17

18 Integrate with chip design tools & data Power modeling Functionality modeling Design layout Micron-Scale Thermal Simulation Timing modeling Package modeling Thermal techfile Die stack-up Reliability modeling 3/19/ Gradient Design Automation 18

19 Summary We have seen significant temperature variations at the micron scale, some of which have caused chips to fail Package engineers are responsible for thermal management Package thermal tools today are not suited for simulating temperature variations at the chip-scale For ease of use, the chip thermal tools must integrate with the chip design tools and data, to get at all the micron-scale details, painlessly Micron-scale thermal analysis requires suitably detailed package model from package engineers 3/19/ Gradient Design Automation 19