Worldwide IC Package Forecast (Executive Summary) Executive Summary

Transcription

1 Worldwide IC Package Forecast (Executive Summary) Executive Summary Publication Date: 7 August 2003

2 Author Masao Kuniba This document has been published to the following Marketplace codes: SEMC-WW-EX-0275 For More Information... In North America and Latin America: In Europe, the Middle East and Africa: In Asia/Pacific: In Japan: Worldwide via gartner.com: Entire contents 2003 Gartner, Inc. and/or its Affiliates. All Rights Reserved. Reproduction of this publication in any form without prior written permission is forbidden. The information contained herein has been obtained from sources believed to be reliable. Gartner disclaims all warranties as to the accuracy, completeness or adequacy of such information. Gartner shall have no liability for errors, omissions or inadequacies in the information contained herein or for interpretations thereof. The reader assumes sole responsibility for the selection of these materials to achieve its intended results. The opinions expressed herein are subject to change without notice

3 Worldwide IC Package Forecast (Executive Summary) Worldwide IC Package Forecast: 11.3 Percent Unit Growth Expected in 2003 Gartner Dataquest has updated the worldwide integrated circuit (IC) package forecast, and the unit growth rate is estimated at 11.3 percent for this year in comparison with Total semiconductor IC package unit shipment volume is expected to grow to 90.3 billion in 2003 and will reach 106 billion in 2004, with growth of 17.5 percent year over year, as shown in Figure 1. In regard to the package type mix, the majority is of conventional package types, such as small outline and thin small outline package (TSOP) for analog and memory devices. Total small outline integrated circuit (SOIC) packages will grow at a 7.9 percent compound annual growth rate from 2002 through 2007, mainly destined for the "matured market," which utilizes the wellestablished infrastructure for the data processing market. On the other hand, total unit shipment volume is relatively small, but Gartner Dataquest estimates strong growth of high-density packages for the emerging market. Figure 1 Worldwide Semiconductor IC Package Forecast Millions of Units 140, , ,000 80,000 60,000 40,000 20,000 Others FBGA Bare Chip BGA SOIC QFP DIP BGA = ball grid array package DIP = dual in-line package FBGA = fine-pitch ball grid array QFP = quad flat package Source: Gartner Dataquest (August 2003) 2003 Gartner, Inc. and/or its Affiliates. All Rights Reserved. 1

4 2 Worldwide IC Package Forecast (Executive Summary) System-in-Package Will Lead the High-Density Packaging Technology Market System-in-package (SIP), consisting of flip chip in package (FCIP) and various other types of multiple-chip package (MCP) is diversifying its product mix to support various vertical markets. This is the critical trend for integrated device manufacturers (IDMs) and original equipment manufacturers (OEMs) to survive the transient market. High-density packaging technology has established the first phase of the "package revolution" with the flip chip interconnection infrastructure. The SIP can support the emerging market by offering the following advantages: Time to market Reasonable development cost Figure 2 System-in-Package Usage by Application Minimization of wiring resistance by multiple chips Use of three-dimensional (3-D) packaging to combine wafers made with different processes and different materials Direct power supply to high-wattage dies with stacking or side-by-side multiple chip packaging or package-level stacking As shown in Figure 2, the SIP will cover various applications. Digital cellular phones are leading the unit growth of SIP in the communication market and will contain two or three radio frequency (RF) and baseband processor SIPs beside the stacked-memory MCP. Also, massive growth is expected in the consumer market. Digital still cameras and other multifunctional mobile electronic products are showing strong unit growth, and the consumer SIP segment is expected to grow to 31 percent of total SIP usage (3.65 billion units) in Industrial (0.2%) Industrial (0.6%) Automotive (7.3%) Data Processing (19.8%) Communications (46.7%) Automotive (6.8%) Data Processing (18.0%) Communications (43.6%) Consumer (26.0%) Consumer (31.0%) Source: Gartner Dataquest (August 2003) 2003 Gartner, Inc. and/or its Affiliates. All Rights Reserved. 7 August 2003

5 Worldwide IC Package Forecast (Executive Summary) 3 While the communications SIP will grow at a 26.5 percent compound annual growth rate (CAGR) from 2002 through 2007, the consumer SIP will grow at a 32.1 percent CAGR. Total SIP unit shipment volume will grow at a 26 percent CAGR between 2002 and 2007, as shown in Figure 3. Gartner Dataquest expects that total SIP unit volume will reach 9.3 billion by From the viewpoint of SIP unit growth by package type, FCIP and multichip module (MCM) dominate in the SIP configuration. Among the FCIP types, FCIP fine-pitch ball grid array (FCIP-FBGA) is the prototype for the SIP configuration, and FCIP-FBGA covers multiple die combinations such as ASIC/ASSP plus memory and advanced memory plus logic. MCM covers various application arenas with side-by-side multiple die combinations such as application-specific integrated circuits (ASICs), digital signal processors (DSPs), memory modules, analog, passive and others. Even in the conventional package types such as SOIC, the SIP is configured in the TSOP for RF and baseband applications for digital cellular phones. Figure 3 System-in-Package Unit Growth by Package Type Millions of Units 10,000 9,000 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1, Others SOIC QFP PBGA/EPBGA MCM FCIP FBGA (W/B) EPBGA = thermally enhanced plastic ball grid array FBGA (W/B) = Fine-pitch ball grid array with a bare die that is wire-bonded to a package substrate Source: Gartner Dataquest (August 2003) Gartner Dataquest Perspective Multiple-chip and flip chip packaging are the leverage for the SIP configuration. IDMs and OEMs are getting focused to reinforce the intellectual property (IP) of packaging through the development of the SIP. The company that can provide the "system solution" by designing the SIP will lead the core SIP market. The other peripheral dies such as advanced memory, DSP, analog and passives will be optimized for the SIP configuration by the other IDMs and possibly be distributed in the market to shorten cycle time. For the distribution of the optimized dies, the minimum level of "cross-functional" standardization is necessary for the system design from the level of wafer process through final assembly and test functions within the high density packaging industry Gartner, Inc. and/or its Affiliates. All Rights Reserved. 7 August 2003

6 4 Worldwide IC Package Forecast (Executive Summary) Semiconductor assembly and test services (SATS) providers are at the critical stage to survive the transient market now. In regard to the SIP core technologycentric market, the horizontal specialized business model is changing its structure to the convergence business model in all directions. The SIP core technology-centric company will form new vertical and compound alliances with IDMs, OEMs, and SATS providers. The compound and flexible approach is critical to invigorate the packaging and assembly market via the SIP solution Gartner, Inc. and/or its Affiliates. All Rights Reserved. 7 August 2003