Power-Aware Task Scheduling for Dynamic Voltage Selection and Power Management for Multiprocessors

Transcription

1 Power-Aware Task Sceduling for Dynamic Voltage Selection and Power Management for Multiprocessors HyunJin Kim 1, Jin-o An 2, Hong-Sik Kim 1 and Sungo Kang 1 1 Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea 2 Department of Electronic Engineering, Hoseo university, Asan, Cungnam, Korea yunjin2.kim@gmail.com, ongsik@yonsei.ac.kr, jan@oseo.edu, and skang@yonsei.ac.kr Abstract Tis paper proposes a power-aware task sceduling algoritm for bot dynamic voltage selection and power management in multiprocessor environments. Based on te power profiling information, te algoritm for te task assignment and te task ordering in multiprocessor systems is provided. Moreover, a new priority-based task sceduling and linear programming models are proposed. Te best solution is searced wit tuning parameters. Experimental results sow tat four processors are sufficient to maximize energy savings for randomly generated applications. Moreover, te relationsip between dynamic voltage scaling and power management is provided by summarizing te energy savings. Keywords Power-aware system, Task sceduling, Dynamic voltage scaling, Power management, INTRODUCTION Energy consumption as become a primary concern in te state-of-te-art multiprocessor system. Te total power consumption of a multiprocessor system consists of a dynamic part from switcing activity and a static part from leakage current. In past tecnology, te dynamic power consumption as been muc larger tan te static power consumption. Wit te trend of srinking feature size, owever, te static power consumption will increase because te leakage current is predicted to increase by a factor of five [1]. Moreover, te static power consumption from leakage current will surpass te dynamic power consumption. To minimize total energy consumption, task computation energy-saving tecniques ave been researced. Hig-level task computation energy-saving tecniques implemented during te design process are more effective tan low-level tecniques [1]. Te main ig-level task computation energy-saving tecniques are te dynamic voltage scaling (DVS) and te power management (PM). Te DVS tecnique scales te voltage swing and te clock frequency of eac cycle of voltage-variable processors on te fly [1]; te PM tecnique sutdowns te power of eac PE or makes te processors dormant [3]. From te previous researc, it was known tat te DVS tecnique is more efficient tan te PM tecnique [4]. However, te coice about wic ig-level task computation energy-saving tecnique is preferred can be canged because te static power consumption increases. Moreover, te dynamic power consumption is dependent on te switcing activities, wic can be different according to te input vectors. Terefore, bot te dynamic power consumption and te static power consumption sould be considered to minimize total energy consumption. Some previous works focused on DVS to minimize total energy consumption by stretcing te computation time in te slack of an application [5] [6]. DVS was applied to te multiprocessor using linear programming (LP) formulation. Te static power consumption, owever, was neglected. Ravindar et al. proposed leakage-aware DVS for real-time embedded systems [1]. Te leakage-aware DVS, owever, did not consider te multiprocessor environments. Tis paper proposes a power-aware task sceduling algoritm for DVS and PM in multiprocessor environments. To minimize total energy consumption, a tuning parameter is used to calibrate te priorities of tasks. Te minimized total energy consumption can be obtained by sweeping te parameter. Experimental results sow te ratio of tasks at DVS mode is related to te energy-saving improvement, and te improvements of energy-savings are not always proportional to te amount of resources. Tis paper is structured as follows. In motivations, te combination of DVS and PM is explained. In power-aware task sceduling, te proposed algoritm is described in detail. In addition, experimental results and conclusion are provided. MOTIVATIONS Te power of a multiprocessor is consumed in eac processor. Te power model described in [1] of a processor is given by: P=P ac +P dc +P on, (1) were P ac is te dynamic power consumption due to te switcing activity, P dc is te static power consumption due to te leakage current, and P on is te intrinsic power consumption needed to keep te processor on. Te dynamic power consumption is given by: 2 P = αc V f, (2) ac normal dd were C is te normalized switcing capacitance, normal te switcing activities, V is te supply voltage, and dd α is f is 165

2 te operation frequency. Te static power consumption is given by: P = V I + V I, (3) dc dd sub bs j were I is te sub-tresold leakage current, V is te sub bs voltage applied between body and source, and I is te reverse bias junction current. From Equation (3), te dy- j namic power consumption is proportional to te operating frequency and te supply voltage. Te total energy needed in a cycle, owever, cannot be decreased because te static energy and te intrinsic energy are proportional to te cycle time and te supply voltage, not te operating frequency. Moreover, te dynamic power consumption of a processor can be canged according to te switcing activities. On te oter and, te dynamic power consumption is determined by te input vectors of applications. Terefore, we decide wic power consumption sould be reduced; i.e. te dynamic power consumption is reduced by DVS or te static power consumption is reduced by PM. Te coice is based on te information from te power profiling; i.e., after evaluating te power consumption of eac task in an application, te information about weter DVS or PM is preferred can be provided. If te switcing activity of a task is active, DVS can be preferred; oterwise, PM is preferred. Te supply voltage level and te operating frequency are predetermined wen DVS is applied; i.e., te values are discrete. Terefore, te information about weter DVS or PM is preferred can provided. POWER-AWARE TASK SCHEDULING To minimize total energy consumption in a multiprocessor, te dependency between tasks sould be considered. In addition, time constraints of tasks limit te amount of te reduced energy. Considering te constraints mentioned above, we propose an algoritm for minimizing total energy consumption in a multiprocessor. Te priority-rule based on earliest deadline first (EDF) is used to select a task to be sceduled. Te tuning parameter is introduced to calibrate te priority values of tasks in PM mode. Figure 1 sows te framework of te proposed algoritm. Figure 1. Framework of proposed algoritm For a given application and its power profiling information, power-aware task sceduling is performed. After poweraware task sceduling, total energy consumption is calculated wit te LP formulation. If an end condition is not satisfied, te value of PM mode tuning parameter is increased by a step. Te task sceduling and te calculation of total energy consumption are repeated until te end condition is satisfied. 4.1 Task Selection based on Priority Rule Te proposed algoritm extends te priority rule represented in priority-based task sceduling in [5], wic attempted not to make unnecessary long pats (dependent sets of ordered tasks). Te priority-based task selection gives more cances to minimize te computation energy consumption by allowing tasks to be constrained by small deadlines, and ten task computations to be stretced by DVS as muc as possible. Te process of priority-based task selection is as follows. Te last finis time of task T i, lft i, is defined as min ( dl i, lft j- NC is.t. i and edge ij edges), (4) were dli is te deadline of Ti and NCi is te execution cycle of Ti. Te earliest start time of Ti, es i, is defined as esi = max ( r i, min(ap js.t < i N + 1)), (5) were N is te number of processors, ap j is te available start time of a computation on te jt processor, and r i is te ready time (time wen te computations of predecessors complete) of T i. Te priority value, PRI, for eac unsceduled task is calculated. Te priority value can be defined as PRIi = ( lfti + esi) ( K + 1), (6) were K is te PM mode tuning parameter. One unsceduled task wit te smallest PRI is selected. Te selected task is mapped on a processor. 166

3 4.2 Task Mapping and Ordering To scedule tasks in an application onto a given number of processors according to te deadline and te dependencies (task sceduling), eac task is assigned onto a processor (task assignment), and ten tese assigned tasks in a processor are ordered in time slots (task ordering). Te task sceduling of a selected task, terefore, consists of task mapping and task assignment. Te process of task mapping is follows. Task T i is assumed to be selected in task selection. T i is mapped on te earliest available processor wen r i is earlier tan te processor available time. T i is mapped on te latest available processor at r i wen r i is later tan or te same as te PE available time. After selecting te processor in task mapping, te starting time of te mapped task is determined by task ordering. If r i is later tan or equal to te available start time of te selected processor, te task is ordered to start from r i ; oterwise, te available start time of te selected processor is te start time of T i. Figure 2 sows task mapping and ordering of a task. For example, after sceduling T 1 and T 2, T 3 is mapped on P 2 because te ready time of T 3 is faster tan te available start time of P 1. Moreover, T 2 and T 3 are ordered as close as possible. T 5 is mapped on P 1 because te available start time of P1 is closer to te task ready time of T 5 tan te available start time of P 2. Figure 2. Example of task mapping and Sceduling After task ordering, te sceduled task is removed from te list of candidate tasks. Ten, te time constraint of te sceduled task is cecked to see if task sceduling is valid; if te task sceduling is not valid, te task sceduling is restarted from te original task grap. Te proposed algoritm repeats te loop to find a set of sceduled tasks. Te set of sceduled tasks are used to calculate total energy consumption using te LP formulation. 4.3 Total Energy Calculation wit LP Formulation After obtaining a set of sceduled tasks, te voltage mode for eac task is selected using te LP formulation. We modify te LP formulation in [5] to calculate te task computation energy to support DVS and PM. Figure 3 sows constraints for te LP formulation considering DVS and PM. In Figure 3, symbol Ex means execution time according to te voltage level: ig or low, symbol D means te start time of a task, symbol dl means deadline of a task. If (mode( Ti) == PM){ = ( v ); Di - Dj = ( v ) s. t. edge edge; ij Di + dli;} Else if (mode( Ti) == DVS){ ( v ) ( v ); l Di - Dj ( v ) s.t. edgeij edge; Di + dli;} Figure 3. Constraints for LP formulation If task T i prefer PM, T i is executed on te processor supplied wit ig supply voltage. DVS is not advantageous over PM, so tat tere is no reason to execute processor wit low supply voltage. Moreover, te processor sutdown after executing te task can save more energy. If task T i prefers DVS, te voltage level of eac cycle wen T i is executed is selected. LP solver calculates total energy consumption wit te constraints sown in Figure 3, were te start time of eac task and te voltage level of eac task are acquired. Te implementation of te proposed algoritm adopts te Application Program Interface (API) functions of te lp_solve [7]. Te value of PM mode tuning parameter is started from zero. Te best solution can be searced by comparing eac solution wit its neigborood solution in an iterative manner. Te values of step and range sould be predetermined. Even toug various euristic approaces can be combined, it is assumed tat te end condition is set as fixed 100 iterations wit increasing te tuning parameter by 0.1. EXPERIMENTAL RESULTS Te proposed algoritm was implemented by te C++ language, te boost grap library, and standard template library (STL). Te implementation was compiled and evaluated using te Microsoft Visual C++, and a PC wit a 1.86GHz Intel Core2 Duo processor and 2GByte RAM. 4.1 Experimental Environments To evaluate te proposed algoritm, six random applications as a set of bencmarks were generated by a pseudorandom task grap generation tool [8]. Te CTG bencmark in te tgff format [8] was used for te experiments. Te number of execution cycles of eac task was between 50 and 350. Te number of tasks and edges, and te deadlines of te applications are listed in Table 1. Te information for a multiprocessor system was based on te data of te ARM 11 processors [6]. Te experiments were performed in two different voltage modes: te ig 167

4 voltage mode at v and te low voltage mode at v l. Te cycle time at v was one time unit; te cycle time at v l was two time units. Tere were two types of energy consumption: 40pJ/cycle of te computation energy consumption at te ig voltage mode, 13.3pJ/cycle of te computation energy consumption at te low voltage mode. We assumed tat te switcing activities of tasks at DVS mode and tasks at PM mode are te same. Simply, DVS was not applied to tasks at PM mode. Te sutdown overead and power consumption in a sleep mode were neglected. We implemented a mode generator wic assigns DVS or PM mode to tasks randomly. Te percentage of DVS tasks was parameterized to evaluate te energy savings according to te ratio of DVS tasks to PM tasks. 168

5 Table 1. Properties of task graps Name #Tasks #Edges Deadline 1_TG _TG _TG _TG _TG _TG Performance Evaluation Table 2 sows te evaluation results wen te multiprocessor wit four processors was adopted and te percentage of DVS tasks was 50%. Te energy savings were measured by te amount of te energy reduced from te original energy consumption. From Table 2, te average energy saving is 38.37%. Table 2. Energy Savings for a multiprocessor wit four processors and 50% DVS tasks Name Original(pJ) Proposed(pJ) Savings (%) 1_TG _TG _TG _TG _TG _TG REFERENCES To evaluate te effect of resource constraints, we evaluated our algoritm in tree cases: tree, four, and five processors. Table 3 sows te energy savings cases wen tree, four, and five processors are adopted, respectively. Te energy savings wen te multiprocessor wit tree processors is adopted are 29.58% on average. Te energy savings wen te multiprocessor wit five processors is adopted are not improved compared to tat wit four processors. Terefore, four processors are sufficient to save total energy consumption for te six applications. Table 3. Summary of Energy Savings wit various multiprocessors and 50% DVS tasks Name Tree (%) Four (%) Five (%) 1_TG _TG _TG _TG _TG _TG Te effect of te ratio of DVS tasks to PM tasks was evaluated. Te energy savings were evaluated wen te percentage of DVS tasks was 60% and te multiprocessor wit four processors was adopted. As sown in Table 4, te energy savings wen tree, four, and five processors are adopted are provided. Te summary means te energy savings can be improved wen te resource constraints are more relaxed and te ratio of DVS is iger. Te improvement, owever, is not proportional to te ratio of DVS tasks. Table 4.Summary of Energy Savings wit various multiprocessors and 60% DVS tasks Name Tree (%) Four (%) Five (%) 1_TG _TG _TG _TG _TG _TG CONCLUSION Tis paper proposes a power-aware task sceduling algoritm for bot DVS and PM in multiprocessor environments. Te proposed algoritm provides a new prioritybased task sceduling and linear programming models. Te neigborood searc wit te PM tuning parameter provides te best solution. In experimental results, te proposed algoritm can be applied wen various resource constraints and ratios of DVS tasks to PM tasks are adopted. It is sown tat te multiprocessor wit four processors is sufficient to maximize energy savings for randomly generated applications. Moreover, te relationsip between DVS and PM is provided by summarizing te energy savings. [1] Jejurikar, R., et al., Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems, in Proc. of te Design Automation Conference, Jun. 2004, pp [2] Candrakasan, A. and Brodersen, R., Low Power Digital CMOS Design, Kluwer Academic Publisers, [3] Benini, L., et al., A survey of design tecniques for system-level dynamic power management, IEEE Trans. on VLSI systems, vol. 8, Jun. 2000, pp [4] Hong, I., et al., Power Optimization of Variable- Voltage Core-Based Systems, IEEE Trans. on CAD, vol. 18, dec. 1999, pp [5] Zang, Y., et al., Task sceduling and voltage selection for energy minimization, in Proc. of te Design Automation Conference, Jun. 2002, pp [6] G. Varatkar, R. Marculescu, Communication-aware task sceduling and voltage selection for total systems energy minimization, in Proc. of Int l Conf. on Computer-Aided Design, Nov. 2003, pp [7] lp_solve reference guide, ttp://sourceforge.net/project/, ver [8] Dick, R., et al., TGFF: task graps for free. in Proc. of Int l Worksop on Hardware/Software Codesign, Mar. 1998, pp