ewlb (embedded Wafer Level BGA) Technology: Next Generation 3D Packaging Solutions

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1 ewlb (embedded Wafer Level BGA) Technology: Next Generation 3D Packaging Solutions by Seung Wook Yoon and Meenakshi Padmanathan STATS ChipPAC Ltd. Andreas Bahr Infineon Technologies AG Xavier Baraton STMicroelectronics Flynn Carson STATS ChipPAC Inc. Fremont, CA, USA Originally published in the International Wafer Level Packaging Conference Proceedings, Santa Clara, California, USA, October 27-30, Copyright The material is posted here by permission of the SMTA - The Surface Mount Technology Association. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 ewlb (EMBEDDED WAFER LEVEL BGA) TECHNOLOGY: NEXT GENERATION 3D PACKAGING SOLUTIONS Seung Wook Yoon and Meenakshi Padmanathan STATS ChipPAC Ltd. Andreas Bahr Infineon Technologies AG Xavier Baraton STMicroelectronics Flynn Carson STATS ChipPAC Inc. Fremont, CA, USA ABSTRACT Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fanout packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. ewlb (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D ewlb technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D ewlb can be implemented with through silicon via (TSV) applications as well as discrete component embedding. Keywords: ewlb, Fan-out Wafer Level Packaging, Wafer Level Packaging, 3D packaging, 3D SiP INTRODUCTION Electronic products continue to find new applications in personal, portable, healthcare, entertainment, automotive, environmental and security systems.[1] Advancements in packaging co-design, low-cost materials and reliable interconnect technologies are critical in enabling the innovative packaging solutions required to help drive the industry forward. Packaging semiconductor devices is becoming a challenge for the industry. As process technologies become smaller, so too do the devices which are being made with those processes. Moreover, interfacing the chip to the outside world becomes equally problematic. Mobile phone developers, for one, are looking for devices that not only have the minimum footprint possible, but which also are as thin and light as possible. This paper will highlight some of the recent advancements in 3D ewlb packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging. The advantage of 3D ewlb technology and applications of 3D packaging will be presented with several examples. The process flow of 3D ewlb fabrication, assembly and packaging challenges, and performance characteristics will be also discussed. 160

3 thermal issues related to power consumption and the device's electrical performance (including electrical parasitic and operating frequency). Figure 1. Driving force for wafer level packaging WLP applications are expanding into new areas and are segmenting based on I/O count and device. The foundation of passive, discrete, RF and memory device is expanding to logic ICs and MEMS. The WLP segment has matured over the past decade, with numerous sources delivering high-volume applications across multiple wafer diameters and expanding into various end-market products. With infrastructure and high volumes in place, a major focus area is cost reduction. One of the most well known examples of a fan-out WLP structure is ewlb technology. This technology uses a combination of front- and back-end manufacturing techniques with parallel processing of all the chips on a wafer, which can greatly reduce manufacturing costs. Its benefits include a smaller package footprint compared to conventional leadframe or laminate packages, medium to high I/O count, maximum connection density, as well as desirable electrical and thermal performance. It also offers a high-performance, power-efficient solution for the wireless market.[2] Figure 3. ewlb wafer after packaging with reconstruction, RDL and backend processes. Figure 4. SEM micrographs of cross-section of ewlb.[3] Figure 2. Comparison of FI-WLP and ewlb (FO-WLP) ewlb TECHNOLOGY ewlb technology is addressing a wide range of factors. At one end of the spectrum is the packaging cost along with testing costs. Alongside these are physical constraints such as its footprint and height. Other parameters that were considered during the development phase included I/O density, a particular challenge for small chips with a high pin count; the need to accommodate systems in package (SiP) approaches, The obvious solution to the challenges was some form of wafer level packaging (WLP). But two choices presented themselves: fan-in or fan-out. Fan-in WLP is an interconnection system processed directly on the wafer and compatible with motherboard technology pitch requirements. It combines conventional front- and backend manufacturing techniques, with parallel processing of all chips. There are three stages in the process. Additional fab steps create an interconnection system on each die, with a footprint smaller than the die. Solder balls are then applied and parallel testing is performed on the wafer. Finally, wafers are sawn into individual units, which are used directly on the motherboard without the need for interposers or underfill. The ewlb approach should not be confused with bumped flip chip devices which have a finer pitch, smaller bumps and which need underfill. 161

4 important features. Transition to ewlb packaging technology enables a significant reduction in recurring costs by eliminating the need for expensive substrates. Figure 5. ewlb technology for bridging the interconnection gap between device level and board level interconnections. ewlb, meanwhile, is a fan-out process. The die is surrounded by a suitable material, which spreads the package footprint outside the die. Tested good dice are embedded in an artificial plastic wafer (reconstituted wafer) using a wafer level molding technique. Front end isolation and metallization processes are then used to fanout the interconnections to the surrounding area with lithography and patterning wafer level processes. Again, solder balls are applied and parallel testing is performed on wafer. The reconstituted wafer is then sawn into individual units, which are packed and shipped. With the fan-in approach, the number of interconnects and their pitch must be adapted to the chip's size. ewlb, by contrast, supports a fan out area which is adaptable and which has no restriction on ball pitch. Advantage of ewlb The advantage of ewlb packaging can be summarized as below; No substrate required Miniaturized and high performance package Green packaging (Pb-free and Halogen-free) Cu/low-k compatible packaging technology Full module approach with free top surface (Thin Package-on-Package(POP), SMD compatible) Batch process of wafer level including wafer level test Embedding die in mold during assembly/packaging Simple logistics and supply chain Enabling 3D IC packaging The current BGA package technology is limited by the organic substrate capability. Moving to ewlb helps overcome such limitations and also simplifies the supply chain. Building the substrate on the package itself, if you will, allows for higher integration and routing density is less metal layers. ewlb is a next generation platform that will support future integration, particularly for wireless devices and this packaging technology has a number of BGA packaging also faces a challenge with technology nodes beyond 65nm as the device performance density drives the need for flip chip. But advanced flip chip nodes drive fine pitch combined with weaker low K dielectric structures resulting in flip chip becoming narrower in terms of process margin,. In addition, there is a big trend in being environmentally friendly, driving lead free and halogen free, or green, material sets. With ultra low-k and interconnects pitch becoming smaller and smaller and with the shift to lead free materials, the technical limitations faced by the packaging industry are becoming more challenging. ewlb technology provides a window for packaging next generation devices in a generic, leadfree/halogen free, green packaging scheme. NEXT GENERATION; 3D ewlb TECHNOLGOY A. Next Generation ewlb The first generation of ewlb technology was designed for a single side and 1-RDL approach. To address the advanced requirements in the market for higher performance and design complexity, new technical items and envelops should be developed and implemented into the current ewlb technology as shown below; Double-side ewlb with vertical interconnection: Both sides of reconstituted wafer have isolation and metal layers, connected by means of conductive vias in the plastic portion of the wafer; Multi-layer RDL ewlb: More than one metal layer can be present in both sides; Large size ewlb: Package size is increased to 12x12mm 2 Thin ewlb : Package thickness is reduced to 0.5mm Multichip ewlb : More than one chip is embedded Multi-layer RDL ewlb In situations where a device may have an interconnect pad arrangement or a flip chip or wafer level component, an additional layer of lateral connections may be employed to rearrange the connections in a manner suitable for wafer level processing. This additional layer is known as a redistribution layer or RDL and fabricated from a thin layer of metal with dielectrics in between. RDL is for higher electrical performance and complex routing to meet electrical requirements. It also can provide embedded passives (R, L, C) using a multi-layer structure as shown in Figure 7. Excellent performance of transmission lines (TMLs) was reported in manufacturing ewlb (Insertion loss GHz, GHz)[4]. Inductors in ewlb offer significantly 162

5 better performance compared to inductors in standard onchip technologies as shown in Fig. 7(a). Further improvement of the quality factor of the integrated capacitors by using low-loss thin-film dielectrics on ewlb was reported as well.(fig.7(b)) There was another report that a 77 GHz SiGe mixer packaged as an ewlb had excellent high frequency electrical performance due to the small contact dimensions and short signal pathways which decreased parasitic effects.[5] removing of Si/epoxy material together using the same process steps. (a) Figure 8. Thin ewlb after ewlb packaging process. (b) Multi-chip ewlb Packaging Side-by-side multichip packaging can provide more design flexibility for SiP applications because a chip designer has more freedom in pad location as well as circuit block allocation. 3D ewlb technology utilizes very fine pitch metal line width and space as well as multi-layer RDL process, so it provides better technical solutions for multi-chip packaging. (a) Figure 6. SEM micrographs of ewlb package of (a) single RDL and (b) double RDL. (a) (b) (b) Figure 7. Embedded Passives on ewlb wafers ; (a) Single-Layer Spiral Inductors and (b) Interdigital capacitors. [4] Thin ewlb Packaging For mobile and handheld applications, portability is a critical factor for product selection. The thinner package can provide better board level reliability as well as lighter and thinner profile in system level. Using advanced thinning technologies, ewlb was thinned down to 250 m thickness as shown in Figure 8. The critical technical challenges were handling the thin wafer and grinding and Figure 9. (a) Schematics of 2-die multichip ewlb and (b) SEM micrograph of cross-section of completed mold filling between two chips. Double-side ewlb Packaging In the next generation of ewlb, both sides of the reconstituted wafer will have isolation and metal layers, 163

6 connected using conductive vias. More than one metal layer can be included and package size will be increased to 12 x 12mm 2, with thickness reduced to 0.5mm. In addition, it may be possible to embed more than one chip. (a) (b) Figure 10. Applications of double-side ewlb packaging; (a) Package-on-package (PoP) and (b) System-on-Wafer (SOW). 3D packaging using the z-axis TSV stacking concept has been and continues to be investigated by a number of semiconductor manufacturers and research institutes and is believed to be one of the most promising technologies. There is a growing interest in the development and application of this new chip stacking approach to existing and future devices. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes. Applications have to be well understood and integrated in order to successfully be applied. But still there are obstacles and barrier to overcome for mass production of TSV assembly and packaging beside TSV formation challenges, such as bonding/debonding process for temporary thin wafer handling, and microbump interconnects for assembly and packaging. 3D ewlb with TSV Technology TSV is typically not a packaging solution by itself. TSV uses only back-end manufacturing techniques such as bonding, fine pitch bumping, back grinding and thin wafer handling. Final packaging is required to connect the device to the PWB.[7] Due to assembly constraints, the choice of the final package solution could impact the entire TSV process flow. This final packaging could be a BGA package, a fan-out WLP type, an embedded die in substrate (EDS), or other. Here, it is interesting to notice how complementary 3D IC configurations with TSV and 3D packaging can be. In effect, 3D ewlb can enable designs to fully benefit from the 3D IC integration and can reduce the package footprint with more aggressive design rules than BGA packages. Figure 11. Double-side ewlb wafer with vertical interconnections. 3D ewlb WITH TSV (THROUGH SILICON VIA) TECHNOLOGY Demand for through silicon via (TSV) is being driven by the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies.[6] Figure 12. Schematics of 3D ewlb packaging with TSV for 3D SiP applications. TSV is a new technology and 3D ewlb is a new packaging technology as well. TSV is not limited to BGA types of packages. Some constraints can even be relaxed by coupling 3D IC TSV with 3D advanced packaging and then the full benefits of TSV can emerge. New opportunities should emerge and be realized in view of cost, yield, functionality, process flow as well as 164

7 performance characteristics of TSV and 3D ewlb. Using a 3D ewlb approach with TSV may offer advantages such as: Eliminating TSV thin wafer handling issues Integrating TSV & ewlb Technology for 3D vertical interconnections Integrating Memory & ASIC/ Processor and heterogeneous functional integration in one package as well as at the wafer level Utilizing micro-bump and micro bonding process for interconnection Further Wafer Level Integration with 3D ewlb for Heterogeneous Functionality There is a need for miniaturization at the IC, module (or sub-system), and system levels. At the IC level, scaling continues as it has over the last four decades according to Moore's Law. In addition, 3D chip stacking technology with through silicon vias (TSVs) has garnered a lot of attention recently due to its potential in improving the performance, form factor, cost, and reliability at the subsystem or module level. There is still a great deal of research and development required to bring this heterointegration technology to cost-effective implementation with the required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system. [8] Although active and stacked ICs are a highly functional and important component of the overall system, they are only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely met by the current technology domain in the areas of through silicon vias (TSVs), 3D stacking, and wafer level packaging. There should be further study on integration, focusing on TSVs, 3D stacking and 3D ewlb with better electrical and thermal performance, greater system reliability, and reduced form factor and overall cost. It will go far beyond this to realize a truly seamless wafer level integrated 3D packaging module as shown in Fig. 13, that will incorporate aspects of 3D stacking, as well as Si package with embedded passive, actives in 3D ewlb packaging with TSV, flip chip, and microbump as well as 3-D WLPs. Figure 13. Total solutions for 3-D packaging with ewlb(fo-wlp) and TSV technology. [9] CONCLUSION Advanced packaging plays a crucial role in driving products with increased performance, low power, lower cost and smaller form factor. There are challenges associated in the application of cost effective materials and processes for various reliability requirements. The industry requires innovation in packaging technology and manufacturing to meet current demands and the ability to operate equipment in high volume with large throughput. ewlb technology is an enhancement to standard WLPs, allowing the next generation of a WLP platform due to its fan-out capability. The benefits of standard fan-in WLPs such as low packaging/assembly cost, minimum dimensions and height as well as excellent electrical and thermal performance are true for ewlb as well. The ability to integrate passives like inductors, resistors and capacitors into the various thin film layers, active/passive devices into the mold compound and 3D vertical interconnection opens additional design possibilities for new Systems-in-Package (SiP) and 3D stacked packaging. Moreover, 3D ewlb technology provides more value-add in performance and promises to be a new packaging platform that can expand its application range to various types of devices as well as 3D TSV integration for true 3D SiP systems. As the world demand for portable electronics has accelerated, the need to make semiconductors smaller, faster, lighter and cheaper has never been greater. As witnessed by the dramatic evolution of cellular phones, product differentiation today is driven by ever-expanding functionality, feature sets, multi-functionality and faster communications. At the same time, consumers have made clear their desires for feature-rich products in compact form factors to enable maximum portability. ewlb technology is successfully enabling semiconductor manufacturers to provide the smallest possible, highestperforming semiconductors. 165

8 REFERENCES [1] Mahadevan Iyer, Emerging Trends in Advanced Packaging, Semiconductor International, p.26-31, June 2009 (2009) [2] Graham pitcher, Good things in small packages, Newelectronics, 23 June 2009, p18-19 ( 2009) [3] M. Brunnbauer, et al., Embedded Wafer Level Ball Grid Array (ewlb), Proceedings of 8th Electronic Pacakging Technology Conference, Dec 2009, (2006) [4] Maciej Wojnowski, Klaus Pressel, Grit Sommer, Mario Engl, Package Trends for Today s and Future mm-wave Applications, EuMIC 2008, 38th European Microwave Conference [5] M. Wojnowski1, M. Engl, B. Dehlink, G. Sommer, M. Brunnbauer, K. Pressel, and R. Weigel, A 77 GHz SiGe Mixer in an Embedded Wafer Level BGA Package, Proceedings of 50th ECTC, p , May 2008, (2008) [6] Seung Wook YOON, Dae Wook YANG, Jae Hoon KOO, Meenakshi PADMANATHAN and Flynn CARSON, 3D TSV Processes and its Assembly/Packaging Technology, IEEE 3D Conference 2009, September, 2009, San Francisco, CA, US (2009) [7] Yann Guillou, 3D Integration for wireless products; industrial perspective, Newsletter on 3D Packaging, Yole development, July 2009, p.2-4 (2009) [8] Ritwik Chatterjee and Rao R. Tummala, 3D Technology and Beyond: 3D All Silicon System Module, Advanced Packaging, ( none/indus/1/3d-technology-and-beyond:-3d-all- Silicon-System-Module/) [9] Newsletter on 3D Packaging, 3D IC, TSV, WLP & Embedded Technologies, MARCH 2009, No.10, Yole Development (2009) 166