QFN PACKAGES. Introduction to the QFN. Varieties offered for PC Audio Codecs. Board design APPLICATION NOTE. 32-pin leadless package

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1 APPLICATION NOTE QFN PACKAGES 32-pin leadless package Introduction to the QFN The QFN (Quad Flat No lead) package is a near chip scale plastic encapsulated package related to the plastic quad flat package. This style of package comes in several varieties and is known by several names such as MLF, LPCC, and VQFN and is defined by JEDEC specification MO-220 (currently at issue I.) This package is leadless meaning the leadframe does not extend outside of the defined body of the part. Electrical contact with the PCB is made by soldering the lands on the bottom side of the package to the PCB instead of conventional leads. The package also exposes the die attach paddle as an effective thermal attach pad, and is considered a thermally enhanced package. The QFN package is available in both punch and saw singulated formats. The design practices used in this document are intended to support both punch and saw singulated packages, but the dominant singulation format employed by former SigmaTel codecs (now IDT Codecs) is the punch singulation technique. Also note that although we do not currently offer saw singulated packages with lead pullback, the information presented should also be acceptable for those packages Varieties offered for PC Audio Codecs There are currently 8 variants defined by the JEDEC specification for the 5x5mm 32 pin package and 8 variants defined for the 7x7mm 48 pin package. (MO-220 Issue I.) Currently, we support only 3 variants of the 32 pin package (VHHD-2, VHHD-4, VHHD-5) with VHHD-2 being dominant, and only the VKKD-2 variant for the 48 pin package. Board design Decal overview (32 pin example) The decals supplied by IDT were designed by an independent contract design service using industry standard practices and our suppliers recommendations. The information presented here has been used successfully on a modern automated assembly system. However, it must be emphasized that the following information is for reference only and is offered as a guideline for developing a proper design and assembly process that meets the requirements and practices of the PCB manufacturer. Land size pin QFN package dimensions The 32 pin packages used by IDT have the dimensions outlined in the table below. The 3 supplied packages are the VHHD-2, VHHD-4, and VHHD-5 variants. Variation D2min D2max E2min E2max bmin bmax Lmin Lmax e D E VHHD VHHD VHHD IDT QFN PACKAGES 1 REV A

2 ZDmax D2 CLL CDL b ZEmax GEmin Y E E2 e X L GDmin D Figure 1 - Package dimensions Figure 2 Land References PCB Decal land dimensions The PCB land pattern dimensions to be generated are referenced in Figure 2 - Land References. The dimensions ZD max and ZE max are the outside to outside land extents. GD min and GE min are the inside to inside dimensions. Dimension X represents the width of the land and Y represents the length of the land. C LL is the distance between corner lands, and C DL is the distance from the inside end of the land to the die attach pad on the package. (Vertical height is ignored. If a thermal pad were defined on the PCB, then this measurement would be the minimum spacing between the land and the thermal pad.) The C LL and C DL measurements are clearances defined to help avoid solder bridging Suggested Land Pattern (decal) The suggested land pattern is based on the following assumptions: The QFN leads are embedded in the mold compound on three sides and fillets cannot form on these sides. The fourth side, although exposed, is not plated and fillet formation is not guaranteed, therefore voids may exist. (See Figure 6- Toe Fillet.) However, since the land pattern is likely to be larger than the actual lead dimensions, the solder joints may assume fillets illustrated in Figure 3-Fillets. The toe fillet, if formed, will improve the solder joint reliability. IDT SIGMATEL QFN 2 REV A

3 Figure 6 - Toe fillet Heel Toe Side Figure 5 - Land Pattern dimensions Figure 3 Fillets Minimum solder fillet dimensions: Toe > 0.1mm Heel> 0.0mm (worst case) Side = 0.0mm PCB fabrication tolerance = 0.05mm Package placement tolerance = 0.05mm Using the above, IPC-SM-782A tolerance guidelines, and package suppliers recommended dimensions, the following land dimensions (from Figure 2) were chosen: X = 0.30mm (suppliers recommendations ranged from 0.28mm to 0.31mm) Y = 0.75mm (suppliers recommendations ranged from 0.67mm to 0.69mm) Figure 4 - Pad detail The pads have been intentionally extended to help prevent solder bridging between adjacent pins and between the lands and the package die attach pad. IDT SIGMATEL QFN 3 REV A

4 Solder mask The solder mask is to be 0.1mm ( ) larger than the lands in x and y directions. The solder mask creates a web between the lands which can help prevent solder bridging. Also, the use of a mask beneath the part will create an effective dam to help prevent bridging between the exposed die attach pad on the package and the lands on the PCB. While 0.2mm or larger clearance is desired between the exposed die attach pad and the lands, it is common for the VHHD-4 package to achieve less than 0.1mm clearance using the above decal. Solder bridging has not been an issue as long as an appropriate solder past stencil was used in the assembly process. (See below.) Solder Mask Stencil size A stencil thickness of 5 mils (0.005 or mm - electropolished) is recommended. The use of thicker stencils increases the risk of die attach pad to pin shorts during the assembly process. Thermal PAD Although attaching the die attach pad is not required for thermal or electrical reasons, it can provide benefits. Attaching the die attach pad on the package to a thermal attach pad on the PCB can reduce the stress on the peripheral pads and decrease the thermal resistance by a factor of about 2x. (ASAT) However, even when there is no thermal attach pad on the PCB, the die attach pad is still present on the package. A clearance of at least 0.15mm between the die attach pad and the inner tip of the land patterns will help avoid shorts. (ASAT) IDT SIGMATEL QFN 4 REV A

5 Rework Device removal Generally, it is recommended to preheat the PCB to prevent board warp. However, when the package die attach pad is not soldered to the PCB (as in the above decals), it should not be necessary to pre-heat the board, and either BGA or QFP removal techniques may be employed to remove a package. A forced air rework tool such as systems offered by Metcal and Hakko, is used to heat all sides of the component equally. Once the solder has completely reflowed, the component is typically removed using a vacuum nozzle. Care must be taken when removing packages by hand because, if the solder has not completely reflowed, pads may be lifted from the PCB. The use of flux during reflow is highly recommended. After the package has been removed, gently remove any residual solder from the PCB lands. Apply paste flux directly to the lands and, using a temperature controlled iron with a flat tip, gently apply solder braid to the PCB pads. Clean the site using alcohol and a lint free swab or wipe to remove debris and residual flux. Inspect the site before replacing the package. Device replacement Always clean and inspect the PCB before mounting the component. Using a stencil, apply paste solder directly to the PCB. Identify the proper package orientation and use an automated, or semi-automated, rework system if available to align and place the component. Hand placement is possible, but not recommended due to the high likelihood of creating solder bridges between the package die attach pad and the leads because of poor placement. Using automated rework equipment is highly recommended. Follow the reflow profile for the paste used and use a board pre-heater to reduce the risk of warping the board during the reflow process. Other considerations Lead finish IDT offers QFN packages with either SnPb or Matte Sn (on Pb free and Environmental package options) lead finishes. Currently, no significant differences have been found between the Pb and PB free lead finishes with respect to assembly. The Pb free packages may be used in a Pb free assembly process or a Pb based assembly process. References LPCC APPLICATION NOTES ASAT Holdings Limited Application Notes for Surface mount Assembly of Amkor s MicroLeadframe (MLF) Packages Amkor Technology. MO-220 Issue I JEDEC Solid State Technology Association Toe fillet picture courtesy of Silicon Hills Design Inc. IDT SIGMATEL QFN 5 REV A

6 QFN PACKAGES Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: Corporate Headquarters Integrated Device Technology, Inc Silver Creek Valley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA