Platform Flash PROM VOG48 Package Lead Finish Conversion to NiPdAu

Transcription

1 Platform Flash PROM VOG48 Package Lead Finish Conversion to NiPdAu Qualification Report

2 Xilinx is disclosing this Qualification Report (the Documentation ) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 05/13/ Initial Xilinx release. Lead Finish Conversion Qualification Report

3 Table of Contents Overview Summary Qualification Plan Qualification Test Summary Board-Level Reliability Test Summary Lead Finish Conversion Qualification Report 3

4 4 Lead Finish Conversion Qualification Report

5 Test Data and Results Overview This qualification report summarizes the reliability test results used to qualify Nickel Palladium Gold (NiPdAu) as a leadframe finish. The NiPdAu finish replaces the matte tin finish previously used on leadframes in VOG48 48-lead TSOP packages. The affected devices are Platform Flash in-system programmable configuration PROMs, and are listed in Table 1. Table 1: Affected Devices Device XCF08P-VOG48C XCF16P-VOG48C XCF32P-VOG48C XQF32P-VOG48M XCF08P-VOG48C4019 XCF16P-VOG48C4019 XCF32P-VOG The die attach material and mold compound have also changed and are listed in Table 2. Table 2: VOG48 Bill of Material Changes External Lead Finish Die Attach Material Mold Compound Original VOG48 Package Matte tin QMI509 KE-3300D VOG48 with NiPdAu leadframe finish NiPdAu QMI519 KE-G3000RH These changes are required to ensure supply continuity because the device supplier (Numonyx B.V.) has converted the affected devices (Table 1) to the NiPdAu finish. Summary The device samples tested for this qualification meet all qualification requirements, and the device/packages listed in Table 1 are qualified for production. The qualification test data and the resulting outcome for each test are summarized in Qualification Test Summary. Lead Finish Conversion Qualification Report 5

6 Qualification Plan Qualification Plan XCF32P devices in VOG48 packages are used as qualification vehicles. The selection of a qualification vehicle is based on package size, die size, pin count, and known reliability risk factors. Selected reliability stress tests are run on a sample population of qualification vehicles. Upon completion of the tests on the qualification vehicles, the other devices are qualified by similarity. Table 3 lists the qualification vehicles and the devices qualified by similarity. Table 3: Device and Package Qualification Type Device Package Qualification Type XCF32P VOG48 Qualification vehicle XCF16P VOG48 Qualified by similarity XCF08P VOG48 Qualified by similarity Qualification Test Summary Samples of the qualification vehicles were subjected to the tests listed in Table 4. Based on the data gathered from these tests, the device samples pass reliability requirements and are qualified for production. Table 4: Qualification Test Conditions and Results Stress Test Test Specification Test Conditions/Description Sample Quantity Number of Failures Results Moisture sensitivity level (MSL) preconditioning JEDEC J-STD-020D Level 3: 192 hrs., 30 C/60% RH All samples 0 Temperature cycle, condition C (TCC) JEDEC JESD22-A C to 150 C, 500 cycles (FYI to 1,000 cycles), MSL 3 preconditioning performed prior to test High temperature storage (HTS) JEDEC JESD22-A C, 1,000 hours 77 0 Highly accelerated temperature and humidity stress test (HAST) JEDEC JESD22-A C/85% RH, 1,000 hrs., V CC Max, MSL 3 preconditioning performed prior to test Wire pull MIL-STD-883, TM2011 Assembly wire pull, and wire pull after TCC and HTS 5 0 CSAM and T-SAM inspection Performed before and after 500 TCC All samples 0 Solderability JEDEC JESD22-B102E Method 1: Dip and look test, 8 hours steam age, SnPb and SnAgCu solder Method 2: Surface mount process simulation, SnPb and SnAgCu solder paste Group B solderability MIL-STD-883, TM C, test condition A, 22 leads per device Lead Finish Conversion Qualification Report

7 Board-Level Reliability Test Summary Table 4: Qualification Test Conditions and Results (Cont d) Stress Test Test Specification Test Conditions/Description Sample Quantity Number of Failures Results Group D subgroup 1 subgroup 2 subgroup 3 Physical dimensions 15 0 Lead integrity, B2, 45(0) leads 3 0 Thermal shock, condition B, 15 cycles 15 0 Temperature cycle, condition C, 100 cycles Moisture resistance Visual inspection Endpoint electrical test subgroup 4 Mechanical shock 15 0 Vibration Constant acceleration, E, Y1 only Visual inspection Endpoint electrical test subgroup 5 subgroup 7 Salt atmosphere/visual inspection 15 0 Adhesion of lead finish, 15(0) leads 3 0 Board level reliability IPC-9701 See Board-Level Reliability Test Summary 45 0 Board-Level Reliability Test Summary Board-level reliability (BLR) temperature cycle data was collected on VOG48 packages having NiPdAu leadframes and on VOG48 packages having matte tin leadframes. The packages having matte tin leadframes served as a control. The temperature cycle test conditions were: Temperature range: 40 C to 125 C Dwell: 10 minutes Ramp: 5 minutes Continuous resistance monitoring was used. The test board design details are listed in Table 5. Table 5: Test Board Details Parameter Value PCB material Overall board dimensions Daisy chain routing Standard JEDEC BLR Board, FR4/RCC 132 mm x 77 mm x 1 mm Daisy chains routed on the top and bottom copper layers only Number of metal layers 8 Surface finish Cu organic solderability preservative (OSP) Lead Finish Conversion Qualification Report 7

8 Board-Level Reliability Test Summary Table 5: Test Board Details (Cont d) Parameter Value Pad type Pad dimensions Land pads 0.30 mm x 1.30 mm Table 6 shows the test leg sample organization. Table 6: Package Type Test Leg Sample Organization Leadframe Finish Solder Paste Reflow Profile Leg Sample Size VOG48 NiPdAu Pb-Free SAC 305 Pb-free 1 36 units VOG48 NiPdAu 63 Sn/37 Pb Sn/Pb 2 36 units Table 7 shows the test results for each test leg of the BLR test. Table 7: BLR TC Number of Cycles BLR TC Test Results Failure Rate (Number of Units) Leg 1 Leg 2 NiPdAu SAC NiPdAu SnPb , Based on the data gathered from these tests, the device samples pass reliability requirements and are qualified for production. 8 Lead Finish Conversion Qualification Report