The Neuro-Bit Memristor. User Manual Version 2.0 July 2015

Transcription

1 The Neuro-Bit Memristor User Manual Version 2.0 July 2015

2 Dear Customer, We at Bio Inspired Technologies believe that the future of electronics is based on adaptive intelligence technologies - technologies that enable biologically inspired circuits that think and learn. The Bio Inspired Technologies Neuro-Bit Memristor device is the first in many steps toward that end. Because of the uncanny behavioral and operational similarities between the memristor and the biological synapse, we believe the memristor will play a pivotal role in advancing intelligent systems, and we hope that you find these devices instrumental to your role as researchers, engineers, inventors, or even hobbyists in implementing the future of neuromorphic designs. Invent the future. Thank you for your purchase, The Bio Inspired Technologies Staff Neuro-Bit User Manual 2 of 27

3 Contents Overview ESD Warning and Critical Application Notes Memristor Conventions Absolute Maximum Ratings Electrical Characteristics Pin DIP Neuro-Bit Pin PLCC Neuro-Bit Pin PLCC Breakout Board Raw Neuro-Bit Die Measurement Equipment Importance of Carefully Controlled Measurements The Intrinsic Variability of the Neuro-Bit Memristor DC Measurements DC Voltage Sweep DC Write DC Erase AC Pulsed Measurements Measurement Setup for Pulsed Testing Voltage across a device during Pulse Testing Current through a device during Pulse Testing Contact Us Revision History Copyright and Legal Neuro-Bit User Manual 3 of 27

4 Figures Neuro-Bit User Manual Figure 1: Neuro-Bit Memristor Schematic Symbol Figure 2: 16-pin DIP Neuro-Bit Package Figure 3: 16-pin DIP Pinout Figure 4: 44-pin PLCC Neuro-Bit Package Figure 5: 44-pin PLCC Pinout and Connection Chart Figure 6: 44-pin PLCC Breakout Board Figure 7: Raw Die Wafer-Level Device Layout Figure 8: Recommended Device Analysis Equipment Figure 9: The DC Write Sequence Figure 10: The DC Erase Sequence Figure 11:Example of a DC Write Figure 12: Example of a DC Erase Figure 13: WGFMU Pulsed Testing Connection Figure 14: Device Voltage from a Three-Cycle Sequence Figure 15: Device Voltage from Consecutive Sequencing Figure 16: Repeatability and Stability of Device Voltage Figure 17: Device Voltage and Current Over a Three-Cycle Sequence Tables Table 1: Operational Maximum Ratings Table 2: Neuro-Bit Electrical Characteristics Neuro-Bit User Manual 4 of 27

5 Overview Neuro-Bit User Manual The Neuro-Bit 44-pin PLCC, introduced by Bio Inspired Technologies, contains 20 functional chalcogenide-based ion-conducting memristor devices. Similarly, both the 16-pin DIP and the raw die packages are supplied with 8 and 80 identical memristor devices, respectively. These chalcogenide-based ion-conducting memristors can be "written" and "erased" to alternate the device between high and low resistance states as desired. It is non-volatile in the sense that the device still remembers its programmed state after power has been removed. In a controlled pulsing scenario, the memristor retains a state that is a function of both the history of the device and the current applied signal. The memristor is a nano-scale, thin-film variable electrical resistor fabricated on a silicon wafer that has a memory. The memristor, while exhibiting complex behavior, uses dendrite growth to change its resistance state and is fully reversible through the appropriate application of control signals. The device is analog in nature and can be programmed to a variety of intermediate resistance states in between "on" and "off". Due to this behavior, the memristor is also referred to as a continuously variable resistor (CVR). The dendrite circuit emulates the behavior and operates in nearly the exact way as that of a biological synapse, making it an ideal candidate for: Synthetic neurons Threshold logic and Reconfigurable circuit applications Neuromorphic circuits Tunable memristor-based resistors, capacitors, and inductors Adaptive intelligence and learning systems Neural networks and weighted feedback systems Spike-timing-dependent plasticity (STDP) experimentation Multi-level memory systems Implementing inhibitory and excitatory responses in circuits Bio-Inspired Technologies is currently offering the following package options: 16-pin DIP Package 44-pin PLCC Package ( A breakout PCB is available for the PLCC option) Raw-die Neuro-Bit User Manual 5 of 27

6 ESD Warning and Critical Application Notes Warning! This product is ultra-sensitive to electrostatic discharge (ESD). When handling, care must be taken so that the memristor devices are not damaged. The following precautions must be taken: Do not open the protective conductive packaging until you have read the following, and are at an approved anti-static work station. Use a conductive wrist strap attached to a good earth ground. Always discharge yourself by touching a grounded bare metal surface or approved antistatic mat before picking up an ESD sensitive electronic component. Never handle the packaged parts or test die with bare hands. Use an approved anti-static mat to cover your work surface. Always store devices in a dry, inert environment. Additionally, some caution must be taken into account when testing the devices due to their sensitive nature: Do not measure the memristor resistance with a multi-meter. A multi-meter will damage the device due to high open-circuit voltage. Always set appropriate compliance current (see Maximum Ratings). This is critical to ensure proper device functionality. Limit applied voltages to ±5V for Writes and Erases, or 50mV for Reads. Erases greater than 4V (with respect to polarity) pose greater risk of damaging the devices than Writes due to higher allowable current levels. Neuro-Bit User Manual 6 of 27

7 Memristor Conventions The conventional circuit schematic symbol for the Neuro-Bit memristor is shown below in Figure 1. As shown, the memristor is a two-terminal semiconductor device with top and bottom electrodes that represent the positive and negative terminals, respectively. For all diagrams in this document, the top electrode of a memristor symbol is marked with a black rectangle to denote orientation. Figure 1: Neuro-Bit Memristor Schematic Symbol Absolute Maximum Ratings Table 1: Operational Maximum Ratings Characteristic Symbol Value Units Write Voltage V W 5 V Erase Voltage V E -5 V Read Voltage (Note 1) V R 50 mv Write Compliance A = +25 C I Wc 40 μa Erase Compliance Current (Note A = +25 C I Ec 10 ma Read Compliance Current (Note A = +25 C I Rc 1 ma See notes on next page. Neuro-Bit User Manual 7 of 27

8 Electrical Characteristics Neuro-Bit User Manual Table 2: Neuro-Bit Electrical Characteristics T A = +25 C, unless otherwise noted Characteristic Symbol Conditions Min Typ Max Units SIGNAL CHARACTERISTICS Write Voltage Range V W I Wc = 30μA to 5 V Erase Voltage Range V E I Ec = 30μA to -5 V Read Voltage Range V R I Wc = 30μA mv Write Current I W V W = 1V, 4V - * * μa Erase Current I E V E = -1V, -4V 1 < 100 * μa Read Current I R V R = 50mV 1 * μa Write Compliance Current I Wc V W = 1V μa Erase Compliance Current (Note 2) I Ec V E = -1V μa Read Compliance Current (Note 3) I Rc V R = 50mV ma Write Speed t W V W = 1V ns SWITCHING CHARACTERISTICS High-to-Low Resistance Switch V HL V W = 1V V W = 4V Low-to-High Resistance Switch V LH V E = -1V, -4V - > mv Pre-Programming Resistance R pp MΩ Post-Write Resistance (Note 4, Note 5) R W V W = 1V, 4V kω Post-Erase Resistance (Note 4) R E V E = -1V, -4V MΩ Lifetime Pulse Cycles V W = 1V, V E = -1V M Notes: 1. Read voltages greater than 50mV risk altering device resistance. 2. Erase compliances are larger to allow the device as much current as it needs to switch resistance states. In most cases, the devices will consume less than 100μA. 3. A compliance of 1mA is a recommendation only, as in most cases 50mV will not allow damaging current levels. 4. Maximum and minimum post-programming resistance values will vary depending on allowed compliance current. 5. Post-write resistances below 1kΩ may be difficult to successfully erase. * Value set by respective compliance. Typical current values vary based on magnitude of the device s resistive state mv Neuro-Bit User Manual 8 of 27

9 16-Pin DIP Neuro-Bit Neuro-Bit User Manual The 16-pin DIP package provides the easiest way to start testing and experimenting with the Neuro-Bit memristors. Through-hole connections on the sides of the package allow it to be directly inserted into a breadboard for customized testing circuits, as well as a 16-pin IC socket available from various vendors. The 16-pin DIP package contains 8 two-terminal Neuro-Bit memristors as connected in Figure 2. Figure 2: 16-pin DIP Neuro-Bit Package 16-pin DIP Pinout The 16-pin DIP package contains 8 linearly-connected memristors. Electrode layout seen in Figure 3 uses the convention outlined in Figure 1. Figure 3: 16-pin DIP Pinout Neuro-Bit User Manual 9 of 27

10 44-Pin PLCC Neuro-Bit Neuro-Bit User Manual The 44-pin PLCC package is an excellent package for a significant number of available memristors. The package contains 20 bonded memristor devices, with 60 more devices available for future bonding and use. When paired with the breakout board or a single socket, this option excels at providing the designer a variety of memristors immediately available for use in a circuit without the need for multiple DIP sockets. Figure 4: 44-pin PLCC Neuro-Bit Package Memristor to Package Pinout: A pinout diagram and chart is provided below in Figure 5. The 44-pin package places pins 1 through 44 in a counter-clockwise ascending order, with device connections varying pinfrom-pin. In the chart, M denotes the memristor device and uses TE and BE to denote the pin number used for the top and bottom electrodes for that device, as outlined by Figure 1. Figure 5: 44-pin PLCC Pinout and Connection Chart Neuro-Bit User Manual 10 of 27

11 44-Pin PLCC Breakout Board Neuro-Bit User Manual The breakout board for the 44-pin PLCC allows the user to place the Neuro-Bit chip in a board-mounted socket for ease of testing. Each pin is connected to a labeled header pin as seen in Figure 6. The memristors are labeled TEn and BEn on the header to designate the polarity of the connected electrode, with n as the device number. Additionally, the breakout board is equipped with ESD protection circuitry to reduce the chance of accidental device damage. A mini-usb terminal is provided underneath the board to provide an easy path to an external ground connection. This ground is not connected in any way to the Neuro-Bit devices and is there solely for ESD protection. Figure 6: 44-pin PLCC Breakout Board Neuro-Bit User Manual 11 of 27

12 Raw Neuro-Bit Die Neuro-Bit User Manual The raw Neuro-Bit test die contains 80 memristors with a yield above 75%, and provides the largest number of available memristors without a defined package type. The locations and orientation are as shown below in Figure 7, with devices numbered 1 through 80. The large blocks are alignment features and the small crosses are Van Der Pauw structures to characterize the top and bottom metal layers. Sixteen additional memristors can be found between the row blocks of numbered devices. All memristors on the die are oriented with the top electrode, colored in purple, on the left Figure 7: Raw Die Wafer-Level Device Layout Neuro-Bit User Manual 12 of 27

13 Measurement Equipment Neuro-Bit User Manual The following equipment is highly recommended for use with the Neuro-Bit. Failure to use the recommended equipment or equivalent/similar products can result in unwanted transients that produce faulty data and/or damaged devices. Measurement transients are very common in many instruments and, unless correctly regulated, will result in irreparable damage to the devices. It is recommended that any test equipment be carefully examined with an oscilloscope prior to testing actual memristors. Transients should not exceed a few millivolts. This includes any environmental noise as well. Agilent B1500A Semiconductor Device Analyzer (Figure 8 Top) HP4145/56 Semiconductor Parameter Analyzers (Figure 8 Bottom) Figure 8: Recommended Device Analysis Equipment Neuro-Bit User Manual 13 of 27

14 Importance of Carefully Controlled Measurements The Neuro-Bit Memristors are highly sensitive and reactive devices that, when programmed correctly, may be used in a variety of neural networking or memory-based applications. However, the devices must be carefully controlled to ensure peak performance. A device that is carelessly operated will quickly short, making it nearly impossible to erase for future use. An explanation of a typical DC characterization task is illustrated below: The programming cycle. When freshly manufactured, the memristors have not yet developed preferential dendrite programming pathways. As a result, initial resistance measurements should indicate a very high resistance (nearly open). A simple resistance measurement should be done with a voltage of less than 50mV. Conventional multimeters or unverified equipment should not be used because of the often very large open circuit voltages or unconstrained current parameters. It is important that the sample voltage be kept minimal to prevent the measurements from changing the state of the device. If the sample voltages are greater than 50mV, the device will begin to write while being sampled. The write cycle. The write cycle typically involves simply sweeping the device to a value above the expected switching threshold, or approximately 200 mv to 400mV for the Neuro-Bit devices. A typical sweep for these devices would be from zero to one volt. During DC sweeps, setting a current compliance for your measurement is extremely important and critical to preserving functioning devices. While sweeping the devices above the write threshold is important to perform a write, the current compliance you set will determine both the final resistance value of the memristor and how stable the device will be at that state. Reasonable current compliance values will range between 100nA and 30μA. When experimenting with the Neuro-Bit Memristors, it is best to begin with very conservative values until you are comfortable with the performance. It is possible to set compliance to upwards of 100μA if the devices are having trouble writing to a resistive state below 100kΩ, though this is not recommended unless absolutely necessary and will damage the device more often than not. Note: The reason for setting a conservative compliance current is that the devices form a conductive dendrite (or several) during the programming process. The dendrite effectively makes a connection between the top electrode and bottom electrode, and the conductivity of the dendrites is set by the current allowed to pass through the device while being programmed. If the current is left unconstrained, the ions will flood the channel and create dendrites that effectively form a short circuit between the electrodes. This will make it nearly impossible to reverse the process during the erase cycle and the device will be stuck. It may be possible to reverse this through repeated erase sweeps, but the process is difficult to implement and not always effective. Neuro-Bit User Manual 14 of 27

15 The erase cycle. The erase cycle will reverse the effects of the write cycle, resetting the device back to a high resistance state. Since it is important to allow the device to consume the necessary current to reverse the dendrite growth, a current compliance is not normally required, and the erase currents are typically within the range of 1μA to 10μA (see Table 2). A typical sweep would be from 0V to -1V, setting the current compliance to between 100μA and 10mA as a safety precaution. After the erase step, the resistance of the device should be significantly less than the as-deposited values, and the device is now considered conditioned. Occasionally, the erase cycle may be repeated to achieve the desired resistance values if the first cycle does not erase effectively. There are no illeffects from repeating the erase cycle. The Intrinsic Variability of the Neuro-Bit Memristor The Neuro-Bit Memristors are intrinsically variable devices and no two devices operate identically. While physically the devices are the same size and configuration and will use the same programming and erase methodology, they will produce many different responses. In the semiconductor world where the ultimate goal is to have devices that are all identical, this behavior is unwanted. In the neural circuit world, however, this behavior is ideal. Additionally: Most neural circuits use a weighting system, in which the final output is a function of the tuned input weights. A correctly trained system that converges typically requires a set of randomly weighted inputs. The intrinsic variability of the Neuro-Bit Memristor provides this controlled randomness naturally. The state of the memristor is a function of the sum of the previous signals the device has experienced (both positive and negative), as well as the current signal. This provides for a direct analog to the biological synapse in which weighting is achieved through repeated activity. This can be reinforcing or inhibiting, depending on the sum and nature of the signals. For small compliance values, the memristor demonstrates a relaxation effect, in which the resistance slowly but predictably returns to either an intermediate value or a pre-write resistance value. This behavior could be considered the analog to forgetting, and would be very useful in circuits where signal strength and repetitive use determine functionality or preferred circuit pathways. The Neuro-Bit Memristors are continuously variable resistance (CVR) devices in that many discrete programming values can be achieved by carefully controlling the input pulses. The number of levels achieved is simply a function of the ability of the measurement system (or circuits) to resolve them. In many instances, the discrete states resulting from carefully controlled pulsing conditions form very stable and repeatable resistance values. Neuro-Bit User Manual 15 of 27

16 DC Measurements Neuro-Bit User Manual DC Voltage Sweep (Shown using an Agilent B1500) Memristor devices are typically operated under pulsed conditions since DC (quasi-static) sweeps do not provide true operational information (unless the device will be used in a circuit in a similar manner to the conditions of a DC sweep). However, the DC sequence is often the simplest way to confirm device functionality as well as provide a valuable tool to understanding the behavior of the devices. Below, Figure 9 demonstrates the process of a DC write sweep to and from 1V, with the sweep from 1V to 0V being used to confirm the state switch. Figure 9: The DC Write Sequence Neuro-Bit User Manual 16 of 27

17 The sweep sequence of a DC erase is similar to that of the write, as a voltage threshold forces the dendrites to retract from the device channel and place the device into a high resistance state. Figure 10 explains the process of a DC erase from 0V to -1V. Similar to Figure 9, a backwards erase from -1V to 0V can be applied to confirm the successful erase though it is not shown here. Figure 10: The DC Erase Sequence Neuro-Bit User Manual 17 of 27

18 DC Write For an example of a DC write, a DC signal is increased from 0V to 1V with 30μA compliance. The subsequent waveform performed on this Neuro-Bit device is shown in Figure 11, and demonstrates a successful write cycle with a switching event at 400mV. As the figure illustrates, the device current from a write will always reach and hold at the defined compliance current for the remainder of the sweep. If the compliance current is too high, the constant application of an increasing voltage with no current limit will mean that the device will always experience the maximum amount of power possible across it for the remainder of the sweep. Figure 11:Example of a DC Write Neuro-Bit User Manual 18 of 27

19 DC Erase For the erase, a DC signal is swept from 0V to -1V with 1mA compliance, and an example of the subsequent waveform on an actual device is shown below in Figure 12. An erased memristor will have a typical resistance values greater than 1MΩ. Notice the transition occurs around -100mV. While these values may vary between devices, the characteristic erase shape is evident and is characteristic of a successful transition to a high resistance state. Unlike the erase, however, the device must be allowed to draw enough current to switch states appropriately and for the characteristic shape shown in Figure 12. While erases typically only required a very small amount of current, limiting the device too much will often result in undesired behavior. Figure 12: Example of a DC Erase Neuro-Bit User Manual 19 of 27

20 AC Pulsed Measurements Measurement Setup for Pulsed Testing (Agilent B1500A and B1530A WGFMUs) Pulsed measurements are best performed in a circuit similar to that which will use the device. Alternatively, using an instrument like the Agilent B1500A equipped with the fast pulsing units (WGFMU, B1530A) is an option (we use this for wafer-level device testing). The Waveform Generator/Fast Measurement Units (WGFMUs) are operated in Pulse- Generation (PG) mode with 5V max range when measuring voltage across the device during pulsing. Fast I-V mode is used to measure current through the device during pulsing. A major drawback of this measurement is the lack of current limiting. The devices can be forced into very low resistance states (~50 to 100 Ohms in this case) and the measured current through the device can be in the ma range. This is indicative of how the device must be operated, but does show that it can be operated at very low resistance if desired. Figure 13: WGFMU Pulsed Testing Connection Neuro-Bit User Manual 20 of 27

21 Voltage across a device during Pulse Testing This is the raw data as it is provided by the test instrument. Figure 14 demonstrates the voltage measured at node 1 (WGFMU1) and at node 2 (WGFMU2) presented in Figure 13, with node 1 voltage on the left axis and node 2 voltage on the right axis. Observe that these both have different zero lines and ranges. The pulse train applied is a 3x repetition of the pulse sequence consisting of a read/erase/read/write/read. Because this pulse sequence is repeated 3 times, there are two regions with two consecutive read pulses. Note: The erase is a negative pulse used to increase the device resistance, whereas the write is a positive pulse used to decrease the device resistance. Read pulses are selected not to perturb the device. Figure 14: Device Voltage from a Three-Cycle Sequence. Neuro-Bit User Manual 21 of 27

22 The difference in voltage data between node 1 and node 2 is shown in Figure 15. This is the voltage as seen by the device during each programming/erase/reading pulse sequence through five testing cycles. The impact of the switching and erase events on the voltage pulse is an indication that the device is changing state during the application of the pulse. Additionally, the minimal impact of the read measurements is an important indication that the sample voltage is sufficiently small to have no appreciable impact on the current device state. Figure 15: Device Voltage from Consecutive Sequencing Neuro-Bit User Manual 22 of 27

23 The sequence of pulses (the 3x repetition of the sequence previously described) is repeated 5 times (for a total of 15 pulse sequence cycles). Below, Figure 16 shows the voltage across the device at the read pulses corresponding to the read after erase 1, write 1, erase 2, write 2, erase 3, and write 3. This is an indication of the stability and repeatability of the Neuro-Bit Memristor throughout several programming cycles. Figure 16: Repeatability and Stability of Device Voltage Neuro-Bit User Manual 23 of 27

24 Current through a device during Pulse Testing The raw data collected using the Fast IV mode to measure current through the device during pulse testing is shown in Figure 17. This data is procured from the same device used to collect the other data presented in this document. There is no current limiting during this measurement, so the device resistance gets to values approaching 100 Ohms in this example. Therefore, the measured current through the device is quite high. Note that the device operates nicely in current ranges from nano-amps through milli-amps. Figure 17: Device Voltage and Current Over a Three-Cycle Sequence Neuro-Bit User Manual 24 of 27

25 Contact Us If there are any problems or requirements when testing or using our Neuro-Bit Memristor products, please contact Bio Inspired Technologies, LLC, or visit: The most recent version Neuro-Bit User Manual is also located on the website. Bio Inspired Technologies 1020 W. Main St., STE 330 Boise, ID Tel: (Toll-free) Neuro-Bit User Manual 25 of 27

26 Revision History Ver 2.0, July 2015: Updated specifications to include maximum ratings and electrical characteristics to accurately match data found in Neuro-Bit datasheet (ds01_neurobit) Added information and section for 16-pin DIP Added notes on memristor orientation and symbol convention Modified various aspects of document layout and accessibility Neuro-Bit User Manual 26 of 27

27 Copyright and Legal Neuro-Bit User Manual 2015 Bio Inspired Technologies, LLC - All Rights Reserved Information in this document supersedes and replaces all information previous supplied. Information in this document is provided solely in connection with Bio Inspired Technologies products. Bio Inspired Technologies, LLC, makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes, corrections, modifications, or improvements to this document, and the products and services described herein, at any time, without notice. Purchasers are solely responsible for the choice, selection, and use of the Bio Inspired Technologies products and services described herein, and Bio Inspired Technologies assumes no liability whatsoever relating to the choice, selection, or use of the Bio Inspired Technologies services and products described herein. UNLESS OTHERWISE SET FORTH IN BIO INSPIRED TECHNOLOGIES TERMS AND CONDITIONS OF SALE, BIO INSPIRED TECHNOLOGIES DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF BIO INSPIRED TECHNOLOGIES PRODUCTS INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. IN NO EVENT SHALL BIO INSPIRED TECHNOLOGIES BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL, OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF BIO INSPIRED TECHNOLOGIES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. BIO INSPIRED TECHNOLOGIES PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: SAFETY-CRITICAL APPLICATIONS SUCH AS LIFE SUPPORT, IMPLANTED DEVICES, OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; AND/OR AUTOMOTIVE, AEROSPACE, OR AEURONAUTIC APPLICATIONS. WHERE BIO INSPIRED TECHNOLOGIES PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK, EVEN IF BIO INSPIRED TECHNOLOGIES HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS PRODUCT IS EXPRESSEDLY DESIGNATED BY BIO INSPIRED TECHNOLOGIES AS BEING INTENDED FOR AUTOMOTIVE, AERONAUTIC, AEROSPACE, OR MEDICAL INDUSTRY DOMAINS. Neuro-Bit User Manual 27 of 27