S. H. Chung a, W. L. Pearn a, A. H. I. Lee a & W. T. Ke a a Department of Industrial Engineering & Management,

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1 Ths artcle was downloaded by: [Natonal Chao Tung Unversty 國立交通大學 ] On: 27 Aprl 2014, At: 20:38 Publsher: Taylor & Francs Informa Ltd Regstered n England and Wales Regstered Number: Regstered offce: Mortmer House, Mortmer Street, London W1T 3JH, UK Internatonal Journal of Producton Research Publcaton detals, ncludng nstructons for authors and subscrpton nformaton: Job order releasng and throughput plannng for mult-prorty orders n wafer fabs S. H. Chung a, W. L. Pearn a, A. H. I. Lee a & W. T. Ke a a Department of Industral Engneerng & Management, Natonal Chao Tung Unversty, 1001 Ta Hsueh Road, Hsn Chu, Tawan, 30050, ROC Publshed onlne: 14 Nov To cte ths artcle: S. H. Chung, W. L. Pearn, A. H. I. Lee & W. T. Ke (2003) Job order releasng and throughput plannng for mult-prorty orders n wafer fabs, Internatonal Journal of Producton Research, 41:8, , DOI: / To lnk to ths artcle: PLEASE SCROLL DOWN FOR ARTICLE Taylor & Francs makes every effort to ensure the accuracy of all the nformaton (the Content ) contaned n the publcatons on our platform. However, Taylor & Francs, our agents, and our lcensors make no representatons or warrantes whatsoever as to the accuracy, completeness, or sutablty for any purpose of the Content. Any opnons and vews expressed n ths publcaton are the opnons and vews of the authors, and are not the vews of or endorsed by Taylor & Francs. The accuracy of the Content should not be reled upon and should be ndependently verfed wth prmary sources of nformaton. Taylor and Francs shall not be lable for any losses, actons, clams, proceedngs, demands, costs, expenses, damages, and other labltes whatsoever or howsoever caused arsng drectly or ndrectly n connecton wth, n relaton to or arsng out of the use of the Content. Ths artcle may be used for research, teachng, and prvate study purposes. Any substantal or systematc reproducton, redstrbuton, resellng, loan, sub-lcensng, systematc supply, or dstrbuton n any form to anyone s expressly forbdden. Terms & Condtons of access and use can be found at page/terms-and-condtons

2 nt. j. prod. res., 2003, vol. 41, no. 8, Job order releasng and throughput plannng for mult-prorty orders n wafer fabs S. H. CHUNG{*, W. L. PEARN{, A. H. I. LEE{ and W. T. KE{ To meet the producton target of mult-level (multple prorty rank) orders n wafer fabs, ths paper uses a herarchcal framework based on a mathematcal model, and wthout the assstance of any smulaton tool, to buld a producton schedulng system toplan wafer lot releasng sequence and tme. Ths system frst apples capacty loadng analyss to set up the batch polcy for each level (rank) of orders. Next, the producton cycle tme of each product level s estmated wth consderatons of batchng and loadng factor. The cycle tme s then used to derve system control parameters such as the most approprate level of work n process (WIP) and the number of daly operatons on the bottleneck workstaton. Lastly, a Constant WIP mechansm s appled to establsh a wafer release sequence table and a throughput tmetable. The due date desgnaton for each specfc order can hence be confrmed. Wth the comparson wth the result of smulaton, t shows that under the desgned system the performance and plannng measures n the master producton schedule can be drawn up quckly and accurately, and the system throughput target and due date satsfacton can be acheved. Overall, the proposed producton schedulng system s both effectve and practcable, and the plannng results are supportve for good target plannng and producton actvty control. 1. Introducton At the same tme as upgradng manufacturng technology, wafer manufacturers rase more captal to ncrease capacty. Ths has made the supply of products ncrease tremendously and the competton become even fercer. The dfferent proft rate of products and the vared mportance level of clents result n dfferent levels of orders n a fab, and ths makes producton schedulng deal wth many types of products and dfferent levels of orders. The exstence of rush orders, because of ther prorty for processng, oppresses normal orders, and as a result the average producton cycle tme of normal orders and ts varance are ncreased, and the estmaton of producton cycle tme and schedule plannng becomes more dffcult. In the past, scholars researchng producton plannng and schedulng for wafer fabs usually assumed a un-level product type, and very few consdered mult-level products. In order to ncrease a company s competton edge and proftablty, an effectve schedule plannng system, wth the ablty of settng wafer release sequence and tme as well as throughput, must be bult so as to acheve the system throughput target under the gven combnaton of product type and prorty rank. Revson receved September { Department of Industral Engneerng & Management, Natonal Chao Tung Unversty, 1001 Ta Hsueh Road, Hsn Chu, Tawan 30050, ROC. * To whom correspondence should be addressed. e-mal: t7533@cc.nctu.edu.tw Internatonal Journal of Producton Research ISSN prnt/issn X onlne # 2003 Taylor & Francs Ltd DOI: /

3 1766 S. H. Chung et al. Ths paper covers master producton schedulng and materal release plannng. Based on the throughput plan of a wafer fab, the most approprate WIP level, producton cycle tme, wafer release sequence table and completon tme table for each rank of product orders are prepared. Such a plannng result can be valuable n settng the due date and for decson-makng n producton actvty control system. 2. Lterature revew Producton cycle tme s the tme spent by a wafer batch from materal release to completon (Kramer 1989). It can be further separated nto theoretcal cycle tme and watng tme. Theoretcal cycle tme ncludes process tme, set-up tme, ar pumpng n and out tme, and wafer carryng tme, etc. (Wnston 1991). Watng tme ncludes the tme watng for process and the tme watng for move (Raos 1992). Usually, theoretcal cycle tme has a smaller varance and often s treated as a constant, whle watng tme has a hgh degree of uncertanty. For cycle tme estmaton, Chung and Huang (1999), wth the applcaton of queueng theory and the observaton of the characterstcs of materal flow, developed a producton cycle tme estmatng formulaton, the Block-Based Cycle Tme (BBCT) estmaton algorthm, whch has dstngushable performance. Conway et al. (1967) adopted Laplace transforms to estmate the job cycle tme on a sngle machne, and the cycle tme and WIP level can both be consdered at the same tme. For master producton schedulng, the plannng method can be separated nto three categores: smulaton, mathematcal programmng and the combnaton of the two. The advantage of usng a smulaton tool to plan schedules s that t s easy to construct the system that matches wth the producton actvty control stage (Lu et al. 1995). The smulaton can offer what-f analyss and control well the WIP level n a certan range, but t takes tme. Lnear programmng based on capacty constrants can quckly derve the best producton plan, but there are too many assumptons n descrbng the real phenomenon (Chu 1995, Hackman and Leachman 1989). For ths reason, some researches combned the smulaton and mathematc algorthm to descrbe better the envronment than by separately adoptng ether of the two methods (Burman et al. 1986, Hung and Leachman 1996, Thompson and Davs 1990). Mller (1990) has tred to make the system WIP level constant and decde on batch sze n fab by smulaton tool. Neuts (1975) presented the dea of mnmal batch sze (MBS), whch means that even f a machne s dle, the jobs must be held untl a certan level of batch sze has been gathered before they can be processed. To mnmze the watng tme n a queue lne, Glassey and Weng (1991) consdered the future arrval rate and appled Dynamc Batchng Heurstc (DBH) toset up the batch sze for a sngle product and sngle furnace machne. For the performance of throughput, Chung et al. (1997) focused on layers completed n a fab to measure the producton performance for shop-floor actvty. Leachman and Hodges (1996) desgned an ntegrated producton ablty ndex to measure the performance n dfferent fabs by qualty metrcs, productvty metrcs, and producton speed and output target. Chung and Huang (1999) nvestgated 12 materal release rules for wafer fabs. Among them, Constant WIP (CONWIP) s a type of materal release control between Just-n-Tme (JIT) and a push system. It consders the use of capacty-constraned resource (CCR), controls WIP n number of unts nstead of tme and dynamcally modfes the materal-release tme when machnes break down. Therefore, CONWIP s a relatvely good producton actvty

4 Mult-prorty orders n wafer fabs 1767 control rule and thus wll be used n ths research. The present paper wll estmate cycle tme based on BBCT and wll plan MPS, whch ncludes materal release tme and order, daly bottleneck throughput and throughput tme. Lttle s law wll be appled, whch reveals the relaton of WIP level (L), releasng rate () and producton cycle tme (W), and the relaton can be shown as L ¼ W (Lttle 1961). 3. Model constructon 3.1. Master producton plannng Generally speakng, the prorty levels for orders n a wafer fab are classfed nto several dfferent levels. In ths study, the levels of orders are categorzed nto three: hot lots, rush lots and normal lots. Hot lots have the hghest processng prorty and are not restrcted to the batch polcy. In other words, a hot lot can be processed even f t conssts of only a sngle lot. Rush lots have the second processng prorty, and the batch polcy s determned by the proposed schedulng system under rough-cut capacty plannng. Normal lots have the lowest processng prorty and are constraned by the full-loaded batch polcy. To smplfy the complexty of the problem, the assumptons n ths study are made as follows.. Monthly throughput target, product type and rank mx are predetermned.. No carryng cost s consdered.. No human resource and materal supply shortage problem.. Processng steps and the correspondng processng tmes are dfferent only n the product type, not n the processng prorty.. Sze of each customer order s a multple of release batch sze. Normally, the plannng horzon for master producton schedule (MPS) s 12 weeks, whle the plannng perod (T) s 4 weeks. The framework for MPS plannng s shown n fgure 1. Frst, an MPS plannng module evaluates machne loadng and determnes batch polcy accordng to system throughput target, product type and prorty mx. Second, the block-based cycle tme estmaton algorthm for multple-prorty orders (BBCT-MP), developed by Chung et al. (2001), s used tocalculate the cycle tme for each product type n each rank. The nformaton about cycle tme and throughput s used toderve the sutable WIP level and tocalculate the number of daly bottleneck operatons. A wafer lot releasng sequence and a tmetable are then establshed. The correspondng order completon tme and order due date are determned n consequence Capacty loadng evaluaton and batch polcy determnaton Adoptng a partal loadng batch polcy for a hot lot and a rush lot wll shorten ther producton cycle tme. However, the machne utlzaton rate for each batch machne wll be rased, and ths wll lead to a bottleneck or crtcal machne wanderng, whch n turn wll ncrease the varaton n cycle tmes. To stablze utlzaton rates among machne types, the MPS plannng wll analyse the machne loadng levels for each type of batch polcy to meet the throughput target under a predetermned product type and rank mx. The batch polcy s set to be one lot for hot lots and full-loaded for normal lots. Snce the maxmum batch sze for many batch machnes s sx lots, and these machnes such as furnace usually have qute long processng tmes, we present the batch polcy evaluaton process for machnes wth a maxmum batch sze of sx n fgure 2. In ths case, the batch

5 1768 S. H. Chung et al. Producton Related Informaton System throughput target Product mx Prorty level Product process Workstaton nformaton MPS Module Batch polcy decson Sutable WIP level for each prorty level Release batch sze for each prorty level Cycle tme for each prorty level (BBCT-MP) Releasng sequence Releasng schedule Capacty loadng evaluaton (BBCT-MP) Daly operatons for bottleneck resources Completon tme Due date assgnment Fgure 1. Framework for MPS plannng. polcy s set to be sx lots, full-loaded for normal lots. Whle for rush lots we wll evaluate whether the batch sze of one lot wll make the machne overloadng happen. If there s not suffcent capacty, we need to ncrease the batch sze of rush lots. Even f there s suffcent capacty, we stll need to check the utlzaton rate of CCR. The utlzaton of CCR should be at least 10% less than that of bottleneck to avod bottleneck wanderng. The batch sze of rush lots s determned when there s lttle chance of bottleneck wanderng.

6 Mult-prorty orders n wafer fabs 1769 Capacty and batch sze evaluaton Batch sze of hot lots=1 Batch sze of normal lots=6 Batch sze of rush lots=1 Estmate the utlzaton rate of each resource Capacty suffcent for batch machnes Yes Bottleneck wanderng No Decde batch sze of rush lots End ncrease batch sze of rush lots No Yes Fgure 2. Batch polcy evaluaton process. A queung model s often adopted to estmate the utlzaton rate of a resource. Owng to expensveness and essentals n makng a photo layer, the photolthography stepper s treated as the bottleneck resource n the real world. In addton, the number of process steps and the total process tme for each photo layer are sgnfcantly dfferent. Such characterstcs make a large varaton n tme for re-entry to one specfc workstaton. We thus assume that each workstaton s an M/M/c queung system, and workstatons are ndependent n loadng evaluaton. In order to derve the arrval rate for each level of product orders comng to a workstaton, we let that quantty for system nput equal the planned throughput of the plannng perod based on CONWIP materal release control polcy. The procedures for dervng utlzaton rate are as follows. Step 1. Calculate the average system hourly arrval (throughput) rate, hr, based on throughput target R n a plannng perod (T):

7 1770 S. H. Chung et al. hr ¼ R Tz 24 : Step 2. Estmate the mean arrval rate pr k for each rank of product orders arrvng workstaton k per hour. It was derved by the average system hourly arrval (throughput) rate, mx rato for product type ð ¼ 1;...; IÞ toall product types, p, proporton of throughput wth rank pr to throughput of all product type ðp pr Þ, number of process vstng workstaton k, f k, and average rework rate for workstaton k, k : pr k ¼ hr X ð1þ ½p p pr f k ð1 þ k ÞŠ; for each k and pr: ð2þ Step 3. Estmate the equvalent avalable unts for machne type k, c k, whch equals the total avalable unts (n k ) deductng the downtme rato and mantenance tme rato: c k ¼ Xn k MTTR km MTTPM km 1 ð3þ MTBF km þ MTTR km MTBPM km þ MTTPM km m¼1 for each k, where MTTR km s the mean tme torepar (MTTR) for the mth machne for machne type k, MTBF km s the mean tme between falure (MTBF) for the mth machne for machne type k, MTTPM km s the mean tme topreventve mantenance (MTTPM) for the mth machne for machne type k, and MTBPM km s the mean tme between preventve mantenance (MTBPM) for the mth machne for machne type k. Step 4. Estmate the number of machnes used for producng all knds of hot lots ðpr ¼ hþ, c h k. Because the mnmum batch sze for hot lot flowng through machne type k, B mn;h k, s set to be 1, the batch sze consderaton s omtted from ths formula: c h k ¼ hr XI X p p h PT p ; for each k; ð4þ ¼1 p2fmð; pþ¼kg where PT p s the process tme for product at pth step, and Mð; pþ s the workstaton type used for process type at pth step. Step 5. Estmate the number of machnes used for producng all knds of rush lots ðpr ¼ rþ, c r k, wth the temporary batch sze set at B mn;r c r k ¼ hr XI ¼1 p X p2fmð; pþ¼kg k :! PT p B mn;r ; for each k: ð5þ k Step 6. Estmate the number of machne type k avalable for normal lots, c n k. It s the remanng machne unts after provdng all the capacty needs to hot lots and rush lots: c n k ¼ c k c h k c r k; for each k: ð6þ Step 7. Estmate the mean process tme for all knds of processes passng through machne type k, PT k (hr):

8 PT k ¼ XI ¼1 p X pr Mult-prorty orders n wafer fabs p pr X p2fmð; pþ¼kg PT p mn; pr Bk f k 1771 ; for each k: ð7þ Step 8. Estmate the mean output rate for wafer lots wth rank pr passng through workstaton k, O pr k : O pr k ¼ cpr k pr Bmn; k ; for each k and pr: ð8þ PT k Step 9. Estmate the mean output rate for each workstaton k, O k : O k ¼ X p f k X ðp pr O pr k ; Þ for each k: ð9þ pr Step 10. Estmate the mean servce rate n a plannng perod for each workstaton, k. It s the product of effcency rato of workstaton k (e k, the fracton of tme that the workstaton s n a condton to perform ts ntended functon to the total producton avalable tme) and mean output rate for each workstaton k: k ¼ e k O k ; for each k: ð10þ Step 11. Estmate the mean utlzaton rate of the resources k, k. It s calculated by dvdng the mean arrval rate for all product orders arrvng a workstaton to the mean servce rate for that workstaton: k ¼ X pr pr k k ; for each k: ð11þ 3.3. Estmaton of cycle tme for each prorty level Once a batch polcy s determned, the release batch sze for each prorty rank of orders s set the same as the largest batch sze of all workstatons set for that prorty rank to utlze workstatons effectvely and to make flow smoothly. Let n pr be the number of lots contaned n a release batch wth rank pr, where h, r, andn stand for hot, rush and normal, respectvely. After the releasng batch sze for each rank of orders s defned, an accepted order wll be cut nto several suborders, based on the correspondng releasng batch sze and for the ease of producton control. Next, after the confrmaton of product mx, we can apply the block-based cycle tme estmaton algorthm for multple-prorty (BBCT-MP), developed by Chung et al. (2001), to estmate cycle tme for each product type n every prorty rank. Input data nclude monthly throughput target, product type and rank mx, process plan, workstatonrelated nformaton, and batch polces. Because batch formng before a batch workstaton s one of the major reasons for congeston of materal flows, BBCT-MP treats each batch workstaton as a cuttng pont and dvdes a manufacturng process nto blocks. In each block, as depcted n fgure 3, all steps are seral machne steps except the frst and last process steps, whch are batch-type process steps. The dfference n batch szes and n output velocty between precedng and succeedng machnes nduces dfferent watng tmes before machnes. We thus recognze the two reasons for ncurrng watng as batchng and loadng factors for every block.

9 1772 S. H. Chung et al. Start B 1 B ( j - 1) B j B m Out block1 block - ( j 1) Seral-type workstaton block + ( j 1) block j block ( m + 1) Batch-type workstaton Fgure 3. Block j for product type. The watng tme caused by batchng factor conssts of two parts. One s due to gatherng the requred batch sze before batch processng. The other s due to the releasng of all the lots contaned n a batch after the batch operaton. Ths causes the ncrease of transent loadng for a downstream seral workstaton. The batch factorng flow tme (BFFT) algorthm s used to estmate such a watng tme (Chung et al. 2001). On the other hand, the watng tme caused by the loadng factor s due to the average load rased on each workstaton so as to acheve the system throughput target. The watng tme for each rank of orders that ncurred by the loadng factor s estmated by a non-preemptve prorty queung model (Chung et al. 2001). Addng two knds of watng tme and the total process tme of all blocks of each process derves the product cycle tme for a specfc prorty rank. The BBCT-MP algorthm has a remarkable performance n cycle tme estmaton because t captures the exact nteracton between two batch workstatons and all seral workstatons n a block SystemWIP level estmaton For producton smoothng,.e. mnmzng cycle tme varaton, a constant WIP control s adopted here for settng the wafer release plan, and the sutable system WIP level for each prorty rank of wafer lots, L pr, needs tobe derved. Lttle s Law n queung theory (Lttle 1961), L pr ¼ pr CT pr, s appled, where pr s the arrval rate and CT pr s the correspondng cycle tme for the specfc product type and rank. By adoptng a constant WIP control polcy, wafer lot(s) can be released to the shop floor only when the same quantty of wafers are fnshed and transferred out. The arrval rate for product type wth rank pr, pr, s thus equvalent tothe correspondng throughput rate. The estmated system WIP level, L, s computed by summng up all the estmatng values of L pr. Under a constant WIP control polcy, once a system WIP level s lower than L, a fxed number of consecutve lots as defned n the releasng sequence wll be released nto the shop floor. Note that f a system WIP level s set too low, the amount of throughput wll be affected drectly. The procedures for dervng system WIP level are as follows.

10 Mult-prorty orders n wafer fabs 1773 Step 1. Calculate the average hourly arrval rate for each product type n each prorty rank, pr. It s derved by multplyng hr wth the product mx ratoof product toall system throughput, p, and the ratoof rank pr orders among all product outputs, p pr : pr ¼ hr p p pr : ð12þ Step 2. Estmate the approprate WIP level for product n rank pr, L pr, by Lttle s law: L pr ¼ pr CT pr : ð13þ Step 3. Estmate the system WIP level, L, by summng up all L pr values: L ¼ X X L pr : ð14þ pr 3.5. Calculatng the number of daly moves for a bottleneck resource As mentoned above, two major characterstcs of the process of wafer fabrcaton are a long cycle tme and numerous re-entry operatons. In order to acheve the throughput target and to mplement PAC effcently, the number of daly bottleneck operatons needs to be derved. A photolthography stepper, an extremely expensve resource and one n charge of the most crtcal operaton for buldng every photo layer, s treated as a bottleneck resource. A hgh utlzaton rate and long queue lne are expected for a photolthography stepper. Completon of a bottleneck operaton mples that the most crtcal operaton of a layer s fnshed and therefore s the completon of a system move. The concept of producton smoothng s proposed here,.e. the system throughput for each day s close to the average daly throughput target. Also, the output combnaton must ft the predetermned product type and rank mx rato. To meet these condtons, the number of moves at each layer must be the same as the daly system output. Meanwhle, the combnaton of each layer output must be the same as the combnaton of the system output. The procedures for daly moves plannng are shown below. Step 1. Calculate planned daly output for product type wth rank pr, pr d : pr d ¼ pr 24: ð15þ Step 2. Estmate the number of daly moves for product type wth rank pr, M pr d, whch s the product of pr d and the number of photo layers for product, N : M pr d ¼ pr d N : ð16þ Step 3. Number of the system daly moves, M d s the summaton of all M pr d values: M d ¼ X X M pr d : ð17þ pr 3.6. Buldng a cyclc wafer release sequence For products wth the same prorty rank, the same release batch sze s defned for every product type. In ths stuaton, the number of release tmes for each product type wth the same rank depends on ts product mx rato to all product types. On the

11 1774 S. H. Chung et al. other hand, for products wth dfferent prorty ranks, dfferent release batch szes may be appled. The number of release tmes s proportonally reverse to ther release batch szes for product types wth same product mx rato. Thus, to make the combnaton of daly throughput satsfy a predetermned product type and rank mx, a table showng a cyclc release sequence must be bult consderng the product type mx, rank mx and the release batch sze desgned for each rank. To set up a table of the releasng sequence and tme, the throughput nterval for each product type wth each rank s calculated frst. Then, the release nterval can be set to match wth the predetermned release batch sze. For a hot run, the releasng nterval s the same as ts average throughput nterval snce ts release batch sze s one lot. For producton orders wth normal rank, ther releasng nterval s sx tmes the average throughput nterval snce ther release batch sze s sx lots. A smlar rule s appled to rush orders once the release batch szes are determned. For each product type wth each rank, once the release nterval s derved, one can calculate the release tme for every release batch lot so as to make the dstrbuton of all WIP n the shop floor satsfy the product type and rank mx rato. We then sort the release tmes of all product types and all ranks, from small to large, to establsh the release tmetable and release sequence. Fnally, the release cycle table s determned after all products reach ther expected throughput rato. The release plan wll be made based on ths table. The algorthm for settng a cyclc release table s as follows. Step 1. Calculate the product/rank mx for product wth rank pr, pro pr, by dvdng pr d by the maxmum common dvder for all pr d : pro pr ¼ pr d fmaxmum common dvder for all pr d g ; for each and each pr; and pr d 6¼ 0: ð18þ Step 2. Fnd the mnmum common multpler for all knds of release batch szes,.e. ½n h ; n r ; n n Š, and calculate the relatve frequency for job order wth rank pr by dvdng ½n h ; n r ; n n Š by the release batch specfed for rank pr, n pr. The release number for product wth rank pr, q pr the correspondng relatve release frequency for rank pr:, s the multplcaton of pro pr wth q pr ¼ pro pr ½nh ; n r ; n n Š n pr : ð19þ Step 3. Compute the maxmum sequencng number n the release table, q max by summng up all q pr dgts of all product types wth all ranks: q max ¼ X X q pr : ð20þ pr Step 4. Calculate the daly average nterval between the throughput of product type wth rank pr, I pr out;. It s the recprocal of pr d : I pr out; ¼ 1 ; for each ; each pr: ð21þ pr d

12 Mult-prorty orders n wafer fabs 1775 Step 5. Estmate the average release nterval for product type wth rank pr, I pr arr;, by multplyng the average nterval between throughput I pr out; wth ts correspondng release batch sze n pr : I pr arr; ¼ I pr out; npr ; for each ; each pr: ð22þ Step 6. For every product type wth rank pr, set release numberng q ¼ 1. Step 7. Let the frst release tme for every product type wth rank pr, t pr arr;, equal ts average release nterval I pr arr; : Step 8. Step 9. t pr arr; ¼ I pr arr; ; for each ; each pr: ð23þ Choose the smallest release tme among all product types and all ranks. Identfy ts product type *, rank pr*, and put t on the release table, wth sequence numberng q. If there are more than two product types or ranks that have the same smallest release tme, choose the one wth the smaller number of tmes beng chosen to break the te. However, f the te stll exsts, arrange the sequence randomly. Record the seq q ¼ð*; pr*þ nformaton n the cyclc release table. t pr arr; ¼ mnftpr arr; ; for all and all prg ð24þ seq q ¼ð*; pr*þ q ¼ q þ 1: ð25þ ð26þ Renew the next release tme for product type * wth rank pr* only. The others reman the same: t pr arr; ¼ tpr arr; þ I pr arr; ; for ¼ *; pr ¼ pr* only: ð27þ Step 10. Repeat Steps 8 and 9 untl q ¼ q max. Then, the cyclc release table s bult. For example, assume that planned daly throughput s 20 lots and daly outputs pr d for products A, B and C are 2, 6 and 12 lots respectvely. Further assume that product A ranks hot and the release batch sze s one lot, whle products B and C are normal and the release batch sze s sx lots. The product/rank mx calculated usng Step 1 s as n table 1. Product type rank pr d pro pr ¼ pr d fmaxmum common dvder for all pr d g A_H 2 B_N 6 C_N 12 Table 1. 2 fmaxmum common dvder for 2; 6; 12g ¼ 1 6 fmaxmum common dvder for 2; 6; 12g ¼ 3 12 fmaxmum common dvder for 2; 6; 12g ¼ 6 Calculatons of product/rank mx.

13 1776 S. H. Chung et al. Product type rank pro pr A_H 1 B_N 3 C_N 6 Table 2. Calculatons of maxmum sequencng number. pro pr ½nh ; n r ; n n Š n pr ½1; 6; 6Š 1 ¼ ¼ 6 ½1; 6; 6Š 3 ¼ ¼ 3 ½1; 6; 6Š 6 ¼ ¼ 6 The pro pr ratos thus 1:3:6 for products A_H, B_N and C_N, respectvely. The maxmum sequencng number n the release table, q max, can be derved followng Steps 2 and 3 as n table 2. From table 2, we can calculate that q max ¼ 6 þ 3 þ 6 ¼ 15. The correspondng average throughput ntervals are 1/2, 1/6 and 1/12 day, and the average release ntervals between throughput are thus 1/2, 1 and 1/2 day, respectvely, for products A, B and C. As shown n fgure 4, the release sequence s A-C-B- A-C A-C-B-A-C A-C-B-A-C. Note that an alternatve opton s acceptable by replacng all the A-C sequence wth C-A Releasng and delvery schedule settng Once the cyclc release sequence s known, the release schedule of the plannng perod can be easly derved. Frst record the last release tme n the prevous plannng perod for each product type wth each rank, t pr arr;. For each job order wth dstngushable product type and rank, we can derve ts planned release tme by usng the correspondng nformaton of throughput nterval, release batch sze h out, A h arr, A n out, B n arr, B n out, C n arr, C Tme (day) 0 1/12 2/12 3/12 4/12 5/12 1/2 7/12 8/12 9/12 10/12 11/12 1 Fgure 4. Settng of the wafer release sequence and tmng for the example.

14 Mult-prorty orders n wafer fabs 1777 and the sequencng specfed n the release sequence table. Addng the correspondng cycle tme tothe planned release tme derves the delvery schedule for the specfed job order. To set a due date, a cycle tme-based allowance for each job order s needed to absorb the mpact of the dsturbance. Because orders wth hgher rankng have the preferental rght for processng, ths wll cause hgher varance n cycle tme for job orders wth lower ranks. Lower prorty job orders thus need a larger allowance to ncrease the rato of on-tme delvery and reduce the rsk of lateness. Procedures for settng releasng and delvery schedule are as follows. Step 1. Set the ntal job lot numberng as v ¼ 1 for the current plannng perod. Lot numberng wll be assgned for lots wth a release tme already beng scheduled. Step 2. Trace the fnal release tme n the prevous plannng perod for every product type wth rank pr, t pr arr;. Also, trace the fnal release seral number q n the prevous plannng perod. Step 3. Accordng to the release seral number q, dentfy product type *, ts prorty pr*, and the seq q ¼ð*; pr*þ nformaton from the cyclc release table. Set ts job lot number as v and record ts release tme, product type and rank: Re l v ¼ t pr pr arr; þðiout; npr Þ; only for ¼ * and pr ¼ pr* Reset t pr arr; ¼ Re l v; only for ¼ * and pr ¼ pr*: Step 4. Estmate the completon tme of job lot v,comp v, by summng up the release tme and cycle tme of the correspondng product type and rank, CT prðvþ ðvþ : ð28þ ð29þ Comp v ¼ Re l v þ CT prðvþ ðvþ : ð30þ Step 5. Calculate due date of lot v, Due v, by summng up the release tme, cycle tme of the correspondng product type and rank, and a predetermned fractonal allowance of cycle tme wth fracton pr : Due v ¼ Re l v þð1 þ pr ÞCT prðvþ ðvþ : ð31þ Step 6. If n pr > 1, copy nformaton of Re l v, ðvþ prðvþ, Comp v, Due v for job lot numbers v, v þ 1;...; v þ n pr 1. If Re 2 v s greater than the closng tme of the plannng perod, end the plannng. Otherwse, set v ¼ v þ 1 and q ¼ q þ 1. In the case q > q max, reset q ¼ 1. Goback tostep Verfcaton wth smulaton To verfy the effect of ths plannng system, data from a wafer fabrcaton faclty n Hsnchu, Tawan, are used.. Producton nformaton: there are fve dfferent product types, A E, to be fabrcated n ths system. The products are categorzed nto two product famles, logc I.C. and memory I.C. All product types have dfferent process routes, and every product type has only one route. The requred workstatons and process tmes used n each route are known.. Order prorty nformaton: there are three prorty ranks n the system.. Hot: hghest prorty. The job orders are not lmted by batchng polcy and they can be released nto the shop floor and be loaded onto any batch machne wth only a sngle lot.

15 1778 S. H. Chung et al.. Rush: secondary prorty. Batchng polcy s defned accordng to the model proposed n ths paper, and release polcy s determned by the result of batchng polcy.. Normal: lowest prorty. Full loadng polcy s requred, and release batch s sx lots.. Workstaton nformaton: there are 83 dfferent types of workstatons (coded from W1 to 83), ncludng seral and batch workstatons. There are 15 sx-lot workstatons (W24 36), three four-lot workstatons (W38 40) and 19 two-lot workstatons (W07, W08, W13 15, W47, W48, W67 77, W81). The photo stepper, W46, s the bottleneck, and furnace, W24, s the CCR.. Down tme dstrbuton of workstatons: MTBF and MTTR are exponentally dstrbuted and are traced for each workstaton, whle MTBPM and MTTPM are known constants.. Machne set-up tme: average set-up tme s ncluded n process tme for most of workstaton types Assumptons for master producton schedule plannng. Product type and rank mx: the throughput target for each plannng perod s 640 lots. The product type mx for products A E s 5, 7, 3, 4 and 1 respectvely,.e. p A, p B, p C, p D and p E are 5/20, 7/20, 3/20, 4/20 and 1/20, respectvely. The rank rato(p h ; p r ; p n ) for products A E are (0, 2/5, 3/5), (0, 3/7, 4/7), (0, 1/3, 2/3), (0, 1/4, 3/4) and (1, 0, 0), respectvely. Based on the above, the throughput target for each product type and rank s lsted n table 3.. Allowance for settng due date: assume that the due date allowances for hot, rush, and normal rank of orders are 0.1, 0.12 and 0.15 of the estmated cycle tme.. Dspatchng rule: for jobs watng before a resource, the one wth a hgher rank has the preferental rght. For jobs wth same prorty rank, frst-n frst-out s appled Systemdesgn for smulaton To verfy results of the system, a smulaton model s bult by SMPLEþþ software developed by AESOP Co. To match the length of the MPS plannng horzon, a smulaton horzon s set to 168 days. The frst 84 days are a warm-up perod; hence, only results belongng to the next 84 days are collected. The smulaton model s run 15 tmes toget adequate statstcal results Process and results of the MPS module Capacty loadng and batchng polcy for rush-rank orders Snce the capacty loadng for the furnace (W24), a CCR, s next to the bottleneck workstaton (W46), ts batchng polcy s taken serously. When evaluatng the capacty loadng for rush orders, W46 and W24 are thus the man focus. Table 4 shows the evaluaton results. The above results show that when the mnmum loadng batch sze for rush orders s less than fve lots, there s a bg possblty of a bottleneck shftng or wanderng. When the mnmum loadng batch sze s set to fve or sx lots, there s a sgnfcant dfference n utlzaton rate between W46 and W24. Note that the maxmum loadng batch szes for batch machnes can be two, four or sx lots. Consderng the exstence of a multplcaton factor between dfferent batch machnes

16 Mult-prorty orders n wafer fabs 1779 Total A B C D E Total H R N Table 3. Throughput target for each product type and rank n a plannng perod (unt: lot). Mnmum batch sze for rush orders (lots) Utlzaton of W Utlzaton of W Table 4. Result of the capacty loadng under dfferent batchng polcy. wll beneft the materal flow, we set sx lots as the batch polcy for W24 and adopt a full batch polcy for all knds of batch machnes. Furthermore, snce the release batch sze s better to match wth the batch polcy for crtcal resources, rush orders wafers are released n sx contnuous lots Estmaton of producton cycle tme by product type and rank The BBCT-MP algorthm (Chung et al. 2001) s appled toestmate the producton cycle tme. The dfference n cycle tmes between the estmated dgt and smulaton result are shown n table 5. The accuracy of the cycle tme estmaton s above 96.25%, and the maxmum dfference s only h. In general, the estmaton method s good for predctng producton cycle tme Estmaton of WIP level After dervng the cycle tme of each product type and rank, we estmate the system work n process level wth Lttle s law. As shown n table 6, the estmated system WIP level s about 280 lots. To test and verfy the theoretcal WIP level properly, we set 280 lots as system WIP levels and ran the smulaton model 15 tmes. Wth the constant WIP release control polcy, the smulaton system throughput was lots, whch s very near to our throughput target of 640 lots. Product type_rank A_R A_N B_R B_N C_R C_N D_R D_N E_H (1) Estmated value (2) Smulaton result Dfference ð3þ ¼ð1Þ (12) Error rate ð4þ ¼ð3Þ=ð2Þð%Þ Table 5. Comparson of producton cycle tme by product type and rank (unt: h).

17 1780 S. H. Chung et al. Total A_R A_N B_R B_N C_R C_N D_R D_N E_H Total Table 6. Estmaton of WIP level by product type and rank (unt: lot) Estmaton of daly movement Usng equatons (15 17), the daly total movement for the bottleneck and the daly layer throughput are derved as shown n table Buldng a cyclc release sequence Snce the release batch sze for each rank has been determned, we can buld the cyclc wafer release table usng equatons (18 27) as shown n table Release and delvery schedule Follow the procedures n Secton 3.7, we can derve the release tme, completon tme and due date for each wafer lot. For space savng, only planned and smulaton results of 160 wafer lots released durng the 112th to 119th days (the ffth week after the warm-up perod) are shown n fgure 5. The analyss wll be gven below Effect analyss of MPS plannng Analyss of the accuracy n releasng tme predcton Fgure 5 and table 9 show that the predcton of release tme s qute close to the tme obtaned by smulaton. Note that we adopt the constant WIP level polcy for Layer movement Total A_R A_N B_R B_N C_R C_N D_R D_N E_H Fnal Total Table 7. Estmaton result of daly movement (unt: lot).

18 Mult-prorty orders n wafer fabs 1781 Seral no. Product type Prorty Batch release (lots) Seral no. Product type Prorty Batch release (lots) 1 E H 1 16 E H 1 2 B N 6 17 C R 6 3 A N 6 18 D R 6 4 B R 6 19 A R 6 5 D N 6 20 C N 6 6 E H 1 21 A N 6 7 A R 6 22 B R 6 8 C N 6 23 D N 6 9 B N 6 24 B N 6 10 E H 1 25 E H 1 11 A N 6 12 B R 6 13 D N 6 14 E H 1 15 B N 6 Date Table 8. Cyclc wafer release sequence. Comparson of the Plannng Result wth the Smulaton Output for Materal Release and Completon Tme pred cted mater al rel ease t me real materal release tme pred cted compl et on t me real completon tme Lot ID Fgure 5. Comparson of the plannng result wth the smulaton output for materal release and completon tme. Absolute error n release predcton (day) Number of job orders (lot) Percentage to total job orders > 0: Total Table 9. Error analyss for release tme estmaton.

19 1782 S. H. Chung et al. Type_rank A_R A_N B_R B_N C_R C_N D_R D_N E_H Throughput n smulaton Planned throughput Dfference Error percentage Table 10. Comparson of average throughput n smulaton to the planned throughput of a plannng perod (unt: lot). A_R A_N B_R B_N C_R C_N D_R D_N E_H Total Average no. of tardy lots (lot) Average throughput per perod (lot) Percentage of tardness Percentage of on-tme delvery Avg. Tardness (day) Table 11. Analyss of on-tme delvery (unt: lot). release tme control. Only 1.25% of the total job orders have an error n release predcton of more than 0.6 days. Ths mples qute good control n throughput tme and throughput quantty Analyss of throughput target achevement Table 10 shows the results of throughput target achevement of the plannng perod (4 weeks). For every product type and rank, the average dfference between the planned target and the smulaton result s less than one lot. Ths means that the desgned release schedule and fxed WIP level polcy play a successful role n throughput mx and quantty control Analyss of due date performance Table 11 shows that the percentage of on tme delvery for each knd of product s qute hgh, rangng from to 99%. The rato of tardy lots s low, and the average tardness s less than 1 day. Wthout usng any due-date-orented dspatchng rule n the producton actvty control (PAC) phase, such a result reflects the value of the proposed MPS plannng and releasng method. 5. Concluson and future research Multple-prorty orders and numerous product types are a unversal phenomenon for current wafer fabrcaton. Quck response n due date settng and hgh satsfacton n on tme delvery are crtcal ssues for market competence. Ths paper has presented a plannng system for mult-prorty orders to set batch polcy, estmate cycle tme, determne a sutable system WIP level, set daly bottleneck operatons, plan a release schedule and set due date for job orders. Wthout the need of smulaton, ths system responds quckly for any change n product type and

20 Mult-prorty orders n wafer fabs 1783 rank mx, or n machne unts. The case study reveals the followng effects of the proposed system.. Accurate estmaton of the producton cycle tme for each product and level s necessary. Snce cycle tme s the foundaton for MPS n settng a proper system WIP level and n predctng the release schedule for each job order, the paper adopts a BBCT-MP module (Chung et al. 2001) for estmatng cycle tme and gets results near to those of smulaton experments.. Release nterval s determned by usng the projected throughput rate and product mx. Wth a release nterval, cycle tme estmaton and predetermned release batch sze, we can determne the tmng of each release batch. Wth release wafer lots based on the release tme, the system can produce the rght amount of products at the rght tme as predcted. The case study shows that the dfference between expected and actual release tme s qute small. Consequently, ths model has a relatvely good result n processng stable product mx and multple-prorty orders. We can plan the MPS and detal schedule effcently wthout the support of a smulaton tool. The output of ths plannng system ncludes the nformaton of producton cycle tme, proper WIP, daly move, batch polcy, release cycle lst, release tme lst, output tme lst, and due date settng of each job order. Such nformaton s qute useful for makng a decson n the producton actvty control system. Future research can be focussed on a producton schedulng plannng based on a fluctuatng product mx or capacty use level. A target plannng system that consders the ssues such as fnancal measures, cycle tme, throughput, market envronment and compettveness can alsobe researched on. Acknowledgements Ths work was partally supported by the Natonal Scence Councl, Tawan, ROC under Grant No. NSC E References Burman, D. Y., Gurrola-Gal, F. J., Nozar, A., Sathaye, S. and Stark, J. P., 1986, Performance analyss technques for IC manufacturng lnes. AT&T Techncal Journal, Chu, S. C. K., 1995, A mathematcal programmng approach towards optmsed master producton schedulng. Internatonal Journal of Producton Economcs, 38, Chung, S. H. and Huang, H. W., 1999a, The block-based cycle tme estmaton algorthm for wafer fabrcaton factores. Internatonal Journal of Industral Engneerng, 6, Chung, S. H. and Huang, H. W., 1999b, The desgn of producton actvty control polcy for wafer fabrcaton factores. Journal of the Chnese Insttute of Industral Engneers, 16, Chung, S. H., Pearn, W. L., Kang, H. Y., Chen, C. C. and Ke, W. T., 2001, Cycle tme estmaton model for wafer fabrcaton wth multple-prorty orders. Proceedngs of the Advanced Smulaton Technologes Conference, Seattle, WA. Chung, S. H., Yang, M. H. and Cheng, C. M., 1997, The desgn of due-date assgnment model and the determnaton of flow tme control parameter for the wafer fabrcaton factores. IEEE Transacton on Components, Packagng, and Manufacturng Technology, 20, Conway, R., Maxwell, W. and Mller, L. W., 1967, Theory of Schedulng (Readng: Addson-Wesley). Glassey, C. R. and Weng, W. W., 1991, Dynamc batchng heurstcs for smultaneous processng. IEEE Transactons on Semconductor Manufacturng, 4,

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