Outline. Interconnect scaling issues Polycides, silicides and metal gates Aluminum technology Copper technology

Transcription

1 Outline Interconnect scaling issues Polycides, silicides and metal gates Aluminum technology Copper technology Wire Half Pitch vs Technology Node ITRS 2002 Narrow line effects Ref: J. Gambino, IEDM,

2 Interconnect Scaling Scenarios Scale Metal Pitch with Constant Height - R, C s and J increase by scaling factor - Higher aspect ratio for gapfill / metal etch - Need for lower resistivity metal, Low-k A A /S C S SC S Scale Metal Pitch and Height R and J increase by square of scaling factor - Sidewall capacitance unchanged A C S - Aspect ratio for gapfill / metal etch unchanged - Need for very low resistivity metal with significantly improved EM performance 0.5 A /S 2 C S Why Copper? Low ρ (Resistivity) Metal Ag Cu Au Al W Bulk Resistivity [µω cm] Cu is the second best conducting element RC =! t M " L2 # ILD t ILD Dealy Time (psec) Reduced RC delay Cu+Low-k(2.0) Total Delay Al+SiO 2 Total Delay 3 Cu+Low-k(2.0) Al+SiO 2 2 Interconnect Delay Interconnect Delay Feature Size (µm) Calculations assume longest interconnect in the chip controls delay Gate Delay 4 2

3 Cu Has Excellent Reliability Al Cu Melting Point 660 ºC 083 ºC E a for Lattice Diffusion.4 ev 2.2 ev E a for Grain Boundary Diffusion ev ev high electromigration resistance J = 2.5x0 6 A/cm 2 T = 295 C Percentile > 0X Al(Cu) T 50 =.3 Hrs Cu T 50 = 47.7 Hrs Ref: S. Luce, (IBM), IEEE IITC 998 Stress Time (hours) 5 Why Cu and Low-k Dielectrics? Number of Metal Layers Al/SiO 2 Al/Low-k Cu/SiO 2 Cu/Low-k Ref: M. Bohr, IEDM Technology Generation (µm) global semiglobal local RC =! t M " L2 # ILD t ILD Better electromigration resistance, reduced resistivity and dielectric constant results in reduction in number of metal layers as more wires can by placed in lower levels of metal layers. 6 3

4 Problem: Copper Diffusion in Dielectric Films Cu atoms ionize, penetrate into the dielectric, and then accumulate in the dielectric as Cu+ space charge. 7 Copper Diffusion in Dielectric Films Bias temperature stressing is employed to characterize behavior Both field and temperature affect barrier lifetime Neutral Cu atoms and Cu ions contribute to Cu transport through dielectrics Ref: A. Loke et al., Symp. VLSI Tech. 998 Silicon nitride and oxynitride films are better barriers 8 4

5 Solutions to Problems in Copper Metallization Fast diffusion of Cu into Si and SiO 2 Poor oxidation/corrosion resistance Poor adhesion to SiO 2 Dielectrics Barrier Layer Diffusion barrier /adhesion promotor Passivation Cu Difficulty of applying conventional dry-etching technique Damascene Process Typical Damascene Process 9 Barriers/Linears Barrier/Linear Space for wire Via Dielectric Metal 0 5

6 Materials for Barriers / Liners Transition metals (Pd, Cr, Ti, Co, Ni, Pt) generally poor barriers, due to high reactivities to Cu <450 C. Exception: Ta, Mo, W... more thermally stable, but fail due to Cu diffusion through grain boundaries (polycrystalline films) Transition metal alloys: e.g., TiW. Can be deposited as amorphous films (stable up to 500 C) Transition metal - compounds: Extensively used, e.g., TiN, TaN, WN. Amorphous ternary alloys: Very stable due to high crystallization temperatures (i.e., Ta 36 S 4,N 50, Ti 34 Si 23 N 43 ) Currently PVD (sputtering/evaporation is used primarily to deposit the barrier/liner, however, step coverage is a problem. ALD is being developed for barrier/liner application. ALD PVD Interconnect Fabrication Options Positive Pattern Negative Pattern Metal Etch Dielectric Etch Dielectric Deposition Metal Deposition Metal Dielectric Planarization by CMP Metal CMP Dielectric Deposition Dielectric Photoresist Etch Stop (Dielectric) Subtractive Etch (Conventional Approach) 2 Damascene 6

7 Cu Damascene Flow Options Single Damascene Dual Damascene Via Pattern & Etch Via & Lead Pattern & Etch Barrier & Cu Dep Cu Via CMP Barrier & Cu Dep Nitride + Oxide Dep Lead Via Cu CMP Lead Pattern & Etch + Barrier & Cu Dep Oxide Lead Via Cu Lead CMP Copper Conductive Barrier Dielectric Etch Stop/Barrier 3 Deposition methods of Cu films: PVD Various deposition methods for Cu metallization has been attempted : Physical vapor deposition (PVD) : Evaporation, Sputtering conventional metal deposition technique: widely used for Al interconnects produce Cu films with strong () texture and smooth surface, in general poor step coverage: not tolerable for filling high-aspect ratio features Deposited film 4 7

8 Deposition methods: CVD 5 Various deposition methods for Cu metallization has been attempted : Physical vapor deposition (PVD) : Evaporation, Sputtering conventional metal deposition technique: widely used for Al interconnects produce Cu films with strong () texture and smooth surface, in general poor step coverage: not tolerable for filling high-aspect ratio features Chemical vapor deposition (CVD) conformal deposition with excellent step coverage in high-aspect ratio holes and vias costly in processing and maintenance generally produce Cu films with fine grain size, weak () texture and rough surface Electrochemical deposition (EVD) Why Cu Electroplating?: Good step coverage and filling capability comparable to CVD process (0.25 µm) Compatible with low-k dielectrics Generally produce strong () texture of Cu film Produce much larger sized grain structure than any other deposition methods through self-annealing process 6 8

9 Deposition methods: Electroplating Copper electroplating Chemistry : Plating Bath : standard sulfuric acid copper sulfate bath (H 2 SO 4, CuSO 4 solution) Additives to improve the film quality Dissociation : CuSO 4 Cu 2+ + SO 2-4 (solution) Oxidation: Cu Cu e - (anode) Reduction : Cu e - Cu (cathode, i.e., wafer) 7 Trench Filling PVD vs. Electroplating of Cu non-conformal "bottom-up filling" ("superfilling") void PVD Electroplating 8 9

10 DEFINITION Additives for Copper ECD Mixture of organic molecules and chloride ion which are adsorbed at the copper surface during plating to: -- enhance thickness distribution and feature fill -- control copper grain structure and thus ductility, hardness, stress, and surface smoothness COMPONENTS Most commercial mixtures use 3 or more organic components and chloride ion which adsorb at the cathode during plating. Brighteners (Accelerators) Levelers Carriers Chloride Suppressors 9 Mechanisms of Superconformal Cu plating t = 0 sec t = 2 sec = Accelerators = Suppressors c = Chloride ions L = Levelers Wafers immersed in plating bath. Additives not yet adsorbed on Cu seed. Additives adsorbed on Cu seed. No current flow. t = 0 sec t = 20 sec Conformal plating begins. Accelerators accumulate at bottom of via, displacing less strongly absorbed additives. Accumulation of accelerator due to reduced surface area in narrow features, causes rapid growth at bottom of via. Ref: J. Reid et al., Solid St. Tech., 43, 86 (2000) D. Josell et al., J. Electrochem. Soc., 48, C767 (200) 20 0

11 Brighteners (Accelerators) Adsorbs on copper metal during plating, participates in charge transfer reaction. Determines Cu growth characteristics with major impact on metallurgy Levelers Reduce growth rate of copper at protrusions and edges to yield a smooth final deposit surface. Effectively increases polarization resistance at high growth areas by inhibiting growth to a degree proportional to mass transfer to localized sites Carriers Carriers adsorbed during copper plating to form a relatively thick monolayer film at the cathode (wafer). Moderately polarizes Cu deposition by forming a barrier to diffusion of Cu 2+ ions to the surface. Chloride Adsorbs at both cathode and anode. Role of Additives Accumulates in anode film and increases anode dissolution kinetics. Modifies adsorption properties of carrier to influence thickness distribution. 2 Effect of of the seed layer on the properties of the final Cu Seed Layer Texture Plated Film Texture Seed Layer Surface Roughness Plated Film Grain Size Seed Layer Strong () texture Smooth surface Electroplated Film Strong () texture Large grain size (Thin, PVD seed preferred) Electroplating needs a seed layer of Cu as it does not occur at a dielectric surface. Properties of the final Cu layer critically depend upon the characteristics of the seed layer. The deposition of the seed layer can be done by PVD, CVD or ALD. Currently PVD is preferred, CVD and ALD being investigated 22

12 Plated Copper Fill Evolution Seed only 5 seconds 0 seconds 5 seconds 25 seconds Ref: Jonathan Reid, IITC, Trench Filling Capability of Cu Electroplating 0.3µ trenches 0.8µ vias 029µ vias Ref: Jonathan Reid, IITC,

13 Grain Size Distribution Lognormal grain size distribution (a) CVD (b) electroless plating 0. as-deposited 0.08 S = 0.6µm σ = D (µm) annealed S = 0.294µm σ = as-deposited S = 0.50µm σ = 0.38 Electroplated Cu gives bigger grain size D (µm) 0 (c) electroplating as-deposited S = 0.863µm σ = 0.76 annealed S = 2.682µm σ = Ref: H. Lee, PhD Thesis, Stanford Univ., D (µm) 25 Electromigration: CVD vs. Electroplating Time-to-Failure (sec) grain size 23 C Electroplated Cu E a = 0.89 ev e µ =.4 µm CVD Cu E a = 0.82 ev e µ =0.3 µm Ref: Ryu, et al., IEEE IRPS /T (0-3 /K) Electroplated Cu CVD Cu Electroplated Cu has higher resistance to electromigration because of its grain structure 26 3

14 Film Microstructure vs. EM Time-to-Failure Empirical relationship (for Al & Al alloys) MTF! eµ " 2 log[ I () I (200) ] 3 S. Vaidya et al., Thin Solid Films, Vol. 75, 253, 98 EM dependence on the microstructure of Cu films C Time-to-Failure (sec) () CVD Cu E a = 0.86 ev (200) CVD Cu E a = 0.8 ev Ref: Ryu, Loke, Nogami and Wong, IEEE IRPS /T (0-3 /K) 27 Self-annealing at Room Temperature t = 2 hrs µm.6 t = 60 days µm grain size (µm) days 0 days day hrs DC plating current density (ma/cm 2 ) Grains are initially small in all films but recrystallization increases their size 28 Ref: H. Lee, PhD Thesis, Stanford Univ.,

15 Thin Film Cu Resistivity Effect of Electron Scattering Reduced mobility as dimensions decrease Grain boundary scattering Surface scattering Reduced mobility as chip temperature increases Increased phonon scattering Grain Grain boundary e Surface scattering e Bulk scattering 29 Cu Resistivity: Effect of Line Width Scaling W. Steinhögl et al., Phys. Rev. B66 (2002) 30 5

16 Cu Resistivity: Effect of Line Width Scaling Model Resistivity increases as grain size decreases due to increase in density of grain boundaries which act as carrier scattering sites Resistivity increases as main conductor size decreases due to increased surface scattering W. Steinhögl et al., Phys. Rev. B66 (2002) 3 Thin Film Cu Resistivity Effect of Cu diffusion Barrier Barriers have higher resistivity Barriers can t be scaled below a minimum thickness Consumes larger area as dimensions decrease Resistivity of the composite wire is increased Cu Future Barrier Resistivity of metal wires could be much higher than bulk value 32 6

17 Cu Resistivity: Theoretical Background Barrier Barrier Effect! b =! o A AR* w b " 2 Important parameter: A b to A int ratio ρ b increase with A b to A int ratio Future: ratio may increase Cu w h AR=h/w A int =AR*w 2 Electron Surface Scattering Effect " s " o = # 3(# P)$ mfp 2d ) * % X # ' # e #kx & 3 X 5 ( # Pe #kx dx P: Fraction of electrons scattered elastically from the interface k= d/ λ mfp λ mfp : Bulk mean free path for electrons d: Smallest dimension of the interconnect Reduced electron mobility Operational temperature Copper/barrier interface quality Dimensions decrease in tiers: local, semiglobal, global P=0 Diffuse scattering Lower Mobility P= Elastic scattering No Change in Mobility Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April Cu Resistivity: Effect of Barrier barrier Cu e C PVD barrier Cu Effect of Scaling Effect of Barrier Technology IPVD Al ALD Effective resistivity (µ ohm-cm) Technology node (µm) Global 00 C PVD Cu, P=0.5 C-PVD Al P=0 P=0.5 P= I-PVD ALD: 0nm ALD: 3nm ALD: nm No Barrier Year Barriers can t be scaled and have high resistivity Surface electron scattering increases resistivity Real chips operate at higher temperatures Kapur and Saraswat, IEEE TED, April

18 Semi-global & Local Interconnects Technology node (µm) Semiglobal Temp.=00 0 C PVD I-PVD Cu, P=0.5 C-PVD Al P=0 P=0.5 P= ALD: 0nm ALD: 3nm ALD: nm No Barrier Effective resistivity (µ ohm-cm) Temp.=00 0 C Local Temp.=00 0 C Technology node (µm) PVD C-PVD Cu, P=0.5 ALD: 0nm Al ALD: 3nm P=0 P=0.5 P= ALD: nm No Barrier With ALD least resistivity rise Al resistivity rises slower than Cu. Cross over with Cu resistivity possible no 4 sided barrier smaller λ mfp => smaller k Al Cu Year Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April Cu Resistivity: Effect of Chip Temperature Effective resistivity (microohm-cm) Technology Node (µm) Global T=00 0 C T=27 0 C Year Higher temperature lower mobility higher resistivity Realistic Values at 35 nm node: P=0.5, temp=00 0 C - local ~ 5 µω-cm - semi-global ~ 4.2 µω-cm - global ~ 3.2 µω-cm Kapur, McVittie & Saraswat IEEE Trans. Electron Dev. April

19 Summary Interconnect scaling issues Thermal issues Electromigration Aluminum technology Copper technology 37 9