PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

Save this PDF as:
Size: px
Start display at page:

Download "PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam"


1 PHYS 534 (Fall 2008) Process Integration Srikar Vengallatore, McGill University 1 OUTLINE Examples of PROCESS FLOW SEQUENCES >Semiconductor diode >Surface-Micromachined Beam Critical Issues in Process Integration 2 1

2 Process Integration Efficient and cost-effective sequencing of unit processes to manufacture and package microscale structures and devices to meet specified performance and reliability targets 3 Process Flow for a Diode SiO 2 p+ implant layer n+ implant layer Al p-type Si substrate [Senturia] 4 2

3 SiO 2 p+ implant layer n+ implant layer Al p-type Si substrate Metallization Implant p+ Implant n+ 5 Detailed Process Flow for a Diode Starting Material: (100)-oriented, single-crystal silicon, double-side polished; p-type (10 15 /cm 3 boron) Front Side Reverse Side (Back-side) Step 1 Clean Standard RCA cleans with HF dip 6 3

4 Cleaning is an Art RCA Cleans are standard. Step 1: Sulfuric acid and Hydrogen peroxide (7:3) (Removes all organic coatings) Step 2: Water: Hydrogen peroxide: Ammonium hydroxide (5:1:1) (Removes all organic residues) Step 3: Water: HCl: Hydrogen peroxide (6:1:1) (Removes all ionic contaminants) Need RCA Cleans before every high-temperature step (oxidation, diffusion, or CVD) RCA: Radio Corporation of America 7 Dip in Hydrofluoric Acid (HF) after RCA Cleans Silicon has a very strong tendency to oxidize When Si is exposed to oxygen, a thin SiO 2 layer is formed 2 This oxide is referred to as Native Oxide If the native oxide must be removed, then dip the silicon wafer in HF for a few minutes Step 1: RCA Cleans + HF Dip 8 4

5 Step 2 Oxidation Grow 0.1 μm SiO 2 on both surfaces Choice: wet or dry? p-si substrate SiO 2 9 Step 3 Protect front Spin photoresist on front side and prebake Protect front surface from contamination during implantation Step 4 Ion implant Implant boron. Target: /cm 3 after all thermal annealing Back surface 10 5

6 Step 5 Strip photoresist from front surface Front surface Si substrate SiO 2 p+ implant layer 11 Step 6 Photolithography Spin cast resist, prebake, expose top surface using Mask 1. Develop, post-bake. Mask 1 (implant) Process parameters: Characteristics of mask aligner Type of photoresist (positive vs. negative) Exposure time Development time 12 6

7 Structure after photolithographic patterning: SiO 2 Si substrate p+ implant layer Photoresist 13 Step 7 Implantation Ion implant phosphorous. Target = /cm 3 after all thermal treatments SiO 2 p+ implant layer Photoresist n+ implant layer 14 7

8 After Step 7: SiO 2 p+ implant layer Photoresist n+ implant layer Step 8 Remove photoresist from front surface (acetone dip, followed by oxygen plasma) Note: Front surface implanted region cannot be identified using visual inspection! 15 Step 9 Clean RCA Cleans without HF dip Step 10 Drive-in Thermal treatment to achieve desired implant profile Junction depth Design Specifications: Junction depth = 1 μm Surface concentration = /cm 3 >Sophisticated process modeling tools are available to estimate process parameters 16 8

9 Step 11 Photolithography using Mask 2 Mask 1 (implant) Mask 2 (via) Process parameters: SiO 2 p+ implant layer Photoresist n+ implant layer ALIGNMENT type of photoresist Exposure & development conditions 17 Step 12 Etch oxide with buffered HF to open contacts in SiO 2 (Note: SiO 2 on back-surface is fully removed in this process) Step 13: Remove photoresist (acetone + oxygen plasma) 18 9

10 Step 14: Step 15: Clean (RCA without HF dip) Metallization (1 μm Al) on front side SiO 2 p+ implant layer n+ implant layer Al Evaporate or Sputter? 19 Step 16: Photolithography with Mask 3 Mask 1 (implant) Mask 2 (via) Mask 3 (metal) Step 17 Etch aluminum (PAN etch) Step 18 Strip pphotoresist SiO 2 p+ implant layer n+ implant layer Al 20 10

11 Step 19 Blanket metal deposition on back surface SiO 2 p+ implant layer n+ implant layer Al 21 But, what about PACKAGING? Step 20: Die saw (separate individual chips) Die-saw 6-inch Wafer 1 mm Chip 22 11

12 Step 21: Attach bottom metal to ceramic package Wire bond to front surface Al pad. (CMC) 23 Metallization Aluminum Bond pad Chip (

13 Why is Process Integration Difficult? Attention to local and global details Known Unit Processes versus Unknown Inter-Process Interactions >Learn to identify critical process steps and parameters >Learn from experience 25 Process Design Issues Device geometry Backside processing Institutional constraints System partitioning Packaging Process partitioning Cleaning requirements Cross-contamination constraints Thermal constraints Material property p control Mechanical & thermal stability Process accuracy Alignment features Wafer architecture Die separation 26 13

14 VISUALIZATION OF DEVICE GEOMETRY Sophisticated Computer-Aided-Design tools for MEMS (Memulator from Coventor) Draw multiple cross-sections! 27 Do NOT assume that one cross-section will reveal all problems Example 2: Process Flow For Surface-Micromachined Beam Polycrystalline Silicon (polysilicon) Captured Silicon oxide Single-Crystal Si Substrate This process illustrates the importance of sketching multiple cross-sections 28 14

15 Silicon oxide Silicon oxide mask A A After Photolithography and etch 29 Conformal Polysilicon (LPCVD) Silicon oxide mask A A Photolithography h using polysilicon mask Polysilicon Mask 30 15

16 Release etch 31 B Silicon oxide mask A A Polysilicon mask B Cross-section A-A Cross-section B-B 32 16

17 Packaging Microelectronic Devices Goals:-Protect chip from environment -Provide electrical connectivity -Provide heat flow path (Modern ICs dissipate enormous power) Standard Approach: -Dice up wafer using die-saw -Use standard ceramic/plastic packages (commercially available) -Consideration of packaging-induced stresses can be important 33 Packaging MEMS Need multiple interconnections -Fluidic -Electrical -Optical Interaction with environment can be critical (ex: pressure sensors) Costly! (35% Silicon chip; 45% package; 20% calibration & test) Disposable blood pressure sensors (Motorola) 34 17

18 Au wire bonds 10 μm Polysilicon beams Currently being commercialized: 35 Die Separation Die-sawing is a violent operation (wet & dirty) Excellent for microelectronics (no-moving parts) Die-saw can cause micromechanical structures to fracture One solution: encapsulate moving parts during die-saw 36 18

19 Release Etch: Before vs. After Die-Saw Release etch after die-saw: Structures are immobile and protected during die-saw But, Low throughput (process each device individually) Si Wafer Release etch (Clean room packaging!) 37 Release Etch at Wafer Level: Much higher throughput (Analog Devices) But, risk damage during die-saw Hence, protect structures using encapsulation schemes (A) Silicon Wafer (B) Release etch (C) Protective encapsulation Via wafer bonding (D) (E) Die-saw and Remove encapsulation 38 19

20 Thermal Constraints A change in temperature affects ALL materials on device. Ex: Remove all photoresist before high-temperature anneal Does annealing temperature exceed melting point of metallization? Best Practice: After each process step, assign a permissible temperature window for next step 39 Simple Example Starting material: Silicon 20 o C < T < 1414 o C (Melting point of Si) polyimide 20 o C < T < 300 o C (Softening point of polyimide) Al 20 o C < T < 615 o C (melting point of Al) 40 20

21 Diffusion of Dopants x Diffusivity, D(T) m 2 /s Time, t s Diffusion length, L = Dt First order estimate of total diffusion length in N step process = N Dt n= 0 41 Mechanical Stability of Intermediate Structures Wafer bonding Sealed cavity under pressure Plasma etch (at low pressure) Pressure differential can fracture membrane before etch is complete 42 21

22 Process Accuracy Variation across wafer (ex: thickness of evaporated metals; DRIE etch rates) Variation from wafer to wafer (Stress in LPCVD films) Random variations in process parameters (ex: temperature of tube furnaces; local humidity) Alignment errors in photolithography (especially important in anisotropic wet bulk micromachining) 43 Depiction of Thin Film Deposition w H Non-conformal Perfectly conformal h Cusp formation 44 22

23 Alignment Features Design of alignment features critical aspect of photolithography Target feature on wafer Alignment feature on mask Perfect alignment during photolithography 45 Many steps leave no visible indications (for example, implantation) Blanket metal depositions can obscure topography depending on relative thickness and conformality 46 23

24 Wafer Architecture Not all locations on wafer are equivalent Deep Reactive Ion Etching Middle of wafer 3 cm away (2.6 %) 42.3 μm 43.4 μm 47 Material Property Control Residual Stresses Strength Adhesion Affected by temperature; e; Local and global details. Phase stability Very few predictive models Need measurements early in process design! 48 24

25 Phase Stability Diffusion barrier After high temperature step After high temperature step Interdiffusion & Compound formation Diffusion barrier prevents composition change 49 Adhesion Strength of attachment of adjacent surfaces Film surface energy γ f Substrate surface energy γ s Interfacial energy γ fs 50 25

26 Adhesion depends on Interface Characteristics Abrupt interface Compound interface Diffuse interface Mechanical locking 51 Guidelines for Improving Adhesion Use of adhesion-promoting layers is common. For ex: gold does not adhere to silicon. Hence, deposit thin Cr or Ti layers first; immediately deposit gold. Surface cleanliness is critical (Identify and eliminate contaminants organics, C, oxides, ) Use ion beams to modify surfaces. Activate polymeric films with suitable surface groups [Ohring] 52 26

27 STRESS CONTROL STRATEGIES Explore bulk-micromachining options using stress-free wafers and direct wafer bonding Identify sources of stresses (external; thermal; intrinsic) >Thermal stresses: material properties (α); ΔΤ >Intrinsic stresses: Process selection If intrinsic stresses cannot be reduced, try stress balancing 53 STRESS BALANCED STRUCTURES Compressive layer (σ 1, h 1 ) SUBSTRATE Tensile layer (σ 2, h 2 ) Condition for zero net stress: σ1 h1 + σ 2h2 = 0 If films are comparable in thickness and stiffness to substrate, then need to negate bending moments as well SUBSTRATE 54 27

28 Guidelines for Process Integration Address local and global considerations simultaneously (esp. thermal constraints) Address packaging, residual stresses, adhesion, & stability early in process design (often with targeted experiments) Examine all possible cross-sections. Sophisticated visualization tools now emerging Unlimited opportunities for innovation. Be Creative! 55 Overview of Microdevice Manufacture Starting Material: Substrate (wafer) Subtractive Processes Wet etching Dry etching Plasma etching DRIE Polishing Processes Patterning Additive Processes Photolithography E-beam lithography Ion beam lithography Soft lithography Evaporation Sputtering CVD Electrodeposition Wafer bonding Package Microdevice 56 28

29 Microfabrication = SUMMARY ESSENTIAL IDEAS + DETAILS Class notes Handbooks Journals Google + IMAGINATION! 57 Aluminum Choice of sectioning Choice of sacrificial materials Choice of etching methods Choice of deposition techniques Silicon 58 29