CMOS Factory Laboratory

Transcription

1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING CMOS Factory Laboratory Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Tel (585) Department webpage: CMOS_Factory.ppt Page 1

2 INTRODUCTION This document contains items that should be included in the students lab notebook. This includes general information about the processes and products made in the student factory. Page 2

3 INTRODUCTION RIT is supporting two different CMOS process technologies. The older p-well CMOS and SMFL-CMOS have been phased out. The SUB-CMOS process is used for standard 3 Volt Digital and Analog integrated circuits. This is the technology of choice for teaching circuit design and fabricating CMOS circuits at RIT. The ADV- CMOS process is intended to introduce our students to process technology that is close to industry state-of-the-art. This process is used to build test structures and develop new technologies at RIT. RIT p-well CMOS l = 4 µm Lmin = 8 µm RIT SMFL-CMOS l = 1 µm Lmin = 2 µm RIT Subµ-CMOS l = 0.5 µm Lmin = 1.0 µm RIT Advanced-CMOS l = 0.25 µm Lmin = 0.5 µm Page 3

4 RIT SUBµ CMOS RIT Subµ CMOS 150 mm wafers Nsub = 1E15 cm-3 Nn-well = 3E16 cm-3 Xj = 2.5 µm Np-well = 1E16 cm-3 Xj = 3.0 µm LOCOS Field Ox = 6000 Å Xox = 150 Å Lmin= 1.0 µm LDD/Side Wall Spacers 2 Layers Aluminum L Long Channel Behavior 3 Volt Technology VT s = +/ Volt Robust Process (always works) Fully Characterized (SPICE) Page 4

5 RIT SUBµ CMOS N+ Poly NMOSFET 0.75 µm Aluminum PMOSFET p+ well contact N+ D/S LDD P-well 6000 Å Field Oxide N-well LDD P+ D/S n+ well contact Channel Stop P-type Substrate 10 ohm-cm Page 5

6 SUB-CMOS 150 PROCESS SUB-CMOS Versions CL01 2. OX05--- pad oxide, Tube 4 3. CV02- Si3N4-1500Å 4. PH03 1- JG nwell 5. ET29 Nitride Etch 6. IM01 n-well 7. ET07 Resist Strip 8. CL01 9. OX04 well oxide, Tube ET19 Hot Phos Si3N4 11. IM01 p-well 12. OX06 well drive, Tube ET06 - Oxide Etch 14. CL OX05 pad oxide, Tube CV02 Si3N Å 17. PH03 2 JG Active 18. ET29 Nitride Etch 19. ET07 Resist Strip 20. PH03 - -Pwell Stop 21. IM01- stop 22. ET07 Resist Strip 23. CL OX04 field, Tube ET19 Hot Phos Si3N4 26. ET06 Oxide Etch 27. OX04 Kooi, Tube IM01 Blanket Vt 29. PH03 4-PMOS Vt Adjust 30. IM01 - Vt 31. ET07 Resist Strip 32. ET06 Oxide Etch 33. CL OX06 gate, Tube CV01 Poly 5000A 36. IM01 - dope poly 37. OX08 Anneal, Tube DE01 4 pt Probe 39. PH03-5-JG poly 40. ET08 Poly Etch 41. ET07 Resist Strip 42. PH n-ldd 43. IM ET07 Resist Strip 45. PH p-ldd 46. IM ET07 Resist Strip 48. CL CV03 TEOS, 5000A 50. ET10 - Spacer Etch 51. PH N+D/S 52. IM01 N+D/S 53. ET07 Resist Strip 54. PH03 9 P+ D/S 55. IM01 P+ D/S 56. ET07 Resist Strip 57. CL01 Special - No HF Dip 58. OX08 DS Anneal, Tube CV03 TEOS, 4000A 60. PH03 10 CC 61. ET26 - CC Etch 62. ET07 Resist Strip 63. CL01 Special - Two HF Dips 64. ME01 Metal 1 Dep 65. PH metal 66. ET15 plasma Etch Al 67. ET07 Resist Strip 68. SI01 - Sinter 69. CV03 TEOS- 4000Å 70. PH03 VIA 71. ET26 Via Etch 72. ET07 Resist Strop 73. ME01 Metal 2 Dep 74. PH03- M2 75. ET15 plasma Etch Al 76. ET07 - Resist Strip 77. SEM1 78. TE TE TE TE Page 6

7 ASML 5500/200 NA = 0.48 to 0.60 variable = 0.35 to 0.85 variable With Variable Kohler, or Variable Annular illumination Resolution = K1 l/na = ~ 0.35µm for NA=0.6, =0.85 Depth of Focus = k 2 l/(na) 2 = > 1.0 µm for NA = 0.6 i-line Stepper l = 365 nm 22 x 27 mm Field Size Page 7

8 RIT SUB-CMOS PROCESS N+ Poly NMOSFET 0.75 µm Aluminum PMOSFET LVL 1 n-well LVL 6 P-LDD p+ well contact 6000 Å Field Oxide N+ D/S LDD LDD P+ D/S n+ well contact Channel Stop P-type Substrate 10 ohm-cm CC P-well N-well POLY ACTIVE P SELECT LVL 2 - ACTIVE LVL 3 - STOP LVL 4 - PMOS VT LVL 7 N-LDD LVL 8 - P+ D/S LVL 9 - N+ D/S METAL LVL 10 - CC N SELECT N-WELL LVL 5 - POLY 11 PHOTO LEVELS LVL 11 - METAL

9 ASML RETICLE Chrome Side Mirrored 90 Chip Bottom at Bottom Non Chrome Side As loaded into Reticle Pod, Chrome Down, Reticle Pre- Alignment Stars Sticking out of Pod Page 9

10 RIT ADVANCED CMOS RIT Advanced CMOS 150 mm Wafers Nsub = 1E15 cm-3 or 10 ohm-cm, n or p Nn-well = 1E17 cm-3 Xj = 2.5 µm L Np-well = 1E17 cm-3 Xj = 2.5 µm Shallow Trench Isolation Field Ox = 4000 Å Dual Doped Gate n+ and p+ Long Xox = 100 Å Channel Lmin= 0.5 µm Behavior LDD/Nitride Side Wall Spacers TiSi2 Silicide Tungsten Plugs, CMP, 2 Layers Aluminum Page 10

11 RIT ADVANCED CMOS NMOSFET N+ Poly PMOSFET P+ Poly p+ well contact N+ D/S LDD P-well N-well LDD P+ D/S n+ well contact Page 11

12 ADV-CMOS 150 PROCESS ADV-CMOS Versions 150, Two level Metal 1. OX05--- pad oxide 500 Å, Tube PH03 level 5 - P-well retrograde 2. CV Å Si 3 N 4 Deposition 22. IM01 1E14, B 11, 45 KeV 3. PH03 level 1- STI 23. ET07 ash 4. ET29 - etch Nitride 24. ET06 etch 500 Å pad oxide 5. ET07 ash 25. CL01 pre-gate oxide RCA clean 6. CL01 RCA clean 26. ET06 etch native oxide 7. OX04 First Oxide Tube OX06 30 Å gate oxide, Tube 4 8. ET06 Etch Oxide 28. CV01 poly deposition, 2500 Å 9. OX04 2 nd Oxide Tube PH03 level 6 - poly gate 10. ET19 Etch Nitride 30. ET08 poly gate plasma etch 11. PH03 level 2 - N-well 31. ET07 ash 12. IM01 5E13, P 31, 170 KeV 32. CL01 RCA clean 13. ET07 ash 33. OX05 poly re-ox, 250 Å, Tube PH03 level 3 - P-well 34. PH03 level 7 - p-ldd 15. IM01 7E13, B 11, 100 KeV 35. IM01 9E14, BF 2, 20 KeV 16. ET07 ash 36. ET07 ash 17. OX06 Well Drive, Tube PH03 level 8 - n-ldd 18. PH03 level 4 - N-well retrograde 38. IM01 5E15, P 31, 20 KeV 19. IM01 9E13, P 31, 70 KeV 39. ET07 ash 20. ET07 - ash 40. CL01 RCA clean 41. CV02 nitride spacer 2500Å 42. ET39 sidewall spacer etch 43. PH03 level 9 - N+D/S 44. IM01 1E15, P 31, 25 KeV 45. ET07 ash 46. PH03 level 10 - P+ D/S 47. IM01 5E15 BF 2, 27 KeV 48. ET07 ash 49. CL01 RCA clean 50. OX08 DS Anneal, RTP 51. ET06 Silicide pad ox etch 52. ME03 HF dip & Ti Sputter 53. RT01 RTP 5 sec, 650C 54. ET11 Unreacted Ti Etch 55. RT02 RTP 5 sec, 700C 56. CV03 TEOS, P-5000, 3000Å 57. PH03 level 11 - CC 58. ET06 CC etch 59. ET07 ash 60. CL01 RCA clean 61. ME01 Aluminum 62. PH03 level 12-metal 63. ET15 plasma Al Etch 64. ET07 ash 65. CV03 TEOS 66. PH03 Via 67. ET26 Via Etch 68. ME01 Al Deposition 69. PH03 Metal ET07 - Ash 72. SI01 sinter 73. SEM1 74. TE TE TE TE04 L = 0.5 m V DD = 3.0 V V TN = 0.75 V V TP = V (Revision ) Page 12

13 RIT ADVANCED CMOS PROCESS NMOSFET PMOSFET N+ Poly P+ Poly LVL 1 - STI LVL 7 - PLDD p+ well contact P-well N+ D/S LDD N-well LDD P+ D/S n+ well contact LVL 2 - NWell LVL 8 - NLDD 12 PHOTO LEVELS LVL 3 - Pwell LVL 9 N+D/S POLY CC ACTIVE P SELECT LVL 4 - VTP LVL 10 P+D/S METAL LVL 5 - VTN LVL 11 - CC N SELECT N-WELL LVL 6 - POLY LVL 12 METAL 1

14 MASK ORDER CONTINUED Page 14

15 PRODUCTS New John Galt Test Chip (Sub-CMOS and Adv-CMOS) Older Obsolete Chips: Mixed Analog/Digital Test Chip (Sub-CMOS Process) Test Chip (Advanced CMOS Process) John Galt Test Chip (Sub-CMOS Process) 4-Bit Microprocessor (Sub-CMOS Process) Analog to Digital Converter (Sub-CMOS Process) Page 15

16 JOHN GALT CMOS TESTCHIP 2010 Page 16

17 FACTORY TEAMS - TUESDAY Red Group Orange Group Yellow Group Green Group Blue Group Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc. Diffusion Bruce Furnace AG-RTP Blue M Oven Nanospec Spectromap CDE Resistivity Map Lithography Canon Stepper SSI Track CD Linewidth Overlay Branson Asher Discipline PVD/Plasma Etch CVD/PECVD CVC601 Drytech Quad Lam490 Lam4600 Nanospec Tencore P2 ASM 6 LPCVD P-5000 Nanospec Spectromap Varian 350D While in each discipline the students will Process lots requiring steps in that discipline Perform follow up Inspection and Metrology Investigate and Update SPC data Monitor non-device process metrics Perform a pass down at the end of (2 weeks) Track lots in and out of Mesa Wet Etch/CMP Al Wet Etch BOE Etch RCA Clean Hot Phos Nitride Etch BOE Solvent Strip CMP and CMP Clean Nanospec Surfscan SEM Page 17

18 FACTORY TEAMS - THURSDAY Red Grou 1. Chakrakeerthi 2. Shreyas 3. Orange Group 1. Pooja 2. Timothy 3. Yellow Group 1. Rahnuma 2. Veena 3. Green Group 1. Venkatesh 2. Muhammad 3. Blue Group 1. Ky-El 2. Arshia 3. Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc. Diffusion Bruce Furnace AG-RTP Blue M Oven Nanospec Spectromap CDE Resistivity Map Lithography Canon Stepper SSI Track CD Linewidth Overlay Branson Asher Discipline PVD/Plasma Etch CVD/PECVD CVC601 Drytech Quad Lam490 Lam4600 Nanospec Tencore P2 ASM 6 LPCVD P-5000 Nanospec Spectromap Varian 350D While in each discipline the students will Process lots requiring steps in that discipline Perform follow up Inspection and Metrology Investigate and Update SPC data Monitor non-device process metrics Perform a pass down at the end of (2 weeks) Track lots in and out of Mesa Wet Etch/CMP Al Wet Etch BOE Etch RCA Clean Hot Phos Nitride Etch BOE Solvent Strip CMP and CMP Clean Nanospec Surfscan SEM Page 18

19 EXAMPLE TEAM REPORT AT END OF ROTATION Discipline: Lithography Date: Nov 30- Dec 8, 2017 Group Members: Matt McQuillan, Dave Pawlik Lot Advancement: F CC Photo Changed Stepper Job to Align using TVPA Marks Only added 2 µm shift to alignment key locations on pg 4/ in process file F Resist Strip F Active Photo F LDDP Photo F Resist Strip-Changed Stepper Job to Align using TVPA Marks Only F P-Well Photo-Changed Stepper Job to Align using TVPA Marks Only F Resist Strip Other: Short Loop Resist Coat Thickness measurement for Coat.rcp, Xpr=1.0 µm Branson Asher often gives purge timeout error, select continue Page 19

20 Dr. Lynn Fuller Red (Diffusion) Orange (Lithography) Yellow (Plasma Etch) Green (Implant/CVD) Blue (wet Etch) Date: Lot Status Report Lot No Product Process / Version Current operation Q P STEP Next Operation Qty Comments F JOHN GALT SUB-CMOS 150 PH03 X 70 ET26 2 ORANGE F JOHN GALT SUB-CMOS 150 IM01 X 46 ET07 4 YELLOW F JOHN GALT SUB-CMOS 150 CV01 X 35 IM01 2 GREEN F JOHN GALT SUB-CMOS 150 ET06 X 26 OX04 3 BLUE F JOHN GALT SUB-CMOS 150 OX04 X 9 ET19 4 RED, TUBE 1 F JOHN GALT SUB-CMOS 150 CL01 X 1 OX05 3 BLUE Time: 8:00 am F JOHN GALT ADV-CMOS 150 OX05 X 1 CV02 3 RED, TUBE 4 ORANGE determine correct exposure time for lot numbers using MA150 contact exposure - prepare wafers for testing aluminum plasma etch - test completed wafers

21 OPERATOR FLOW CHART FOR FACTORY WORK START Access MESA Lot Status In Queue? Yes Find Queue Status Step Number Current Operation Next Operation Quantity No On Hold? Yes LOT SELECTION RULES Do Photo first Do Oldest Lot Next Separate Lots Current Step Match Skill Level Use Equipment that is Up No Mesa History Who Did Move-In Do Move-In Start Run Timer Continue A Yes Find Wafers Prelininary Quality Check Pass? No INITIAL QUALITY CHECK Count Wafers Check Picture Log Book Think Refer to Previous Process Step Check MESA Move-Out Comments See Lab Instructor On Hold? No Check Equipment Status Yes See Lab Instructor Contact Person Determine What To Do Next Do Work Follow MESA Instructions Exactly Final Quality Check FINAL QUALITY CHECK Count Wafers Check Picture Log Book Think Do Results Make Sense? Apply Lot Selection Rules Continue A See Lab Instructor No Pass? Yes Stop Run Timer Move Out Record Data Clean Up Return Wafers Return Masks END Page 21

22 SPC CHARTS SPC6SC_FO Field Oxide Thickness SPC6SC_GOX Gate Oxide Thickness SPC6SC_KOX Kooi Oxide Thickness SPC6SC_LTO LTO/TEOX Oxide Thickness SPC6SC_MTL Metal Thickness SPC6SC_N1 Nitride Thickness (1500Å) SPC6SC_N2 Nitride Thickness (3500Å) SPC6SC_PADPad Oxide Thickness SPC6SC_POL Poly Thickness SPC6SC_WO Well Oxide Thickness SPC6SCPROS Poly Sheet Resistance Page 22

23 NWA QUALITY ANALYST, SPC CHART Pad Oxide Target 500Å USL 600Å LSL 400Å Mean 535Å Std Dev 25Å Cpk Cp Page 23

24 MANUFACTURING IMPROVEMENT If no factory lots are available in a specific discipline then group will do manufacturing improvement projects. For Example: BOE Etch rate verification RTP Tool operation and recipe verification PECVD Tool operation and deposition rate verification,teos Oxide Resist Coat Thickness Measurement using Spectromap for Coat.rcp and CoatMtl.rcp Recipes used by Factory SPC Chart verification, evaluation and process capability improvement Verify all MESA picture documents are correct Verify MESA instructions are correct Page 24