ASIC Physical Design CMOS Processes

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1 ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI Design Global Foundries: BiCMOS_8HP8XP_Training.pdf BiCMOS_8HP_Design_Manual.pdf

2 Physical design process overview CMOS transistor structure and fabrication steps Standard cell layouts Creation, verification & characterization of a standard-cell based logic circuit block Creation of a chip from circuit blocks 2

3 ASIC layout 3

4 ASIC Design Flow Behavioral Design Verify Function DFT/BIST & ATPG Gate-Level Netlist Verify Function Transistor-Level Netlist Verify Function & Timing DRC & LVS Verification Physical Layout Verify Timing 4 Mask Data

5 ASIC Design Flow 5

6 IC Floorplan 6

7 CMOS standard cell layout (generic) 7 Source: Weste CMOS VLSI Design

8 BiCMOS8HP NAND2_A Cell Yellow Pins Orange = Poly Blue = Metal1 (LEF file) 8 Cadence Encounter Cell Viewer Tool

9 BiCMOS8HP DFFS_B Cell (LEF file) Yellow Pins Orange = Poly Blue = Metal1 9 Cadence Encounter Cell Viewer Tool

10 Standard Cell-Based Block 10

11 Global Foundries BiCMOS8HP process cross-section Passivation 11

12 BiCMOS8HP process cross-section External Connections Via Via Aluminum Via Via Copper PC = Polysilicon 12 CA = Contact to diffusion/poly

13 BiCMOS8HP metallization options: AM Analog Metal (RF wiring) 13

14 Basic N-channel MOS transistor drain V GS + W L + V DS V GS + gate so urce bulk + V DS gate T ox p-type n-type so urce electrons E x mobile channel charge n-type drain depletion region fixed depletion charge bulk GND or VSS 14

15 CMOS Inverter Cross-Section 15 Source: Weste CMOS VLSI Design

16 Inverter cross-section with well and substrate contacts 16 Source: Weste CMOS VLSI Design

17 IC fabrication process hour wafer furnace spin resist grow crystal sa w grow oxide mask resist oxide etch As Grow oxide SiO2 5. Apply photoresist 6. UV light exposes resist 7. Remove exposed resist 8. Etch exposed oxide Implant ions in exposed substrate 11. Strip resist 12. Etch oxide

18 CMOS Process steps P-substrate SiO2 layer Photoresist Expose and etch Etch SiO2 Remove photoresist Implant n-well Remove SiO2 18 Source: Weste CMOS VLSI Design

19 CMOS Process steps Deposit poly Etch Deposit SiO2 Etch Diffusion Remove SiO2 19 Source: Weste CMOS VLSI Design

20 Inverter mask set Generated by IC layout tools Layout is a set of patterns for each layer. N-well Poly N+ diffusion P+ diffusion Contacts Metal 20 Source: Weste CMOS VLSI Design

21 Inverter mask set 21

22 Standard Cell Mask Set (Submitted to foundry) Source: Smith, Figure

23 MOSIS fabrication processes ( TSMC Fabrication Processes 28, 40, 65, 90, 130, 180 and 350 nanometer processes. Tiny2 program is also available on 65 and 180nm processes. GlobalFoundries Fabrication Processes 14 nm, 28 nm, 40 nm, 55 nm, 0.13 µm,0.18 µm, 9HP (90 nm), 8HP (0. 13 µm), 8XP (0.13 µm), 7WL (0.18 µm), 7RF SOI (0.18 µm) 7SW (0. 18 µm) 9WG (90 nm), 9WG (90 nm), and TinyChip processes. ON Semiconductor Fabrication Processes 0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS. ams AG Fabrication Processes 180 and 350 nanometer processes - CMOS and high voltage CMOS and SiGe-BiCMOS. AIM Fabrication Processes AIM Photonics Fabrication 23

24 (Older) MOSIS fab processes ( AMI bought by ON Semiconductor: TSMC (Taiwan Semiconductor): =ON =ON Mentor Graphics ASIC Design Kit 24 Scalable CMOS Source: Weste CMOS VLSI Design

25 Scalable CMOS process design rules w ell 2. 2 active 3. 3 poly 10 (1.1) 3 (2.1) 5 (2.3) 3 (2.4) nwell nwell 3 0 or 4 (2.2) (2.5) nwell pdiff pdiff ndiff 0 (1.4) 9 (1.2) nwell pwell 4. 4 select pwell poly 2 (4.2) hot ndiff n-se lect p-se lect pdiff pwell ndiff p-se lect ndiff pdiff 3 (2.1) 5 (2.3) 3 (2.4) pwell pdiff nwell n-se lect ndiff 7. metal via1 1 (7.3) pdiff poly 3 (7.1) 2 (8.4) poly 2 (8.5) via1 3 1 (8.3) metal2 co ntact (7.2a) m1 m2 active m1 co ntact poly 2 (8.5) (8.1) (7.2b) 3 (8.2) ndiff 1 (7.4) 9. metal2 15. metal overglass (microns) 14. via2 m2 via1 3 (9.2b) 4 (9.2a) m1 0 or 6 (1.3) 3 (9.1) 1 (9.3) 1 (4.3) 2 2 (14.1) m2 via2 3 (14.2) 2 (14.4) m2 3 (2.2) m3 via1 1 (14.3) 3 (4.1) 0 or 4 (2.5) m3 4 (15.2) 5. 5 poly contact via active contact 2 (15.3) 1.5 (6.2a) 6 (15.1) 2 (3.2) 1.5 (5.2a) poly 2 2 (6.1a) glass 1 (3.5) 2 (6.3a) 6 (10.3) 1.5 (6.2a) m (10.1) pdiff 3 (3.4) 2 (3.3) 2 (3.1) poly 2 (5.3a) poly 2 2 (5.1a) nwell 2 (6.4a) 30 (10.4) m3 m2 15 (10.5) m1 Source: Smith, Figure 2.11

26 MOSIS Design Rules Smith text: Tables

27 MOSIS Design Rules Smith text: Tables

28 MOSIS Design Rules Smith text: Tables

29 MOSIS Design Rules Smith text: Tables

30 MOSIS Design Rules Smith text: Tables