Integrated Circuit Engineering Corporation. DRAMs

Transcription

1 DRAMs As generally known, the focus of technology in this product category continues to be complex vertical polysilicon structures to reduce cell area. This not only pushes the limits of deposition and patterning of the poly features themselves but also to develop methods of making vertical interconnections to reach down far enough to contact the active gate areas. We thus continue to see very tall stems of poly and very tall plugs. In fact the company with the smallest cell size seen to date (Micron) is forced into using dual (tungsten on poly) plugs to reach down the 2 microns from metal 1 to substrate. Likewise, trench cells have to be seven or eight microns deep, and everyone is finding ways to minimize contact to gate spacing. Hemispherical grained poly has not yet been seen in products available to us, and the use of tantalum pentoxide dielectrics keeps suffering implementation delays. 2-1

2 DRAMs HORIZONTAL DIMENSIONS (DESIGN RULES) Table 2-1

3 DRAMs VERTICAL DIMENSIONS Table 2-2

4 DRAMs DIE MATERIALS Table 2-3

5 Mitsubishi M5M465405AJ TECHNOLOGY DESCRIPTION MITSUBISHI M5M465405AJ 64Mbit (x4) CMOS EDO DRAM Introduction Ref. report SCA These parts were packaged in 32-pin plastic SOJ packages using a Lead-On-Chip Center Bond (LOCCB) technique with a dimpled paddle. They were fully functional production devices organized in a 16M x 4 design, offer an access time of 50nsecs, and operate from a 3.3V power source. The date code was 9732 (week 32 of 1997). See tables for specific dimensions and materials identification and see figures for examples of physical structures. Important/Unique Features - A unique LOCCB (lead-on-chip, center bonded) leadframe design, using a dimpled paddle. - Sub-half micron (0.35 micron) gate lengths. - Textured poly stacked cell (changed from early 64M cell design). Quality Quality of the process implementation was good, except at metal 2 steps where aluminum thinned up to 95 percent at via edges (barrier maintained continuity). In the area of layer patterning, etch definition and control were both acceptable but not particularly good. Some overetching was present at vias and contacts and patterning of both metal 2 and metal 1 left very rounded corners. Alignment and registration were good. Technology These devices were manufactured by a recessed oxidation twin-well CMOS process on a P substrate (no epi). They incorporated two levels of metal interconnect, four levels of poly and used a capacitor over bit line (COB) stacked cell design. 2-2

6 Mitsubishi M5M465405AJ Passivation consisted of a thick layer of nitride. It was not planarized but did have a polyimide die coat. The two levels of metal were defined by standard dry-etch techniques (no damascene). Metal 2 consisted of aluminum with titanium-nitride cap and barrier. Metal 1 used a titanium-nitride cap on the aluminum but had no discernible barrier. Metal 2 used standard vias to connect to metal 1. Since via cuts were overetched through the metal 1 cap into the metal 1 aluminum, metal 2 to metal 1 contact is from metal 2 aluminum through the titanium-nitride barrier to metal 1 aluminum. Tall tungsten plugs were used for metal 1 contacts to silicon. Plugs were lined with titanium-nitride underneath only (i.e., no TiN deposition after plug formation). Poly 2 (polycide) was used as a metal substitute in the decode and array areas. Intermetal dielectric layers consisted of two layers of silicon-dioxide (TEOS?) with a spin-on-glass (SOG) between for planarization (no CMP). The SOG had been subjected to an etchback. Pre-metal dielectric under the metal 1 consisted of three layers of reflow glass (BPSG) and densified/grown oxide. Four levels of polysilicon were used. Poly 4 and 2 were used almost exclusively in the array for the capacitors. Poly 4 was also used to form redundancy fuses. Poly 3 was only used in the array for capacitor plates. Poly 2 (tungsten silicide) formed the bit lines in the array, and interconnect in the decode. Poly 1 (tungsten silicide) was used to form the word lines in the array and all gates on the die. Sidewall spacers (very small) used on all gates were of oxide, providing the spacing for the LDD requirements. Buried contacts were used in the decode and array between polycide 2 and N+. Poly 3 buried contacts were used in the array. Normal implanted N+ and P+ sources/drains were employed and did not use a salicide process. Twin-wells were employed in the P substrate (no epi). A small notch or step was visible in the top of the LOCOS which was etched back to be almost planar with the substrate. No evidence of unusual gate oxides or other dielectrics was found (in the peripheral or array circuitry). Poly 4 redundancy fuses were used. Only passivation was cleared over the fuse locations. Some fuses had been activated. 2-3

7 Mitsubishi M5M465405AJ Memory Cell Structures Memory cells consisted of a stacked NMOS DRAM cell design with capacitors over bit lines. Poly 4 (sheet) was used for the common plate of the capacitors and poly 3 formed the individual capacitor plates. The poly 3 pedestals were thick and used a textured poly surface to increase surface area. Poly stems connected the individual capacitor plates to the drain diffusions of the select gates. This is a change from the design seen in 1994 on the first Mitsubishi 64Mb device (see 1995 Successful Technologies Review ). Metal 2 was not used directly in the cells. Metal 1 formed piggyback word lines. We presume the capacitor dielectric was an oxide-nitride as there was no evidence of a tantalum-pentoxide. This DRAM had the largest cell size 1.28 micron 2, of any of the DRAMs analyzed in 1997, although it had the most recent date code. Overall minimum feature size measured anywhere on these dice was the 0.2 micron polycide 2 bit lines. Minimum gate lengths were the 0.35 micron gates in the cell array. Packaging/Assembly As mentioned, these parts were packaged in 32-pin plastic SOJ packages using a Lead- On-Chip Center Bond (LOCCB) technique. The leadframe design was unique only in the fact that a dimpled paddle was used on which the die was mounted using silver epoxy. Wirebond pads on the die had a pitch of 150 microns with 60 micron spacing. Pads were 110 microns wide with 90 micron windows. Only metal 2 was used for bond pads. A patterned (at bond pads) polyimide die coat was present. 2-4

8 Mitsubishi M5M465405AJ Die photograph of the Mitsubishi M5M465405AJ 64Mbit DRAM. Mag. 13x.

9 Mitsubishi M5M465405AJ PASSIVATION METAL 2 Mag. 16,800x SOG LOCAL OXIDE METAL 1 PRE-METAL GLASS M1 PLUG M1 PLUGS POLY 2 Mag. 10,000x POLY 1 POLY 2 POLY 4 POLY 2 POLY 1 GATE Mag. 51,000x N+ S/D N+ S/D SEM views illustrating general structures.

10 Mitsubishi M5M465405AJ POLY 1 POLY 2 Mag. 60,000x N+ S/D POLY 1 P+ S/D Mag. 66,000x GATE OXIDE M1 PLUG SIDEWALL SPACER SILICIDE POLY 1 Mag. 80,000x GATE OXIDE SEM views of typical transistors.

11 Mitsubishi M5M465405AJ POLY 3 PLATES Mag. 21,250x, 60 POLY 2 BIT LINES POLY 3 CAPACITOR PLATE REMAINING POLY 1 Mag. 44,000x, 60 STEM POLY 4 SHEET POLY 3 PLATE Mag. 32,750x POLY 1 SELECT GATES N+ S/D SEM views of the cell array.

12 Hitachi HM ATT6 TECHNOLOGY DESCRIPTION HITACHI HM ATT-6 64Mbit (x8) CMOS EDO DRAM Introduction Ref. report SCA These parts were packaged in 32-pin, plastic, thin small-outline packages (TSOP) with J-leads and using a lead-on-chip center bonded (LOCCB) leadframe design. They were fully functional devices organized in an 8M x 8 design, offer 60nsec access time, and operate from a 3.3V power source. They were date coded 9705 (week 5 of 1997). See tables for specific dimensions and materials identification and see figures for examples of physical structures. Important/Unique Features - Beveled die edges. - Tungsten metal 1. - Metal 3 redundancy fuses located over poly 1 fuse patterns. Quality Quality of the process implementation was not very good. The metal 2 and metal 1 aluminum thinned up to 100 percent at many vias. The thick tungsten barriers maintained continuity very adequately however. In the area of layer patterning, etch definition was good and control was adequate (some overetching was present at vias and contacts). Alignment and registration were also adequate rather than good. The most obvious misalignment was at bit contacts in the array. Technology These devices were manufactured by a recessed oxidation, twin-well, CMOS process on a P substrate (no epi). They employed three levels of metal, five levels of poly, and stacked crown capacitor over bit lines (COB) cells. 2-5

13 Hitachi HM ATT6 Passivation consisted of a layer of nitride over two layers of silicon-dioxide. It had not been planarized but did have a polyimide die coat. The three levels of metallization were defined by standard dry-etch techniques (no damascene). Metal 3 and metal 2 consisted of aluminum with titanium-nitride on titanium caps and thick tungsten barriers. Metal 1 was tungsten on a thick titaniumnitride and surrounded by a thin layer of titanium-nitride, on a substantial layer of titanium. Standard vias and contacts were used (no plugs). The via cuts penetrated through the titanium cap layer thus contact was from aluminum, through the tungsten barrier to the aluminum underneath. Intermetal dielectric consisted of two layers of silicon-dioxide (TEOS?) with a spin-onglass (SOG) between for planarization. The SOG was etched back. No CMP was employed. Planarization under metal 1 consisted of two layers of CVD glass (BPSG) that was reflowed prior to contact cuts. A nitride etch stop layer was present on the densified oxide under poly 4. Five levels of polysilicon were used. Polys 5 and 4 were used exclusively in the cell array to form the capacitor plates. Poly 3 (poly and tungsten silicide) formed the bit lines in the array. Poly 2 was strictly used for plugs or stems under the poly 4 capacitor plates. Poly 1 (poly and tungsten-silicide) formed all gates on the die and the word lines in the cell array. Sidewall spacers used on all gates were of oxide and left in place. Direct poly 3-to-N+, and poly 2-to-N+ diffusion (buried) contacts were present in the array only. In addition, poly 4 made direct contact to the poly 2 stems to contact select gate drains in the array. Normal implanted source/drain diffusions were used and not silicided. Besides the P- wells, two different depth N-wells were present. A deep N-well appeared to be used under the P-well in the array areas. No evidence of unusual gate oxides was found. Standard LOCOS isolation was employed and well implemented. As mentioned, unique metal 3 redundancy fuses were used. They were connected in parallel to and located directly over, identical poly 1 fuse patterns. Since some laser blown fuses were present it was easy to see that the poly structures under the M3 fuses were also severely damaged in the process, but not necessarily physically open. This seems to leave the possibility of having some remaining resistance between the two fuse terminals, in other words an incomplete open. Fuses were blown before the final two layers of passivation were deposited and thus no passivation cutouts remain and the structures are completely sealed. The first layer of passivation had apparently been cut out above the fuses prior to activation. 2-6

14 Hitachi HM ATT6 Memory Cell Structures Memory cells used a stacked crown NMOS DRAM cell design and reflects a radically new design for Hitachi. Poly 5 (sheet) was used for the common plate of the capacitors. Poly 4 formed the individual capacitor plates and made indirect contact to the drain (N+) diffusions of the select gates through the poly 2 stems. The capacitor dielectric was apparently an oxide-nitride layer. A nitride etch-stop layer under the poly 4 capacitor plate allowed backfilling the space under the crown by poly 5 thus surrounding the poly 4 plates to increase capacitance area. Poly 3 (tungsten polycide) formed the bit lines thus resulting in a capacitor over bit line (COB) design. The DRAM cell size was 1.26 microns2, which is the second largest 64M cell seen in Overall minimum feature size measured anywhere on these dice was the 0.2 micron poly 1 (word line) width. Minimum gate length was the 0.35 micron of the select gates. Packaging/Assembly As mentioned, these parts were packaged in 32-pin, plastic, thin small-outline packages (TSOPs) with a lead-on-chip, center bonded (LOCCB) leadframe design. The die was mounted to the bottom of the leadframe with a double sided Kapton type tape. Wirebond pads on the die had a pitch of 140 microns with 30 micron spacings. Pads were 110 microns wide with 100 micron windows. A small beveled edge was present all around the top edges of the die. This is similar to the Intel Pentium II microprocessor which is the only other device we ve seen this on. We presume it is an expensive (but effective?) method to reduce the effects of packaging stresses. A patterned (at bond pads) polyimide die coat was present to protect against alpha particle-induced leakage and packaging stresses. 2-7

15 Hitachi HM ATT6 Die photograph of the Hitachi HM ATT6 64Mbit DRAM. Mag. 12x.

16 Hitachi HM ATT6 DIE SURFACE BEVEL DIE EDGE SUBSTRATE Mag. 1300x DELINEATION ARTIFACT PASSIVATION 3 PASSIVATION 2 PASSIVATION 1 METAL 3 IMD METAL 2 SOG IMD 1 METAL 1 glass etch, Mag. 10,500x SEM section views of general structures.

17 Hitachi HM ATT6 INTACT BLOWN metal 3, Mag. 5500x METAL 3 BLOWN BLOWN Mag. 9000x SEM views of fuses. PASSIVATION POLY 1 INTACT BLOWN poly 1, Mag. 5500x

18 Hitachi HM ATT6 METAL 1 PRE-METAL DIELECTRIC POLY 1 GATE Mag. 24,500x P+ S/D METAL 2 METAL 1 POLY 1 GATE Mag. 22,500x N+ S/D SILICIDE SIDEWALL SPACER glass etch, Mag. 60,000x POLY 1 SEM views of typical gates.

19 POLY 5 METAL 3 POLY 4 METAL 2 POLY 5 POLY 4 Hitachi HM ATT6 POLY 1 Mag. 11,000x POLY 5 POLY 3 Mag. 38,000x POLY 4 POLY 1 POLY 2 STEM SEM views of DRAM cells. POLY 2 STEM Mag. 48,000x

20 Micron MT4LC16M4H9 TECHNOLOGY DESCRIPTION MICRON SEMICONDUCTOR MT4LC16M4H9 64Mbit (x4) CMOS EDO DRAM Introduction Ref. report SCA These parts were packaged in 32-pin plastic small-outline J-lead (SOJ) packages, using a lead-on-chip, center bonded (LOCCB) leadframe design. They were fully functional engineering samples organized in a 16M x 4 design. They provide 60nsec access time and operate from a 3.3V power source. Parts were date coded 9708 (week 8 of 1997). See tables for specific dimensions and material identification and see figures for examples of physical structures. Important/Unique Features - Aggressive metal interconnect design rules (0.7 micron contacted metal 1 pitch). - Tall dual tungsten on poly plugs. - No evidence of redundancy fuses. - Smallest cell size observed to date (0.8 microns 2 ). Quality Quality of process implementation was good even though metal 1 appeared overetched. In the area of layer patterning, etch definition was good and control was good except for the apparent overetch of metal 1 mentioned above. Alignment and registration were good. Technology These devices were manufactured by an apparent twin-well, recessed oxidation CMOS process on a P substrate (no epi). They employ two levels of metal, four levels of poly, a stacked, textured poly crown, capacitor under bit line (CUB) cell design. 2-8

21 Micron MT4LC16M4H9 Final passivation consisted of a thick layer of nitride, over a thick layer of silicondioxide, over a thin sacrificial layer of silicon-dioxide, over another thin layer of silicondioxide. A planarizing sputter backetch procedure was apparently used after the sacrificial oxide deposition for planarization purposes. It was also covered by a polyimide die coat. The two levels of metallization were defined by standard dry etch techniques (no damascene). Both consisted of aluminum with titanium-nitride caps and both showed evidence of a very thin titanium barrier/adhesion layer. As mentioned, metal design rules were quite aggressive. This is especially true for metal 1 since it is used for bit lines where is has a contacted pitch of 0.7 microns. It was overetched slightly and did not cover the tungsten plugs completely. Standard vias were used to connect metal 2 to metal 1 but tungsten plugs (unusually tall) were used between metal and silicon. Via cuts penetrated through the metal 1 cap to the aluminum thus establishing contact between metal 2 aluminum through the titanium barrier, to the aluminum 1 underneath. Some evidence was found of a very thin titanium lining under the plugs but not between the top of the tungsten and metal 1 aluminum (although it is probably there). It appears that the need for the use of the very tall plugs is the use of the capacitor under bit line cell design. A few instances were found of use of poly 2 plugs under the tungsten plugs in peripheral circuitry (this is universal in the array). Intermetal dielectric between metal 2 and metal 1 consisted of two layers of silicondioxide plus a partial (sacrificial) oxide between. It had been planarized by sputter backetching (after sacrificial oxide deposition) and chemical-mechanical planarization (CMP) prior to via contact patterning. No SOG was used in this process. The pre-metal dielectric consisted of at least two layers of reflow glass over a substantial layer of densified oxide (possibly an oxynitride). Both layers of reflow glass appeared to have been planarized by CMP. The memory capacitor structures exist between these two layers. Final planarization of this dielectric was done by CMP both before and after tungsten plug formation. No evidence was found of a nitride sealing layer. Four levels of polysilicon were used. Poly 4 was used for the common capacitor plate, while poly 3 (textured) formed the individual plates. Poly 2 was employed strictly for contact plugs under the tungsten plugs. This was done primarily in the array but also in a few places in peripheral circuit areas. Poly 1 consisted of poly and tungsten-silicide covered with a thin layer of poly. It was used for all gates on the die and word lines in the array. Sidewall spacers were formed by the densified oxide (oxynitride?) layer. This layer also appears to act as an etch stop during contact etch and for the etch in the first reflow glass that creates the cavities for the capacitor plates. Direct poly to diffusion contacts were only present between the poly 2 contact plugs and N+ source/drains. The implanted source/drains were not silicided. Although we were unable to get clear 2-9

22 Micron MT4LC16M4H9 delineation of the P-wells we believe they were present. N-wells appeared normal. No evidence of unusual gate oxides was found and a standard LOCOS isolation was used. No evidence of any redundancy fuses was found which is highly unusual and we assume they were present, possibly covered by the final passivation. Memory Cell Structure Memory cells consisted of a stacked, crown design employing textured poly 3 capacitor plates and a capacitor under bit line design. Poly 4 was in the form of a continuous sheet (with holes) to form the common plate of the capacitors. An oxidenitride capacitor dielectric was used. As mentioned, poly 2 formed both contact plugs connecting the poly 3 capacitor plates to the drains of the select gates, as well as bit contact plugs under the tungsten plugs. Implementation of these structures was very good. As previously stated the design resulted in the smallest cell size seen to date (0.8 microns 2 ). Overall minimum feature size measured anywhere on these dice was the 0.25 micron poly 1. Minimum gate lengths were 0.35 micron but it should be mentioned that we also found evidence of gates that were 0.15 micron wide (not long). Packaging/Assembly These dice were packaged in 32-pin plastic SOJ packages that employed an LOCCB leadframe design. The surface of the die was attached to the bottom of the leadframe with a double backed Kapton type tape. Standard thermosonic wirebonding was used. Pads were 120 microns wide with 100 micron windows and were spaced 60 microns apart. Both levels of metal were present at the bond pads connected with a full pad size via. A patterned polyimide die coat was used. 2-10

23 Micron MT4LC16M4H9 Die photograph of the Micron MT4LC16M4H9 64Mbit DRAM. Mag. 15x.

24 Micron MT4LC16M4H9 PASSIVATION 3 PASSIVATION 2 METAL 2 Mag. 12,000x PRE-METAL DIELECTRIC METAL 1 METAL 1 PLUG POLY 1 GATES N+ S/D Mag. 12,000x PLUGS METAL 1 Mag. 14,000x SEM views illustrating general device structures.

25 Micron MT4LC16M4H9 POLY 1 Mag. 52,000x P+ S/D GATE OXIDE VOID POLY 1 Mag. 52,000x N+ S/D GATE OXIDE TUNGSTEN PLUG DENSIFIED OXIDE SILICIDE glass etch, Mag. 52,000x POLY SEM views of typical gates.

26 Micron MT4LC16M4H9 CAPACITOR PLATES poly 3, Mag. 30,000x, 55 METAL 1 BIT LINE POLY 4 SHEET BIT LINE CONTACT Mag. 26,000x POLY 1 SELECT GATE POLY 2 CONTACT LINK METAL 1 BIT LINES POLY 4 SHEET CAPACITOR DIELECTRIC METAL 1 PLUG Mag. 26,000x N+ POLY 2 LOCOS SEM details of the array.

27 Toshiba TC AFT-50 TECHNOLOGY DESCRIPTION TOSHIBA TC AFT-50 64Mbit (x16) CMOS EDO DRAM Introduction Ref. report SCA These parts were packages in 50-pin, thin plastic (TSOP) packages using a lead-on-chip, center bond (LOCCB) technique. They were fully functional devices organized in a 4M x 16 design. They offer an access time of 50nsec and operate from a 3.3V power source. The date code was 9702 (week 2 of 1997). See tables for specific dimensions and material identification and see figures for examples of physical structures. Important/Unique Features - Three levels of metal of which metal 1 was a damascene patterned tungsten. - Deep, poly-filled trench capacitors. - Shallow trench isolation and CMP planarization. Quality Quality of the process implementation was good, although metal 3 thinned up to 95 percent at some vias. In the area of layer patterning, etch definition and control were both good. Alignment and registration were also good. Technology These devices were manufactured by a twin-well, shallow trench isolation, CMOS process on a P substrate with an N-epi. Three levels of metal interconnect were employed and they use a trench cell design. Final passivation consisted of a layer of silicon nitride over a silicon oxide. It was not planarized but did have a polyimide die coat. 2-11

28 Toshiba TC AFT-50 Metals 3 and 2 consisted of aluminum with titanium-nitride caps and barriers defined by standard dry-etch techniques (no damascene). Metal 1 was tungsten with a titaniumnitride barrier defined by a damascene method (grooves etched in the dielectric and then lined with titanium-nitride and filled with tungsten). Metal 3 used standard vias to connect to metal 2. Vias were etched down to only the surface of the titanium-nitride cap on metal 2 rather than to the aluminum. Since a very thin titanium adhesion layer also appeared to be present under metal 3 (and metal 2) the via contact thus occurs between titanium and titanium-nitride. Tungsten plugs were used for vertical interconnects between metals 2 and 1. Plugs under metal 2 were both lined and covered with a thin titanium-nitride. The plugs under metal 1 were apparently formed coincidentally with the metal 1 tungsten (dual damascene). Intermetal dielectric layers consisted of dual layers of oxide (TEOS?) that were planarized by CMP. Pre-metal dielectric under metal 1 consisted of a thick layer of silicon-dioxide (BPSG?) over densified oxide on top of the polycide. It was also planarized by CMP. No evidence of a sealing nitride layer was found. Three layers of polysilicon were used. Poly 1 was used to fill the trenches of the memory cells and thus formed one side of the cell capacitor. Poly 2 (tungsten polycide) was used throughout for transistor gates and for redundancy fuses. Poly 3 was a thick, doped layer that was used exclusively to form small connecting links (straps) between the drains of the select gates and the poly 1 capacitor plates in the cell array. No direct poly to diffusion (buried) contacts were used except in the array (see below). Sidewall spacers were formed by a layer of densified oxide which also provided protection against shorting the gates to the extremely closely spaced tungsten plugs contacting gate source diffusions. Diffusions were not silicided. No evidence of unusual gate oxides was found. Isolation was provided by oxide filled shallow trenches. Implanted source/drain diffusions were used and were not silicided (i.e., not a salicide process) which is surprising. As mentioned, an N-epi was used on a P substrate, and large P-wells were used in the cell array. Polycide 2 redundancy fuses were present. Passivation and dielectrics down to the premetal were cleared over the fuse locations. Some laser-activated fuses were present. Memory Cell Structures As mentioned, these parts use a trench DRAM cell design very similar to that used by IBM (the original designer) and Siemens, but some differences between the structures 2-12

29 Toshiba TC AFT-50 on these Toshiba parts and the previously analyzed Siemens parts were clearly present. Both use P-channel gates in the array, but Toshiba also uses an N-epi and a P type substrate around the trench cells as the common plate. Also, instead of the very thin poly 3 straps used in the Siemens devices to link select gate drains to the trench poly, Toshiba uses much more substantial looking plugs of poly 3 to do this. Trench poly measured 0.3 x 1 micron at the surface and approximately 0.1 x 0.9 micron at the bottom. Trenches were 7 microns deep. Cell size was 1.1 micron 2. Overall minimum feature size measured anywhere of these dice were the 0.3 micron trenches and 0.35 micron poly 2. Minimum gate length was 0.4 micron. Packaging/Assembly As mentioned, these parts were packaged in 50-pin plastic TSOP packages using a leadon-chip center bond (LOCCB) technique and gull wing leads. In this design the wirebond connections are made parallel to the long dimension of the die. Wirebond pads on the die had a pitch of 210 microns with 100 micron spacing. Pad were 110 microns wide with 100 micron windows. A thin patterned (at bond pads) polyimide die coat was present and a double backed Kapton type tape was used to attach the die to the underside of the leadframe. 2-13

30 Toshiba TC AFT-50 Die photograph of the Toshiba TC AFT-50 64Mbit DRAM. Mag. 13x.

31 Toshiba TC AFT-50 PASSIVATION 2 PASSIVATION 1 VOID METAL 3 Mag. 13,000x METAL 2 METAL 1 N+ M1 PLUG TRENCH OXIDE POLY 2 PASSIVATION 2 PASSIVATION 1 METAL 3 METAL 2 METAL 1 IMD 2 M2 PLUG Mag. 13,000x M1 PLUG POLY 2 GATES N+ S/D POLY METAL 1 Mag. 20,000x SEM views illustrating general device structures.

32 Toshiba TC AFT-50 POLY 2 WORD LINE BIT Q POLY 3 LINK poly 2 and 3 Q BIT C POLY 3 LINK CONNECTION TRENCH CAPACITORS FIELD OXIDE (SHALLOW TRENCH) delayered to substrate Detailed topological SEM views of DRAM cells. Mag. 30,000x, 0.

33 Toshiba TC AFT-50 METAL 3 METAL 1 BIT LINES METAL 2 Mag. 6500x TRENCH CAPACITORS POLY 3 LINKS METAL 1 Mag. 20,000x POLY 1 FILLED TRENCH METAL 1 BIT LINE POLY 3 Mag. 20,000x POLY 2 SELECT GATE TRENCH OXIDE SEM section views of DRAM cells.

34 Mosel Vitelic V53C181608K60 TECHNOLOGY DESCRIPTION MOSEL-VITELIC V53C181608K60 16Mbit (x16) CMOS EDO DRAM Introduction Ref. report SCA These parts were packaged in 42-pin, plastic, small-outline packages with J-leads (SOJ). They were fully functional production devices organized in a 1M x 16 design, access time of 60nsec, and operate from a 5V power source. The date code was 9605 (week 5 of 1996). See tables for specific dimensions and materials identification and see figures for examples of physical structures. Important/Unique Features - IBM-Siemens mask set. - Trench cells. - Shallow trench isolation, salicide process, CMP planarization. Quality Quality of the process implementation was good. No problem areas were identified. In the area of layer patterning, etch definition and control were both good. Alignment and registration were also good. Technology These devices were manufactured by a twin-well, shallow trench isolation, 2 metal, 3 poly CMOS process, on a P substrate with a P-epi. Passivation consisted of a layer of nitride over a layer of silicon-dioxide that was not planarized but did have a polyimide die coat. 2-14

35 Mosel Vitelic V53C181608K60 The devices incorporated two levels of metal defined by standard dry-etch techniques (no damascene). Both consisted of aluminum with a titanium-nitride cap and a titanium barrier. Standard vias were used between metal 2 and metal 1, but tall tungsten plugs were employed for metal 1 contacts to silicon. The plugs were lined with titaniumnitride underneath only. Via cuts penetrated the cap of metal 1 thus establishing contact from aluminum, through the titanium barrier to the aluminum 1 beneath. Intermetal dielectric consisted of three layers of silicon-dioxide (TEOS?) including a sacrificial layer (layer 2) for the sputter backetch planarization used. No SOG was used. Pre-metal dielectric appeared to be a thick layer of borophosphosilicate glass (BPSG) over a thin sealing layer of nitride. It was planarized by CMP both before contact patterning and after plug formation. Three layers of polysilicon were used. Poly 3 and 1 were used exclusively in the array. Poly 2 employed a tungsten silicide, formed all gates on the die, and the word lines in the array. Sidewall spacers used on all gates were of oxide and were left in place. Direct poly to diffusion (buried) contacts were present between poly 3 and P+ (select gate drains) in the array and between the poly 3 and the poly 1 trenches in the array. Salicided (titanium) source/drain diffusion implants were used and a P-epi plus twinwells appeared to be employed on the P substrate. The array used P-channel devices. No evidence of unusual gate oxides or other dielectrics was found. Shallow trench isolation was employed and well implemented, although notches were present at the upper corners under gate poly. Poly 2 redundancy fuses were present. Only passivation was cleared over the fuse locations. Memory Cell Structures Memory cells consisted of a trench capacitor DRAM cell design with the capacitors formed between the trench poly and P-epi. Poly 2 formed the bit lines. Poly 3 links (straps) were used to connect select gate drains to the trench poly. Poly 1 formed the individual capacitor plates of the storage capacitors (trenches). The cells used P-channel gates in an N-well. Trenches had a thick oxide collar that extended below the N-well, and the surface of the trench poly was below the substrate surface and covered by a substantial oxide layer. The resulting cell size was 2.75 microns 2. Overall minimum feature size measured anywhere on these dice was the 0.4 micron poly 2 and metal 1. Minimum gate lengths were 0.5 micron (N-channel) and 0.65 micron (Pchannel). 2-15

36 Mosel Vitelic V53C181608K60 Packaging/Assembly As mentioned, these parts were packaged in 42-pin, plastic, small-outline packages with J-leads (SOJs). An LOCCB design was employed. The die was mounted to the leadframe by a double sided Kapton type tape. Wirebond pads on the die had a pitch of 170 microns with 60 micron spacing. Pads were 110 microns wide with 100 micron windows. Standard thermosonic wirebonding was used. A patterned (to clear bond pads) polyimide die coat was present. 2-16

37 Mosel Vitelic V53C181608K60 Die photograph of the Mosel Vitelic V53C181608K60 16Mbit DRAM. Mag. 15x.

38 Mosel Vitelic V53C181608K60 METAL 1 POLY 2 GATE W PLUG P-channel, Mag. 26,000x P+ S/D OXIDE SIDEWALL SPACER NITRIDE POLY 2 GATE N-channel, Mag. 52,000x N+ S/D GATE OXIDE NITRIDE SIDEWALL SPACER OXIDE W SILICIDE glass-etch, Mag. 52,000x POLY 2 Ti SILICIDE SEM views of typical gates.

39 Mosel Vitelic V53C181608K60 PASSIVATION 1 METAL 2 ILD METAL 1 POLY 2 GATE TRENCH OXIDE W PLUG N+ S/D SEM view illustrating general structure. Mag. 13,000x. POLY 2 WORD LINES BIT CONTACT delayered to poly POLY 1 TRENCH CAPACITOR BIT CONTACT POLY 3 LINK word lines removed Topological SEM views of the DRAM cell array. Mag. 13,000x, 0.

40 Mosel Vitelic V53C181608K60 BIT LINE CONTACT P+ Mag. 6500x OXIDE COLLAR POLY 1 TRENCH CAPACITORS DELINEATION ARTIFACT W PLUG POLY 2 SELECT GATE Mag. 26,000x P+ S/D P+ S/D METAL 1 BIT LINES POLY 2 WORD LINE Mag. 6500x POLY 1 TRENCH CAPACITORS SEM views of the DRAM cell array.