EE 330 Lecture 9. IC Fabrication Technology Part 2

Transcription

1 EE 330 Lecture 9 IC Fabrication Technology Part 2

2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this 2m crystal provide? In solving this problem you may neglect any wire vibration or abrasive particles used during cutting that would increase the width of the kerf.

3 And the number is

4 And the number is

5 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this 2m crystal provide? In solving this problem you may neglect any wire vibration or abrasive particles used during cutting that would increase the width of the kerf. Solution: n w Pull height 2m t t 220um 350um CUT wafer n w 2m 220um 350um 3509

6 Review from Last Time Crystal Preparation Source: WEB

7 Review from Last Time Masking Use masks or reticles to define features on a wafer Masks same size as wafer Reticles used for projection Reticle much smaller (but often termed mask) Reticles often of quartz with chrome Quality of reticle throughout life of use is critical Single IC may require 20 or more reticles Cost of mask set now exceeds $1million for state of the art processes Average usage 500 to 1500 times Mask costs exceeding 50% of total fabrication costs in sub 100nm processes Serve same purpose as a negative (or positive) in a photographic process

8 Review from Last Time Photolithographic Process Photoresist Viscous Liquid Uniform Application Critical (spinner) Baked to harden Approx 1u thick Non-Selective Types Negative unexposed material removed when developed Positive-exposed material removed when developed Thickness about 450nm in 90nm process (ITRS 2007 Litho) Exposure Projection through reticle with stepper Alignment is critical!! E-Bean Exposures Eliminate need fro reticle Capacity very small

9 Review from Last Time Deposition Application of something to the surface of the silicon wafer or substrate Layers 15A to 20u thick Methods Physical Vapor Deposition (nonselective) Evaporation/Condensation Sputtering (better host integrity) Chemical Vapor Deposition (nonselective) Reaction of 2 or more gases with solid precipitate Reduction by heating creates solid precipitate (pyrolytic) Screening (selective) For thick films Low Tech, not widely used today

10 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

11 Implantation Application of impurities into the surface of the silicon wafer or substrate - Individual atoms are first ionized (so they can be accelerated) - Impinge on the surface and burry themselves into the upper layers - Often very shallow but with high enough energy can go modestly deep - Causes damage to target on impact - Annealing heals most of the damage - Very precise control of impurity numbers is possible - Very high energy required - High-end implanters considered key technology for national security

12 Ion Implantation Process From

13 Ion Implantation Process From

14 Ion Implanter From

15 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

16 Etching Selective Removal of Unwanted Materials Wet Etch Inexpensive but under-cutting a problem Dry Etch Often termed ion etch or plasma etch

17 Etching SiO 2 Photoresist p - Silicon Desired Physical Features Note: Vertical Dimensions Generally Orders of Magnitude Smaller Than Lateral Dimensions so Different Vertical and Lateral Scales Will be Used In This Discussion

18 Etching Dry etch (anisotropic) SiO 2 Photoresist p - Silicon Desired Physical Features Dry Etch can provide very well-defined and nearly vertical edges (relative to photoresist paterning)

19 Etching (limited by photolitghographic process) SiO 2 Dry etch (anisotropic) Photoresist p - Silicon Dry etch (anisotropic) Consider neg photoresist Over Exposed Correctly Developed Over Developed Under Developed Under Exposed Correctly Developed Over Developed Under Developed

20 Lateral Relative to Vertical Dimensions Source Drain Gate Bulk n-channel MOSFET SiO 2 Photoresist p - Silicon Still Not to Scale For Example, the wafer thickness is around 250u and the gate oxide is around 50A (5E-3u) and diffusion depths are around λ/5

21 Etching Undercutting (wet etch) Photoresist SiO 2 p - Silicon Isotropic Feature Degradation Desired Edges of SiO 2 from Mask Edge Movement Due to Over Etch, Over Exposure, or Over-Development

22 Etching Undercutting (wet etch) SiO 2 p - Silicon Desired Edges of SiO 2 from Mask SiO 2 after photoresist removal Edge Movement Due to Over Etch, Over Exposure, or Over-Development

23 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Ion Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

24 Diffusion Controlled Migration of Impurities Time and Temperature Dependent Both vertical and lateral diffusion occurs Crystal orientation affects diffusion rates in lateral and vertical dimensions Materials Dependent Subsequent Movement Electrical Properties Highly Dependent upon Number and Distribution of Impurities Diffusion at 800 o C to 1200 o C Source of Impurities Deposition Ion Implantation Only a few A o deep More accurate control of doping levels Fractures silicon crystaline structure during implant Annealing occurs during diffusion Types of Impurities n-type Arsenic, Antimony, Phosphorous p-type Gallium, Aluminum, Boron

25 Diffusion Source of Impurities Deposited on Silicon Surface p - Silicon Before Diffusion p - Silicon After Diffusion

26 Diffusion Source of Impurities Implanted in Silicon Surface p - Silicon Before Diffusion p - Silicon After Diffusion

27 Diffusion Implant p - Silicon p- Silicon Lateral Diffusion Before Diffusion p - Silicon p- Silicon After Diffusion

28 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Ion Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

29 Oxidation SiO 2 is widely used as an insulator Excellent insulator properties Used for gate dielectric Gate oxide layers very thin Used to separate devices by raising threshold voltage termed field oxide field oxide layers very thick Methods of Oxidation Thermal Growth (LOCOS) Consumes host silicon x units of SiO 2 consumes.47x units of Si Undercutting of photoresist Compromises planar surface for thick layers Excellent quality Chemical Vapor Deposition Needed to put SiO 2 on materials other than Si

30 Oxidation Photoresist SiO 2 X 0.47 X p - Silicon Patterned Edges Thermally Grown SiO 2 - desired growth

31 Oxidation Bird s Beaking Photoresist SiO 2 p - Silicon Patterned Edges Thermally Grown SiO 2 - actual growth

32 Nonplanar Surface Oxidation p - Silicon Patterned Edges Thermally Grown SiO 2 - actual growth

33 Silicon Nitride Oxidation Photoresist Pad Oxide p - Silicon Shallow Trench Isolation (STI)

34 Oxidation Silicon Nitride Etched Shallow Trench Pad Oxide p - Silicon Shallow Trench Isolation (STI)

35 Silicon Nitride Oxidation CVD SiO 2 Pad Oxide p - Silicon Shallow Trench Isolation (STI)

36 Oxidation Planarity Improved Planarization Target p - Silicon Shallow Trench Isolation (STI)

37 Oxidation After Planarization CVD SiO 2 p - Silicon Shallow Trench Isolation (STI)

38 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Ion Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

39 Epitaxy Single Crystaline Extension of Substrate Crystal Commonly used in bipolar processes CVD techniques Impurities often added during growth Grows slowly to allow alignmnt with substrate

40 Epitaxy Epitaxial Layer p - Silicon epi can be uniformly doped or graded Original Silicon Surface Question: Why can t a diffusion be used to create the same effect as an epi layer?

41 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

42 Polysilicon Elemental contents identical to that of single crystaline silicon Electrical properties much different If doped heavily makes good conductor If doped moderately makes good resistor Widely used for gates of MOS devices Widely used to form resistors Grows fast over non-crystaline surface Silicide often used in regions where resistance must be small Refractory metal used to form silicide Designer must indicate where silicide is applied (or blocked)

43 Polysilicon Polysilicon Single-Crystaline Silicon

44 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

45 Contacts, Interconnect and Metalization Contacts usually of a fixed size All etches reach bottom at about the same time Multiple contacts widely used Contacts not allowed to Poly on thin oxide in most processes Dog-bone often needed for minimum-length devices

46 Contacts A A B B Acceptable Contact Unacceptable Contact Vulnerable to pin holes (usually all contacts are same size)

47 Contacts B B Acceptable Contact

48 Contacts 2λ 2λ 1.5λ 1.5λ 2λ Dog Bone Contact Design Rule Violation

49 Contacts Common Circuit Connection Standard Interconnection Buried Contact Can save area but not allowed in many processes

50 Metalization Aluminum widely used for interconnect Copper finding some applications Must not exceed maximum current density around 1ma/u Ohmic Drop must be managed Parasitic Capacitances must be managed Interconnects from high to low level metals require connections to each level of metal Stacked vias permissible in some processes

51 Multiple Level Interconnects 3-rd level metal connection to n-active without stacked vias

52 Multiple Level Interconnects 3-rd level metal connection to n-active with stacked vias

53 Interconnects Metal is preferred interconnect Because conductivity is high Parasitic capacitances and resistances of concern in all interconnects Polysilicon used for short interconnects Silicided to reduce resistance Unsilicided when used as resistors Diffusion used for short interconnects Parasitic capacitances are high