High temperature operation of SiC transistors

Transcription

1 1 / 32 High temperature operation of SiC transistors ATW on Thermal Management, Los Gatos Cyril BUTTAY 1, Marwan ALI 2, Oriol AVINO 1,2, Hervé MOREL 1, Bruno ALLARD 1 1 Laboratoire Ampère, Lyon, France 2 Labinal Power Systems, SAFRAN Group, France 23/9/15

2 Outline 2 / 32 Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

3 Outline 3 / 32 Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

4 Automotive 4 / 32 Vehicle Location Max Temp ( C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649 Most data: Kassakian, J. G. et al. The Future of Electronics in Automobiles, ISPSD, 2001, p Low-cost, high-volume applications; Moving to higher voltages (12V->300V for hybrids) Little cooling headroom with silicon devices (T J =150 to 175 C)

5 Automotive 4 / 32 Vehicle Location Max Temp ( C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649 Most data: Kassakian, J. G. et al. The Future of Electronics in Automobiles, ISPSD, 2001, p Low-cost, high-volume applications; Moving to higher voltages (12V->300V for hybrids) Little cooling headroom with silicon devices (T J =150 to 175 C)

6 Automotive 4 / 32 Vehicle Location Max Temp ( C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649 Most data: Kassakian, J. G. et al. The Future of Electronics in Automobiles, ISPSD, 2001, p Low-cost, high-volume applications; Moving to higher voltages (12V->300V for hybrids) Little cooling headroom with silicon devices (T J =150 to 175 C) dedicated cooling circuit for power electronic systems

7 Aircraft 5 / 32 The trend: Hydraulic, Pneumatic and Electric networks co-exist in current systems More-electric aircraft should reduce complexity objective: 1 MW on-board electrical power From mild to very harsh: Some system are located in the cabin Jet engine actuator will face -55 C to 225 C cycling Many systems are located in non-pressurised areas Long system life: around 30 years Reliability is the main concern

8 Aircraft 5 / 32 The trend: Hydraulic, Pneumatic and Electric networks co-exist in current systems More-electric aircraft should reduce complexity objective: 1 MW on-board electrical power The environment: From mild to very harsh: Some system are located in the cabin Jet engine actuator will face -55 C to 225 C cycling Many systems are located in non-pressurised areas Long system life: around 30 years Reliability is the main concern

9 Aircraft 5 / 32 The trend: Hydraulic, Pneumatic and Electric networks co-exist in current systems More-electric aircraft should reduce complexity objective: 1 MW on-board electrical power The environment: From mild to very harsh: Some system are located in the cabin Jet engine actuator will face -55 C to 225 C cycling Many systems are located in non-pressurised areas Long system life: around 30 years Reliability is the main concern

10 Aircraft 5 / 32 The trend: Hydraulic, Pneumatic and Electric networks co-exist in current systems More-electric aircraft should reduce complexity objective: 1 MW on-board electrical power The environment: From mild to very harsh: Some system are located in the cabin Jet engine actuator will face -55 C to 225 C cycling Many systems are located in non-pressurised areas Long system life: around 30 years Reliability is the main concern

11 Aircraft 5 / 32 The trend: Hydraulic, Pneumatic and Electric networks co-exist in current systems More-electric aircraft should reduce complexity objective: 1 MW on-board electrical power The environment: From mild to very harsh: Some system are located in the cabin Jet engine actuator will face -55 C to 225 C cycling Many systems are located in non-pressurised areas Long system life: around 30 years Reliability is the main concern

12 6 / 32 Space Exploration NASA missions to Venus and Jupiter Venus surface temperature : up to 480 C Pressure a few kilometres inside Jupiter: 100 bars, at 400 C Strong thermal cycling, as temperature can drop to 140K at night; Other awful conditions: winds, corrosive gases...

13 7 / 32 Deep oil/gas extraction Continuous operation, relatively low cycling Deep drilling: high ambient temperature (up to 225 C) Expected lifetime: 5 years Main requirement: sensors and datalogging Example of new applications: downhole gas compressor

14 Maximum operating temperature 8 / 32 Junction temperature 3000 C 2500 C 2000 C 1500 C 1000 C Silicon 3C SiC 6H SiC 4H SiC 2H GaN Diamond 500 C 0 C 10 V 100 V 1 kv 10 kv 100 kv 1 MV Breakdown voltage Silicon operating temp is intrisically limited at high voltages V devices rated at <200 C junction temperature

15 Outline 9 / 32 Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

16 Test configuration I High temperature test system I I I I I Silver-sintered interconnects Ceramic substrate (DBC) Copper-kapton leadframe DUT: 490 mω SiC JFET from SiCED characterization: I I Tektronix 371A curve tracer Thermonics T2500-E conditionner 10 / 32

17 Test configuration I High temperature test system I I I I I Silver-sintered interconnects Ceramic substrate (DBC) Copper-kapton leadframe DUT: 490 mω SiC JFET from SiCED characterization: I I Tektronix 371A curve tracer Thermonics T2500-E conditionner 10 / 32

18 Test configuration I High temperature test system I I I I I Silver-sintered interconnects Ceramic substrate (DBC) Copper-kapton leadframe DUT: 490 mω SiC JFET from SiCED characterization: I I Source: Thermonics T-2500E Datasheet Tektronix 371A curve tracer Thermonics T2500-E conditionner 10 / 32

19 Static Characterization of 490 mω JFET 11 / 32 Forward current [A] Buttay et Al. Thermal Stability of Silicon Carbide Power JFETs IEEE transactions on Electron Devices, 2013, 60, C -10 C 30 C 70 C 110 C 150 C 190 C 230 C 270 C 300 C Forward voltage [V] V GS = 0 V, i.e. device fully-on

20 Power dissipation as a function of the junction temp. 12 / 32 Dissipated power [W] A 4.0 A 6.0 A 8.0 A 10.0 A Junction temperature [C]

21 13 / 32 Thermal Run-away mechanism Principle The device characteristic Its associated cooling system In region A, the device dissipates more than the cooling system can extract In region B, the device dissipates less than the cooling system can extract Two equilibrium points: one stable and one unstable Above the unstable point, run-away occurs

22 13 / 32 Thermal Run-away mechanism Principle The device characteristic Its associated cooling system In region A, the device dissipates more than the cooling system can extract In region B, the device dissipates less than the cooling system can extract Two equilibrium points: one stable and one unstable Above the unstable point, run-away occurs

23 13 / 32 Thermal Run-away mechanism Principle The device characteristic Its associated cooling system In region A, the device dissipates more than the cooling system can extract In region B, the device dissipates less than the cooling system can extract Two equilibrium points: one stable and one unstable Above the unstable point, run-away occurs

24 13 / 32 Thermal Run-away mechanism Principle The device characteristic Its associated cooling system In region A, the device dissipates more than the cooling system can extract In region B, the device dissipates less than the cooling system can extract Two equilibrium points: one stable and one unstable Above the unstable point, run-away occurs

25 13 / 32 Thermal Run-away mechanism Principle The device characteristic Its associated cooling system In region A, the device dissipates more than the cooling system can extract In region B, the device dissipates less than the cooling system can extract Two equilibrium points: one stable and one unstable Above the unstable point, run-away occurs

26 Thermal Run-away mechanism examples 14 / 32 Always stable

27 Thermal Run-away mechanism examples 14 / 32 Always stable Always unstable

28 Thermal Run-away mechanism examples 14 / 32 Always stable Always unstable Becomming unstable with ambient temperature rise

29 Power dissipation as a function of the junction temp. 15 / 32 Dissipated power [W] A 4.0 A 6.0 A 8.0 A 10.0 A Junction temperature [C]

30 Power dissipation as a function of the junction temp. 15 / 32 Dissipated power [W] A 4.0 A 6.0 A 8.0 A 10.0 A 1K/W 2K/W 4.5K/W Junction temperature [C]

31 High Temperature Thermal Management 16 / 32 Buttay et al. Thermal Stability of Silicon Carbide Power JFETs, IEEE Trans on Electron Devices, power [W] current changed from 3.65 to 3.7 A Run-away SiC JFET: 490 mω, 1200 V R ThJA = 4.5 K /W 135 C ambient On-state losses time [s] High temperature capability reduced cooling needs! SiC JFETs must be attached to a low-r Th cooling system.

32 Conclusions on high-temp. behaviour of SiC JFETs 17 / 32 Falahi et Al. High temperature, Smart Power Module for aircraft actuators, HiTEN C -10 C 27 C 70 C 107 C SiC JFETs can operate at > 200 C R DSon dependent on temperature sensitive to thermal run-away Require efficient thermal management low thermal resistance (1-2 K/W) low or high ambient temperature (> 200 C possible) V out [V] Drain current [A] C 196 C 234 C 270 C Drain-to-Source voltage [V] C time [µs] time [µs]

33 Conclusions on high-temp. behaviour of SiC JFETs 17 / 32 Falahi et Al. High temperature, Smart Power Module for aircraft actuators, HiTEN C -10 C 27 C 70 C 107 C SiC JFETs can operate at > 200 C R DSon dependent on temperature sensitive to thermal run-away Require efficient thermal management low thermal resistance (1-2 K/W) low or high ambient temperature (> 200 C possible) V out [V] Drain current [A] C 196 C 234 C 270 C Drain-to-Source voltage [V] C time [µs] time [µs]

34 Conclusions on high-temp. behaviour of SiC JFETs 17 / 32 Falahi et Al. High temperature, Smart Power Module for aircraft actuators, HiTEN C -10 C 27 C 70 C 107 C SiC JFETs can operate at > 200 C R DSon dependent on temperature sensitive to thermal run-away Require efficient thermal management low thermal resistance (1-2 K/W) low or high ambient temperature (> 200 C possible) V out [V] Drain current [A] C 196 C 234 C 270 C Drain-to-Source voltage [V] C time [µs] time [µs]

35 Conclusions on high-temp. behaviour of SiC JFETs 17 / 32 Falahi et Al. High temperature, Smart Power Module for aircraft actuators, HiTEN C -10 C 27 C 70 C 107 C SiC JFETs can operate at > 200 C R DSon dependent on temperature sensitive to thermal run-away Require efficient thermal management low thermal resistance (1-2 K/W) low or high ambient temperature (> 200 C possible) V out [V] Drain current [A] C 196 C 234 C 270 C Drain-to-Source voltage [V] C time [µs] time [µs]

36 Outline 18 / 32 Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

37 19 / 32 Double Side Cooling Standard packaging offers cooling through one side of the die only 3-D or Sandwich package offers thermal management on both sides Requires suitable topside metal on the die Requires special features for topside contact

38 19 / 32 Double Side Cooling Standard packaging offers cooling through one side of the die only 3-D or Sandwich package offers thermal management on both sides Requires suitable topside metal on the die Requires special features for topside contact

39 20 / 32 The proposed 3-D Structure V bus J H OUT J L GND Two ceramic substrates, in sandwich configuration Two SiC JFET dies (SiCED) assembled using silver sintering 25.4 mm 12.7 mm (1 in 0.5 in)

40 Ceramic Substrates 21 / 32 Copper 0.15 mm Source 0,15 mm Alumina 0.16 mm Gate Source 0.2 mm SiC JFET 0.3 mm Drain 0,3 mm Scale drawing for mm 2 die Si 3 N 4 identified previously for high temperature For development: use of alumina Etching accuracy exceeds standard design rules Double-step copper etching for die contact Custom etching technique

41 Bonding Material: Silver Sintering Silver Paste Based on micro-scale silver particles (Heraeus LTS-117O2P2) Low temperature (240 C) sintering Göbl, C. et al Low temperature sinter technology Die attachment for automotive power electronic applications proc of APE, 2006 Low pressure (2 MPa) process No liquid phase involved: No movement of the die No bridging across terminals No height compensation thanks to wetting 22 / 32

42 23 / 32 Preparation of the Substrates plain DBC board Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

43 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

44 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

45 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

46 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

47 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

48 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 4a - Photosentive film laminating 3b - Exposure and Developpment Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

49 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 4b - Exposure and Development 4a - Photosentive film laminating 3b - Exposure and Developpment Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

50 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 5 - Etching 4b - Exposure and Development 4a - Photosentive film laminating 3b - Exposure and Developpment Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

51 23 / 32 Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 6 - Singulating 5 - Etching 4b - Exposure and Development 4a - Photosentive film laminating 3b - Exposure and Developpment Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

52 23 / 32 Preparation of the Substrates Final patterns within 50 µm of desired size Two designs, for mm 2 and 4 4 mm 2 dies Total copper thickness 300 µm, 150 µm per step

53 24 / 32 Preparation of the Dies Standard aluminium topside finish not compatible with silver sintering Ti/Ag PVD on contact areas Need for a masking solution jig with locating pockets. Mask Die PVD

54 Preparation of the Dies Standard aluminium topside finish not compatible with silver sintering Ti/Ag PVD on contact areas Need for a masking solution jig with locating pockets. Mask Die PVD Before PVD 24 / 32

55 Preparation of the Dies Standard aluminium topside finish not compatible with silver sintering Ti/Ag PVD on contact areas Need for a masking solution jig with locating pockets. Mask Die PVD Before PVD After Ti/Ag PVD 24 / 32

56 25 / 32 Assembly Screen printing Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

57 25 / 32 Assembly Screen printing 2- Mounting in alignment jig Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

58 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

59 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

60 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of diealignment jig Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

61 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of diealignment jig 6 - Screen printing on "drain" substrate Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

62 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of diealignment jig 7 - Mounting in alignment jig 6 - Screen printing on "drain" substrate Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

63 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of diealignment jig 8 - Second sintering step 7 - Mounting in alignment jig 6 - Screen printing on "drain" substrate Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

64 25 / 32 Assembly Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of diealignment jig Result 8 - Second sintering step 7 - Mounting in alignment jig 6 - Screen printing on "drain" substrate Ceramic laser-cut jigs for precise alignment of dies and substrate Two sintering steps using the same temperature profile

65 Some results Size: mm 2 26 / 32

66 Some results 26 / 32

67 26 / 32 Some results V out [V] time [µs] time [µs] 300 Ω Resistive load, 0.5 A current (no cooling system used) oscillations dues to external layout

68 Outline 27 / 32 Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

69 Conclusion 28 / 32 SiC JFET able to operate continuously at high temperature(> 200 C) Must be provided with efficient thermal management (R Th =1 2 K/W) Proposition: introduce dual-side cooling 3D structure using only high-temperature-rated materials Should be able to operate continuously at 300 C, including passivation (parylene HT or F) Proposed etching technique offers satisfying resolution Silver sintering used for the interconnects, reliability to be investigated Package for demonstration of technology, no cooling attempted yet!

70 Conclusion 28 / 32 SiC JFET able to operate continuously at high temperature(> 200 C) Must be provided with efficient thermal management (R Th =1 2 K/W) Proposition: introduce dual-side cooling 3D structure using only high-temperature-rated materials Should be able to operate continuously at 300 C, including passivation (parylene HT or F) Proposed etching technique offers satisfying resolution Silver sintering used for the interconnects, reliability to be investigated Package for demonstration of technology, no cooling attempted yet!

71 Conclusion 28 / 32 SiC JFET able to operate continuously at high temperature(> 200 C) Must be provided with efficient thermal management (R Th =1 2 K/W) Proposition: introduce dual-side cooling 3D structure using only high-temperature-rated materials Should be able to operate continuously at 300 C, including passivation (parylene HT or F) Proposed etching technique offers satisfying resolution Silver sintering used for the interconnects, reliability to be investigated Package for demonstration of technology, no cooling attempted yet!

72 Conclusion 28 / 32 SiC JFET able to operate continuously at high temperature(> 200 C) Must be provided with efficient thermal management (R Th =1 2 K/W) Proposition: introduce dual-side cooling 3D structure using only high-temperature-rated materials Should be able to operate continuously at 300 C, including passivation (parylene HT or F) Proposed etching technique offers satisfying resolution Silver sintering used for the interconnects, reliability to be investigated Package for demonstration of technology, no cooling attempted yet!

73 Conclusion 28 / 32 SiC JFET able to operate continuously at high temperature(> 200 C) Must be provided with efficient thermal management (R Th =1 2 K/W) Proposition: introduce dual-side cooling 3D structure using only high-temperature-rated materials Should be able to operate continuously at 300 C, including passivation (parylene HT or F) Proposed etching technique offers satisfying resolution Silver sintering used for the interconnects, reliability to be investigated Package for demonstration of technology, no cooling attempted yet!

74 29 / 32 This work was funded by Euripides-Catrenes under the grant name THOR and FRAE under the grant name ETHAER. cyril.buttay@insa-lyon.fr

75 Credits 30 / 32 picture of the Airbus A350: airbus picture of the thrust reverser: Hispano-Suiza picture of the Toyota Prius: Picture by Pawel Golsztajn, CC-SA, available on Wikimedia Commons http: //commons.wikimedia.org/wiki/file:toyota_prius.2.jpg downhole gas compressor: http: // picture of Jupiter: NASA MOSFET wafers from Mitsubishi /1/siliconcarbidewafers

76 Static and Dynamic Characterization of 60 mω JFET 31 / 32 Drain current [A] Falahi et Al. High temperature, Smart Power Module for aircraft actuators, HiTEN C -10 C 27 C 70 C 107 C 160 C 196 C 234 C 270 C V out [V] C Drain-to-Source voltage [V] time [µs] time [µs] Previous results show that SiC JFETs are attractive for > 200 C operation: rated at 1200 V (or more), several Amps Voltage-controlled devices No reliability issue related to gate oxide degradation

77 Properties of some semiconductors Classical wide-bandgap Si GaAs 3C- SiC 6H- SiC 4H- SiC GaN Bandgap Energy E g (ev) 1,12 1,4 2,3 2,9 3,2 3,39 5,6 Diamond Elec. mobility µ n (cm 2.V 1.s 1 ) Hole mobility µ p (cm 2.V 1.s 1 ) Critical elec. field E C (V.cm 1 ) , Saturation velocity v sat (cm.s 1 ) , Termal cond. λ (W.cm 1.K 1 ) 1,3 0, , / 32