HT-FED MEASURED PERFORMANCE OF A MICRO THERMOELECTRIC COOLER

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1 Proceedings of HT-FED ASME Heat Transfer/Fluids Engineering Summer Conference Charlotte, North Carolina, USA, July 11-15, 2004 HT-FED MEASURED PERFORMANCE OF A MICRO THERMOELECTRIC COOLER Luciana W. da Silva and Massoud Kaviany Department of Mechanical Engineering University of Michigan Ann Arbor, Michigan ldasilva@umich.edu, kaviany@umich.edu Mehdi Asheghi Department of Mechanical Engineering Carnegie Mellon University Pittsburgh, Pennsylvania masheghi@andrew.cmu.edu ABSTRACT The measured performance of a column-type micro thermoelectric cooler, fabricated using vapor deposited thermoelectric films and patterned using photolithography processes, is reported. The columns, made of p-type Sb 2 Te 3 and n-type Bi 2 Te 3 with an average thickness of 4.5 µm, are connected using Cr/Au/Ti/Pt layers at the hot junctions, and Cr/Au layers at the cold junctions. The measured Seebeck coefficient and electrical resistivity of the thermoelectric films, which were deposited with a substrate temperature of 130 o C, are -74 µv/k and 3.6x10 5 Ω- m (n-type), and 97 µv/k and 3.1x10 5 Ω-m (p-type). The cooling performance of devices with 60 thermoelectric pairs and a column width of 40 µm is evaluated under a minimal cooling load (thermobuoyant surface convection and surface radiation). The temperatures of the cold and hot surfaces are obtained with an infrared camera. The average cooling achieved is about 1 K. The measured overall electrical resistance ranges from 51 to 58 Ω. Current challenges include the reduction of the column width, implementation of higher substrate temperatures for optimum thermoelectric properties, and improvements of the top connector fabrication. NOMENCLATURE A k cross-sectional area of the thermoelectric element (m 2 ) d te width of the thermoelectric element (m) J e electrical current (A) k thermal conductivity (W/m-K) thickness of the thermoelectric element (m) L te Address all correspondence to this author. N te number of thermoelectric pairs Q c load heat flow rate (W) R e electrical resistance (Ω) R k conduction resistance (K/W) T temperature (K) Z e figure of merit (1/K) α S Seebeck coefficient (V/K) ϕ voltage (V) electrical resistivity (Ω-m) ρ e Subscripts b boundary c contact e electron n n-type thermoelectric material p p-type thermoelectric material, phonon ambient INTRODUCTION Telluride compounds are the thermoelectric (TE) materials used in the fabrication of the micro TE cooler, since they currently have the highest cooling performance at room temperature. The techniques used for the synthesis of these compounds are dependent, among other factors, on the desired film thickness. Zou et al. [1] deposited thin films (700 nm) of n-type Bi 2 Te 3 and p- type Sb 2 Te 3 by vapor deposition, which had a room-temperature dimensionless figure of merit Z e T of approximately 0.3. The Seebeck coefficient α S and electrical resistivity ρ e were -200 µv/k and Ω-m for the n-type material, and Copyright c 2004 by ASME

2 µv/k and Ω-m for the p-type material. Min and Rowe [2] proposed a micro TE cooler where the TE thin films are grown on a very thin, low thermal conductivity SiC membrane (PECVD) to minimize the heat leakage effect. In their design, the electrical current and heat flow parallel to the film plane. Lim et al. [3] deposited thick films (20 µm) of telluride compounds using electroplating for fabrication of TE coolers, where the current and heat flow perpendicular to the film plane (column-type design). They built a microdevice that presented a maximum cooling of 2 K, and Z e T of The n-type Bi 2 Te 3 films exhibited in-plane Seebeck coefficients ranging from -30 to -60 µv/k and an in-plane electrical resistivity of Ω-m. The properties of the p-type Bi 2 x Sb x Te 3 films were not fully characterized due to poor reproducibility. Böttner [4], depositing 20 µm of telluride compounds by co-sputtering, developed a column-type micro cooler using a two-wafer concept (n- and p-type materials are first deposited on separated wafers, patterned and then soldered together). This allowed an optimal post-processing of the n- and p-type wafers. The Seebeck coefficient and electrical resistivity were -155 µv/k and Ω-m for the n-type film, and 227 µv/k and Ω-m (after annealing) for the p-type film. The net cooling obtained was 36.7 K [5]. Conventional column-type TE coolers have not been fabricated with thin films (less than 1 µm) due to the parasitic conduction heat transfer between the hot and cold junctions, and the thermal and electrical contact resistances. These problems can be minimized if thicker films (2 to 10 µm) are used. Here, this design is considered for a wireless micro system application, where the TE films (Bi 2 Te 3 and Sb 2 Te 3 ), grown based on the vapor deposition technique of Zou et al. [1], are 4 to 5 µm thick. The device design is based on predictions from a TE cooler model [6]. The fabrication steps and results from the device characterization, which include the predicted and measured device performances, are presented and discussed. (a) (c) Bi 2 Te 3 Cr/Au/ Ti/Pt Sb 2 Te 3 4 µm 0.26 µm 550 µm Cr/Au/Ti/Pt (Hot Connector) n Sb 2 Te 3 p-type 20 µm Si p Bi 2 Te 3 n-type Ti/Pt Cr/Au SiO 2 A A 7 µm Figure 1. Bi 2 Te 3 AND Sb 2 Te 3 FILMS DEPOSITED ON Cr/Au/Ti/Pt HOT (BOTTOM) CONNECTORS. THE COLD (TOP) CONNECTORS ARE NOT SHOWN. (a) SKETCH SHOWING THE APOXIMATE THICK- NESS OF THE FILMS. SEM MICROGRAPH SHOWING A TOP VIEW OF THE FABRICATED STRUCTURES. THIS IMAGE IS THE EN- LARGED SECTION A INDICATED IN THE PART (c), TOP RIGHT. (c) SEM MICROGRAPH OF A DEVICE WITH 50 TE PAIRS. DEVICE FABRICATION The silicon wafer used in the fabrication is also the micro cooler heat sink. To provide electrical insulation for the device, a 850 nm silicon dioxide layer is grown on the Si wafer. Photoresist () is spun cast, defining a lift-off pattern for the hot (bottom) connectors and electrical connectors (pads). These connectors are Cr/Au/Ti/Pt layers grown by e-beam evaporation. The Au and Pt layers are 200 nm and 20 nm thick, respectively. The Cr and Ti are 20 nm thick seed layers. The Pt, which has an electrical resistivity about 5 times larger and a thermal conductivity about 5 times smaller than Au, is used for its good adhesion to the columns, while preventing the diffusion of Au. Each column of the TE element is patterned consecutively before evaporation using an Omnicoat/SU-8 1 mold, in which the n-type (or p- type) TE element will be formed [7]. Once the TE films have been deposited (with a substrate temperature 2 of 130 C), the is removed, leaving only the columns on top of the hot connectors, as illustrated in Figure 1(a). The actual Sb 2 Te 3 and Bi 2 Te 3 TE elements deposited on the hot connector pattern are shown in Figures 1 and 1(c). The steps needed to complete the fabrication process are pre- 1 SU-8, after exposure and post-exposure bake, becomes a highly cross-linked epoxy, which is extremely difficulty to remove with conventional solvent-based resist strippers. Therefore, a layer of Omnicoat was deposited prior to SU-8. After developing SU-8, the Omnicoat was developed in an O 2 plasma. 2 For Sb 2 Te 3 films, depositions with a substrate temperature greater than or equal to 210 C resulted in an over hardbaked, which could not be removed without damaging the thermoelectric films. For Bi 2 Te 3 films, the limiting temperature is 170 C. 2 Copyright c 2004 by ASME

3 (a) Si Ti/Pt Cr/Au SiO 2 h Cr/Au Si (c) Si Cr/Au or Ti/Au µm 4 µm 0.26 µm 550 µm Figure 2. SCHEMATIC OUTLINING THE OCEDURE FOR FABRI- CATION OF THE COLD (TOP) CONNECTORS. (a) CONTACT OPENING FOR Cr/Au. CONTACT OPENING FOR Au. (c) STRUCTURE THAT WILL BE CONNECTED TO A MICRO SYSTEM (LOAD). sented in Figure 2. A contact area is defined on top of each TE element [Figure 2(a)]. After developing and hardbaking the (AZ9245), a thin Cr/Au layer (20 nm/20 nm) is deposited by sputtering. This metallization is necessary to avoid the exposure of the in the subsequent photolithography process [Figure 2], which is required to define the area where Au (the metal that forms the cold connectors and closes the electrical circuit of the TE cooler) is deposited [Figure 2(c)]. This structure will be connected to a load. To ensure a clean electrical contact opening, the on top of the columns is overexposed. This is due to variations in the thickness, caused by differences in the height of the TE elements (differences as large as 0.8 µm between the n- and p-type TE elements have been observed). Using Ti/Cu and Cu for the last two metallizations (hot connector) result in a large increase in the total electrical resistance of the devices with time, which might be due to oxidation of the Cu. The height of the above the columns, indicated by h in Figure 2, ranges from 1 to 2 µm. Due to this surface nonuniformity, two techniques have been tested for the deposition of the top connector. First, using sputtering (which allows a good step coverage), the top connector was formed by a thin layer of Cr/Au (50 nm/250 nm). In other trials, using evaporation, a thicker layer, Ti/Au (1500 nm/500 nm), was needed. In Figures 3 and 4, the results of the cold connector fabrication by sputtering and by evaporation are shown, respectively, where the layers [indicated in Figure 2] were successfully removed with lift-off in acetone. Note that in Figure 3 there are undesired residual materials left on the top connectors (which cause poor Figure 3. SEM MICROGRAPH SHOWING A COMPLETE ELECTRI- CALLY CONNECTED DEVICE WITH 3 TE PAIRS, WHERE THE TOP CONNECTOR WAS DEPOSITED BY SPUTTERING. THE CROSS- SECTIONAL AREA OF THE TE COLUMNS IS EQUAL TO 40 µm x40 µm. thermal contact with the load). This is due to the Cr/Au that is grown on the side walls of the mode. Here there is a compromise between decreasing the thickness, and allowing enough height for the lift-off. Improvements in the processing techniques are currently being tested, while other geometries [micro TE coolers with up to 300 TE pairs and column width raging 7 µm to40µm] are being fabricated. DEVICE CHARACTERIZATION The cooling performance of the fabricated micro TE coolers has been evaluated at an ambient temperature T of 63 C (all devices discussed here were fabricated on the same wafer). The TE properties, composition and crystal structure of the n- and p- type films that compose these devices were investigated. From a TE cooler model [6], the cooling performance was predicted and compared with the measured results. Properties of Bi 2 Te 3 and Sb 2 Te 3 Films The measured substrate temperature during the film deposition (T sub ), thickness (L te ), electrical resistivity (ρ e ), Seebeck coefficient (α S ) and stoichiometry (At% element ratio) of the n- and p-type TE elements are given in Table 1. The measurement techniques have been discussed in [7]. The diffraction patterns are shown in Figure 5. The data agree with the associated entries in the Powder Diffraction File [8], and the corresponding reflection planes (hkl) are labeled. The results confirm the formation of Bi 2 Te 3 and Sb 2 Te 3 and show that the films are polycrystalline without a strong preferential orientation. 3 Copyright c 2004 by ASME

4 (a) Table 1. DEPOSITION CONDITIONS AND MEASURED OPERTIES OF Bi 2 Te 3 and Sb 2 Te 3 FILMS (AT ROOM TEMPERATURE). TE Film Sb 2 Te 3 Bi 2 Te 3 T sub, C L te, µm ρ e, µω-m α S, µv/k At%Te/At%(Bi or Sb) (a) Intensity (015) (1.0.10) (0.0.15) (1.0.19) (015) (10.10) (110) (02.10) (11.15) Sb 2 Te 3 Bi 2 Te Diffraction angle (2θ) Diffraction angle (2θ) Figure 4. SEM MICROGRAPH SHOWING COMPLETE ELECTRI- CALLY CONNECTED DEVICES WITH (a) 3 and 60 TE PAIRS. THE TOP CONNECTORS WERE DEPOSITED BY EVAPORATION. THE CROSS-SECTIONAL AREA OF THE COLUMNS IS EQUAL TO 40 µm x 40 µm. Predicted Cooling Performance In [6], the flows of heat and electricity in a micro TE cooler have been analyzed. Consideration was given to the phonon (A k R k ) b,pp and electron (A k R k ) b,ee boundary resistances, the phonon-electron non-equilibrium adjacent to the interfaces of the TE elements, and the thermal (A k R k ) c and electrical (A k R e ) c contact resistances. Using the measured (L te, ρ e and α S ) and base-line properties given in Tables 1 and 2, respectively (where k is the thermal conductivity of the TE element), the performance of a device with the number of TE pairs N te equal to 60 and a cross-sectional area of the columns A k (= dte)of40µmx40µm, 2 was evaluated. The predicted device total electrical resistance R e is 50 Ω, and the maximum temperature difference between the heat sink and the top connector 3 (T T c ) is 0.5 K, for an ap- 3 The temperature difference (T T c ) is also referred in the text as the device cooling performance. The coefficient of performance, which is the ratio between the cooling load Q c and the electrical power, is nearly zero (Q c is minimal). Figure 5. X-RAY DIFFRACTION PATTERN OF CO-EVAPORATED (a) Sb 2 Te 3 AND Bi 2 Te 3 FILMS. THE MEASURED PEAKS AGREE WITH THE POWDER DIFFRACTION FILE [8]. Table 2. BASE-LINE OPERTIES USED IN THE TE COOLER MODEL, [6]. TE Film Sb 2 Te 3 Bi 2 Te 3 k, W/m-K (A k R k ) c, K/(W/m 2 ) (A k R e ) c, Ω-m (A k R k ) b,pp, K/(W/m 2 ) (A k R k ) b,ee, K/(W/m 2 ) plied voltage ϕ of 1.8 V, an electrical current J e of 36 ma, and under no cooling load Q c. Note that, for a Q c of 0.1 mw (thermobuoyant surface convection and surface radiation), (T T c ) decreases only by less than 1%. 4 Copyright c 2004 by ASME

5 Measured Cooling Performance Using an infrared thermal microscope (InfraScope II) and 5x lens (pixel resolution of 4.8 µm and accuracy of 5%), the thermal image of a fabricated micro TE cooler (N te of 60 and d te of 40 µm) operating at a J e of approximately 23 ma was obtained, and is shown in Figure 6 4. The measured R e of this device (at room temperature) was 51 Ω. Note that, in the graph of Figure 6, a side-view schematic drawing of the TE pairs (scaled with respect to pixels) indicates the position of the line trace in the thermal image. Darker lines, which indicate lower temperatures, are above the TE elements, while the surfaces of the bottom connectors and the substrate (SiO 2 ) are marked by higher temperatures. In this case, (T T c ) can be approximated to 1.3 ± 0.5 K, where T is maintained at about 63 C. In the thermal image, the isolated spots with large temperature gradients indicate fabrication defects. This device had the top connectors deposited by sputtering, and, as shown in Figure 3, there are residual metals not completely removed by the liftoff process. These can cause an electrical short-circuit between the top and bottom connectors. The non-uniform temperatures observed at the top connectors can be due to the TE element surface roughness or oxidation, both of which compromise an efficient thermal contact. A second device, also with N te of 60, d te of 40 µm, and with the top connector deposited by sputtering, was annealed at 200 C for 2 hours in a nitrogen stream. The measured R e before and after annealing were 51 Ω and 58 Ω, respectively. A thermal image of this device is shown in Figure 7. Observe the difference in the lay-out of the TE elements and connectors along lines 1 and 2 (shown by the side-view schematic drawings superimposed on the temperature graphs). The line trace 2 marks the complete extension of the top connectors, where lower temperatures, although not uniform, are evident. In this case, (T T c ) can be approximated as 0.8 ± 0.5 K (where T is maintained at about 62.5 C), indicating that annealing (at the conditions mentioned above) did not significantly affect the overall device cooling performance when compared with the first device tested. However, note that this was a preliminary attempt on improving the performance by thermal post-treatment. A more careful investigation on annealing is underway, where the inclusion of a diffusion barrier between the TE elements and metal connectors is being considered. The micro TE coolers with the top connectors deposited by evaporation presented an overall electrical resistance 1.6 to 1.8 times the R e of the devices previously discussed (i.e., devices with top connectors deposited by sputtering), and it increased up to 5 times after annealing at 200 C for 2 hours in a nitrogen stream. These devices produced no detectable cooling. This Defect Line Trace Figure 6. INFRARED SURFACE THERMAL IMAGE OF A DEVICE WITH 60 TE PAIRS AND COLUMN WIDTH OF 40 µm. THE TOP CON- NECTORS WERE DEPOSITED BY SPUTTERING. might be due to the diffusion of the thick Ti layer (1.5 µm, deposited prior to Au) into the TE elements. Comparison between Measured and Predicted Cooling Performances The characterized devices have an overall electrical resistance about 2% (before annealing) to 16% (after annealing) larger than the predicted resistances. The measured device temperature difference (T T c ) was approximately 100% larger than the predicted value. The defects observed as hot spots in the thermal images indicate that improvements can be made in the fabrication of the top connectors, which would increase the disagreement between the measured and predicted performances. The properties used in the TE cooler model [6], which are 4 A color version of this paper is available at www-personal.engin.umich.edu / kaviany/researchtopics/topics.html. 5 Copyright c 2004 by ASME

6 (a) 2 T - T c, K α S ρe k 0.5 T - T c, K Fraction of measured/predicted TE property (A k R k ) c (A k R e ) c (A k R k ) b,pp (A k R k ) b,ee Fraction of predicted resistance Figure 8. EFFECT OF (a) TE OPERTIES AND RESISTANCES USED IN THE TE COOLER MODEL ON THE EDICTED COOLING PERFORMANCE OF A DEVICE WITH 60 TE PAIRS AND COLUMN WIDTH OF 40 µm. 2 Figure 7. INFRARED SURFACE THERMAL IMAGE OF A DEVICE WITH 60 TE PAIRS AND COLUMN WIDTH OF 40 µm, WHICH WAS ANNEALED AT 200 C FOR 2 HOURS. THE TOP CONNECTORS WERE DEPOSITED BY SPUTTERING. THE LAYOUTS OF THE TE ELEMENTS AND CONNECTORS ALONG LINES 1 AND 2 ARE REESENTED BY THE SIDE-VIEW SCHEMATIC DRAWINGS AT THE TEMPERATURE GRAPHS. given in Tables 1 and 2, present uncertainties that can be related to this difference. It is possible that the TE properties of the films have changed during the top connector fabrication process, where the wafer was heated to as high as 200 C. The sensitivity of the device overall performance to the TE properties and thermal and electrical resistances is shown in Figures 8(a) and 8, for ϕ, Q c, T, N te and d te equal to 1.8 V, 0.1 mw, 63 C, 60 pairs and 40 µm, respectively. The TE properties are varied up to ±50% of their base values and the resistances are varied from a factor of 0.1 to a factor of 10. Note that, from Figure 8(a), the relation α 2 S /(ρ ek) (a measurement of the TE element performance) is not obeyed. This is due to the TE element geometry being far from optimum (L te /d te around unity). In Figure 8, it is seen that the device performance is less sensitive to the electrical than to the thermal resistances (boundary and contact). FABRICATION OF NEXT GENERATION DEVICE Developments in the fabrication of a micro TE cooler comprise overcoming the limits encountered with the processes indicated in Figure 9. The results presented in previous sections 6 Copyright c 2004 by ASME

7 are labled as GEN-0. In this generation, a limit on the TE column length was reached due to difficulty in controlling the sublimation of the tellurium element. The uncertainty in the deposition rate increases with the depletion of Te inside the evaporation boat. When this fluctuation is greater than ± 0.6 Å/s (for films thicker than 5 µm), large stoichiometry non-uniformity is generated. The next generation of devices, GEN-1, which is currently being fabricated, focuses on improvements in the photolitography process that defines the pattern for the TE elements. The objective is to reduce the column width d te, since the optimum aspect ratio L te /d te was estimated to be around 1.5 [6]. The lower limit of 7 µm is due to the minimum feature size (3 µm) obtainable using the mask fabrication process. The limit of 160 C for the substrate temperature is related to the maximum temperature that the (used for patterning the columns) can be exposed to without over hardbaking (when it can not be removed without damaging the TE elements). The increase in substrate temperature is desired to obtain a dimensionless figure of merit Z e T [which is equal to T α 2 S /(ρ ek)] greater than 0.3 [1]. Z e is also sensitive to the film stoichiometry, as shown by preliminary results reported in [7] and confirmed by an ongoing investigation. This stoichiometry effect is being explored in order to maximize the performance of the TE films at T sub < 160 C. The breakthrough in cooling performance, GEN-2, can be realized if the TE films are deposited and patterned at optimal conditions, i.e, 230 C < T sub < 260 C, [1, 6]. This generation of devices will be able to lower the temperature of a chemiresistor vapor sensor 10 K below ambient. The inclusion of hightemperature photoresist or modifications of the fabrication steps (such as use of shadow mask or use of etching to pattern the TE films) are needed to allow for these higher substrate temperatures. As discussed in pervious sections, the yield and performance of the GEN-0 devices was greatly affected by the fabrication method of the top connector. Therefore, in GEN-1, the introduction of a diffusion barrier between the TE element and connectors, and the removal of the first Cr/Au layer used to avoid the exposure of the between the columns, are also being explored. CONCLUSION Micro TE cooler devices with 60 TE pairs, and thickness and width of columns of approximately 4.5 µm and 40 µm, respectively, were fabricated using co-evaporation for deposition of the TE elements. The Seebeck coefficient and electrical resistivity of the films were measured, and from a micro TE cooler model a net cooling of 0.5 K was predicted for an applied voltage of 1.8 V and minimal cooling load of 0.1 mw. The predicted total electrical resistance R e was 50 Ω. Using an infrared camera, thermal images of these devices Photolitography Limit on TE ColumnWidth d te = 7 µm GEN-1 > 5 K d te, µm GEN-0 ~ 1 K 6 Directions for Optimum L te, µm Cooling Performance Substrate (TE Film Deposition) Temperature Limit on Photoresist Removal T sub = 160 ο C T sub, ο C GEN-2 > 10 K Uniform Stoichiometry Limit on TE Colum Length L te = 5 µm Figure 9. MAP OF DEVICE GENERATION AIMING AT GEN-2. GEN- 0 HAS BEEN COMPLETED. GEN-1 IS THE NEXT GENERATION OF DEVICES. operating at 23 ma and at an ambient temperature of 63 C were obtained. An average cooling performance of 1.3±0.5 K was verified (measured R e of 51 Ω). For a device with same geometry and TE properties, which was annealed at 200 C for 2 hours, the cooling performance was 0.8±0.5 K. After annealing, the electrical resistance increased to 58 Ω, which is an indication of need for a diffusion barrier between the metal connectors and TE elements. The next-generation of devices, currently being fabricated, focuses on increasing the ratio L te /d te (about for GEN-0) towards unity. As the TE element length has reached a limit of 5 µm (uniform stoichiometry limit), improvements will be made in the photolitography process to allow for a smaller d te. ACKNOWLEDGMENT This work was supported by the Engineering Research Center Program of the National Science Foundation under Award Number EEC , at the University of Michigan s Wireless Integrated Micro Systems (WIMS) Center and by the Conselho Nacional de Desenvolvimento Cientifico e Tecnologico - CNPq, Brazil (LWDS). The authors are also thankful to Professor K. Wise and Dr. A. DeHennis for the help on the device design and fabrication, Professors C. Uher and J. Dyck for the help on the fabrication and characterization of the thermoelectric films, and Y. Yang (CMU) for the thermal images. 7 Copyright c 2004 by ASME

8 REFERENCES [1] Zou, H., Rowe, D.M., and Williams, S.G.K., 2002, Peltier effect in a co-evaporated Sb 2 Te 3 (p) -Bi 2 Te 3 (n) thin film thermocouple, Thin Solid Films, 408, [2] Min, G., and Rowe, D.M., 1999, Cooling Performance of Integrated Thermoelectric Microcooler, Solid-State Electronics, 43, [3] Lim, J.R., Snyder, G.J., Huang, C.-K., Herman, J.A., Ryan, M.A., and Fleurial J.-P., 2002, Thermoelectric Microdevice Fabrication Process and Evaluation at the Jet Propulsion Laboratory (JPL), Proceedings of the 21th International Conference on Thermoelectrics, Long Beach, California, [4] Böttner, H., 2002, Thermoelectric Micro Devices: Current State, Recent Developments and Future Aspects for Technological Progess and Applications, Proceedings of the 21th International Conference on Thermoelectrics, Long Beach, California, [5] Böttner, H., 2004, Private Communications. [6] da Silva, L.W. and Kaviany, M., 2004, Micro Thermoelectric Cooler: Size Effects on Thermal and Electrical Transport, International Journal of Heat and Mass Transfer, 47, (10-11), [7] da Silva, L.W., Kaviany, M., DeHennis, A., and Dyck, J., 2003, Micro Thermoelectric Cooler Fabrication: Growth and Characterization of Patterned Sb 2 Te 3 and Bi 2 Te 3 Films, Proceedings of the 22th International Conference on Thermoelectrics, La Grande Motte, France, [8] Joint Committee on Powder Diffraction Standards (JCPDS), 1983, Powder Diffraction File, Swarthmore, Pennsylvania, Cards 8-27 and Copyright c 2004 by ASME