Dr. Lynn Fuller Webpage:

Transcription

1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Microelectromechanical Systems (MEMs) Process Integration Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Tel (585) Fax (585) Department webpage: mem_proc.ppt Page 1

2 OUTLINE Surface Micromachine Processes ngle Poly Layer Processes mple ngle Mask Process Anchor Process Anchor Plus Dimple Process Substrate Isolation Process Two Poly Layer Processes Center Pin Bearing Process Flange Bearing Process Bulk Micromachine Processes licon Diaphragm Process Advanced licon Diaphragm Design Surface Diaphragm Design Integrating Electronics with MEMs Page 2

3 SIMPLE ONE MASK PROCESS 2 µm licon Dioxide LPCVD 2.5 µm Poly licon Pattern Poly Anchor Etch Oxide Released Cantilever Page 3

4 ANCHOR PROCESS 2 µm licon Dioxide Pattern Anchor Holes 2.5 µm Poly licon Pattern Poly Anchor Etch Oxide Released Cantilever Page 4

5 ANCHOR PLUS DIMPLE PROCESS 2 µm licon Dioxide Pattern Bushing Mold Pattern Anchor Holes 2.5 µm Poly licon Pattern Poly and Etch Oxide Bushing Anchor Page 5

6 SUBSTRATE ISOLATION PROCESS Pad Oxide and Nitride Pattern Bushing Mold 2 µm licon Dioxide 2.5 µm Poly licon Pattern Anchor Holes Pattern Poly and Etch Oxide Bushing Anchor Pad Oxide and Nitride Page 6

7 SURFACE MICROMACHINED POLY DIAPHRAGM 30,000 Å O 2 Photolithography Etch in BHF LPCVD 2.0 µmpoly Photolithography Etch Poly in SF6+ O2 Etch O2 in BHF Page 7

8 SURFACE MICROMACHINED POLY DIAPHRAGM Poly Covered Trench 200 µm John Castellana, 1997 BSµE RIT 2 µm Poly 1.5 µm Gap Page 8

9 CENTER-PIN BEARING PROCESS CVD Oxide Pattern Bearing Anchor Pattern Bushing Mold Pattern Bearing Pattern Rotor Release Page 9

10 CENTER PIN AND SUBSTRATE BEARING PROCESS Substrate Insulator and 1st Poly Pattern Substrate Bushing Pattern Bearing Anchor Pattern Rotor Pattern Bearing CVD Oxide Release Page 10

11 FLANGE BEARING PROCESS Pattern Bushing Mold Bearing Clearance LTO Bearing Anchor Pattern Rotor Bearing Poly Deposition and Etch Flange Underetch Release Page 11

12 BACKSIDE ETCHED BULK MICROMACHINED P+ ETCH STOP DIAPHRAGM PROCESS 1500 Å 3 N 4 Boron Doped P+ Etch Stop and n-type Epitaxial Layer LPCVD Nitride Photolithography Etch Nitride insf6 P-type Ion Implanted Resistors KOH Wet Etch P+ Etch Stop 500 µm N epi layer 5-10µm Page 12

13 BACKSIDE ETCHED BULK MICROMACHINED POLYSILICON DIAPHRAGM PROCESSES 1500 Å 3 N 4 10,000 Å Thermal Oxide Photo define Oxide for diaphragm spacer LPCVD Polysilicon diaphragm of 2 µm thickness and removed from backside of wafer LPCVD Nitride Photolithography Etch Nitride insf6 KOH Wet Etch Stop on Oxide Etch Oxide and Nitride Either thin film resistor or capacitive sensor on poly diaphragm. Page 13

14 TOP SIDE BULK MICROMACHINED SILICON NITRIDE DIAPHRAGM 1500 Å 3 N 4 Photolithography Etch insf6 LPCVD 0.8µmPoly Photolithography Etch Poly in SF6+ O2 LPCVD 0.8µm Low Stress 3 N 4 Photo Etch Holes Etch in KOH Page 14 Fill Etch Holes with LPCVD

15 SCREAM PROCESS ngle Crystal Reactive Ion Etched Process for Microelectromechanical Structures A process that involves anisotropic (Cl 2 /BCl 3 ) reactive ion etch (RIE) followed by isotropic (SF 6 ) RIE Page 15

16 INTEGRATING ELECTRONICS WITH MEMS Poly Gate PMOS and MEMs at the Same Time CMOS first MEMs After MEMs first CMP CMOS After CMOS and MEMs at the Same Time 10x 6 µm Topology is the main problem Page 16

17 ELECTRONICS CHIP PLUS MEMS CHIP IN SAME PACKAGE Page 17

18 SCALED DRAWING Poly 2 Poly 1 SacOx Poly 1 via 3N4 licon Substrate 2 um Page 18

19 ADDRESSING TOPOLOGY 1. Use thicker layers for each subsequent layer. 2. Run interconnects in poly over topology because LPCVD is a conformal deposition process. 3. LOCOS like processes to reduce topology. 4. CMP Page 19

20 ADDRESSING TOPOLOGY Poly 1 rotating gear Poly 2 anchor pin Poly 3 - linkage X Y X and Y movement 90 out of phase Poly 1 X/Y motion Where is CMP used and why? Page 20

21 CMOS FIRST MEMS AFTER Page 21

22 CMOS FIRST MEMS AFTER, TEXAS INSTRUMENTS TI Digital Mirror Array TORSIONAL MIRRORS 1 million Mirrors Page 22

23 MEMS FIRST CMP THEN CMOS PROCESSING Buried Polysilicon MEMs with CMP planarization and CMOS post-fabrication (after Nasby, et al, 1996) Page 23

24 PROTECTING ELECTRONICS 1. Poly, Aluminum or nitride layer 2. Glass 3. Organics (Protek) 4. One-sided wafer etcher. Page 24

25 REFERENCES 1. From Microsensors to Microinstruments, Petersen, K.E., Sensors and Actuators, vol. A56, nos. 1-2, Aug. 1996, pp The Challenge of Automotive Sensors, Giachino, J.M., and Miree, T.J., Proceedings of the SPIE Conference on Microlithography and Metrology in Micromachining, Austin, TX, Oct , 1995, SPIE Vol. 2640, pp Integrating SCREAM Micromachined Devices with Integrated Circuits, Shaw, K.A. and Mac Donald, N.C., Proceedings of IEEE International Workshop on Micro Electro Mechanical Systems, San Diego, CA, Fe 11-15, 1996, pp Laminated High-Aspect-Ration Microstructures in a Conventional CMOS Process, Fedder, G.K., et.el., Proceedings of IEEE International Workshop on Micro Electro Mechanical Systems, San Diego, CA, Fe 11-15, 1996, pp Page 25

26 HOMEWORK - PROCESS INTEGRATION 1. List a step by step process to make a cantilever accelerometer that has a piezoresistive sensor for measuring the acceleration. There are many different ways to do this so just state your assumptions and use those for your design. 2. Show a cross section with dimensions. 3. Show a top down layout with dimensions 4. Show example calculations relating acceleration to output voltage. Again make appropriate assumptions. Page 26