Supporting Information. Fabrication of Flexible Transparent Electrode with Enhanced Conductivity from Hierarchical Metal Grids

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1 Supporting Information Fabrication of Flexible Transparent Electrode with Enhanced Conductivity from Hierarchical Metal Grids Linjie Li, 1 Bo Zhang, 1 Binghua Zou, 1 Ruijie Xie, 1 Tao Zhang, 1 Sheng Li, 1 Bing Zheng, 1 Jiansheng Wu, 1 Jiena Weng, 1 Weina Zhang, 1 Wei Huang* 1, 2 and Fengwei Huo* 1 1 Key Laboratory of Flexible Electronics (KLOFE) & Institute of Advanced Materials (IAM), Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM), Nanjing Tech University (NanjingTech), 30 South Puzhu Road, Nanjing , P. R. China 2 Key Laboratory for Organic Electronics and Information Displays (KLOEID), Institute of Advanced Materials (IAM), Nanjing University of Posts and Telecommunications, Nanjing , P. R. China * Corresponding author: iamfwhuo@njtech.edu.cn; iamwhuang@njtech.edu.cn S-1

2 Experiments General materials and instruments shipley1805 (S-1805) and MF319 (MicroChem), spin-coater (CHEMAT GROUP KW-4A-CE), wafers (Silicon), chromium (Cr) masks (SuZhou RuiCai), oxygen plasma (Harrick PDC-32G), buffered hydrofluoric acid (Transene Company), 1H,1H,2H,2H-perfluorodecyltrichlorosilane (Gelest), PDMS and curing agent (Sylgard 184, Dow Corning), fiber-lite illuminators (Dolan-Jenner, MI-150), UV light (UVATA, wavelength of 395 nm), thermal evaporation (SKY Technology Development Co., Ltd, CAS). OM (Olympus), AFM (Park Systems Co.) and SEM (Hitachi S-4800), four-point probe technique (Four Probes Tech, RTS-8). UV spectrophotometer (SHIMADZU, UV-1750), ZnS:Cu and dielectric layer (ShangHai Keyan Phosphor Technology Co), 2400 (keithley). Fabrication of PDMS photomasks S-1805 photoresist was spin-coated on Si (100) wafers with 280 nm SiO 2 to perform conventional far-field photolithography with Cr masks. The Cr masks with micrometer feature size have various line shapes customized from company. After exposure, MF319 was used to develop the photoresist patterns. Then the developed photoresist patterns were treated with oxygen plasma for 5 mins to remove the residual under-developed photoresist. Subsequently, the obtained substrates were put in a S-2

3 commercial buffered hydrofluoric acid for 4 mins to etch away the unprotected SiO 2 inside the features. After this, the photoresist was removed by rinsing in acetone. The obtained Si/SiO 2 substrates were put in KOH etching solution (30% KOH in H 2 O: isopropanol (4:1 v/v)) at 80 C with vigorous stirring to etch the exposed silicon inside the features anisotropic, producing the recessed V-shape trench arrays. Subsequently, the samples were put in buffered hydrofluoric acid for sufficient time (6 mins) to remove the remaining SiO 2. Finally, the Si trench masters were modified with 1H,1H,2H,2H-perfluorodecyltrichlorosilane by gas-phase silanization, rendering them hydrophobic. For preparing PDMS stamp, the mixture of PDMS monomer and its curing agent with a 10:1 wt ratio was poured on silicon masters with the PDMS layer thickness around five millimeters. After removing the bubbles which formed during the mixture process, the sample was cured at 80 C for 4 h and the PDMS trenches were carefully separated from silicon masters. Then the PDMS was cut into a PDMS stamp with the pattern copy from the master, which could be used for near-field photolithography. Fabrication of hierarchical metal grids (HMG) FTCEs PET substrate bought from market was put in ethanol, acetone and DI water ultrasonic cleaning before spin-coating photoresist S-1805, then the photoresist-coated PET was soft-baked on the hot plate at 90 C for 4 S-3

4 mins. PDMS stamp was intimate contact with the positive photoresist, and a fiber-lite illuminators with the adjustable power between 0 and 250 mw/cm 2 was used to expose. After that, Cr mask customized with grids pattern was hard contact with the substrate, and UV light was used to exposure. Subsequently after the exposure, the sample was developed in MF319. Then the substrate with patterned photoresist were evaporated with 3 nm Cr / 15 nm Ag by thermal evaporation. Finally, the sample was under sonication in acetone in sequence, and we would get the FTCE. Characterization of R s -T OM, AFM and SEM were used to characteristic the morphology of the hierarchical metal grids. And the sheet resistance of the FTCEs obtained from four-point probe technique. The light transmittance was defined by UV spectrophotometer. The FTCEs were twined around a glass rod with radius 3 mm to test the flexibility. Fabrication of LED The fabrication details of LEDs: Firstly, the electroluminescence ZnS:Cu and dielectric were mixed with the PB glue with a 1:1 wt ratio, respectively. Secondly, the ZnS:Cu was coated on the HMG electrode, then it was dried at 60 C for 10 mins. Thirdly, the dielectric layer was coated on the ZnS:Cu layer and dried at 60 C for 10 mins. Lastly, a counter electrode was put on the dielectric layer and the device was finished. S-4

5 Calculation of the metal cover percent We focused on a single coarse grid and the metal nanowire arrays in one coarse grid. For the coarse grids, the four sides were used twice, so we calculated half of the four sides. For the arrays, the total area of the gradient lines was the same as the area when the lines were vertical. So, the width and space of coarse grid and metal nanowire were D, L, d, l, respectively, then the cover percent was (D*(D+L) +d*l/l)/(l+d) ^2. S-5

6 Figure S1. A) OM image and B) SEM image of the metal grids (MG) on PET Figure S2. SEM images of the HMG on PET. A) 5 µm /100 µm, B) 7.5 µm /100 µm, C) 10 µm /150 µm, D) 10 µm /200 µm. S-6

7 Figure S3. Evolution of the transmittance of the MG electrodes and HMG electrodes with the same coarse grids size. A) 5 µm /100 µm, B) 7.5 µm /100 µm, C) 10 µm /150 µm, D) 10 µm /200 µm. S-7

8 Figure S4. Evolution of the transmittance of the MG (10 µm /100 µm) and HMG (10 µm /100 µm). S-8

9 Fig. S5. SEM image of HMG after 1000 cycles bending and the metal lines did not peel off from the PET substrate. Fig. S6. The structure of LEDs. S-9

10 Fig. S7. The IV test and optoelectronic properties of LEDs. A, C) fabricated by HMG electrode. B, D) fabricated by ITO electrode. S-10

11 Table S1. Metal per cent of our FTCEs and their influence of R s and T Size of FTCEs Metal percent R s of FTCEs T of FTCEs Metal percent (µm) of FTCEs (%) (Ω/sq) (%) of nanowire arrays (%) MG 10/ / / / / HMG 10/ / / / / S-11