Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators

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1 Semiconductor Physics, Quntum Electronics & Optoelectronics, , N 2. P PCS Qv Friction nd chrcteriztion of 0.14 μm CMOS device using THEN nd TLS simultors Irhim hmd 1, Yep Kim Ho 2, Burhnuddin Yeop Mjlis 1 1 Dept. of Electricl, Electronic nd Systems Engineering, Fculty of Engineering University Kengsn Mlysi, MLYSI Phone: ; fx: E-mil: irhim@vlsi.eng.ukm.my; urhn@eng.ukm.my 2 Dept. of Physicl Sciences, Electricl nd Electronics, Fculty of Engineering nd Science University Tunku dul Rhmn, MLYSI Phone: ; fx: E-mil: yepkh@mil.utr.edu.my strct µm CMOS trnsistor with two levels of interconnection ws designed nd simulted to investigte its functionlity nd chrcteristics. THEN nd TLS simultors were used to simulte the friction process nd to vlidte the electricl chrcteristics, respectively. scling fctor of 0.93 ws pplied to 0.13 µm CMOS. The prmeters eing scled re the effective chnnel length, the density of ion implnttion for threshold voltge ( th ) djustment, nd the gte thickness. In order to minimize high field effects, the following dditionl techniques were implemented: shllow trench isoltion, sidewll spcer, silicide formtion, lightly doped drin implnttion, nd retrogrde well implnttion. The results show tht drin current (I D ) increses s the levels of interconnection increses. The importnt prmeters for NMOS nd PMOS were mesured. For NMOS, the gte length (L g ) is µm, th is , nd the gte thickness (T ox ) is nm. For PMOS, L g is µm, th is , nd T ox is nm. These prmeters were vlidted nd the device ws proven to e opertionl. Keywords: gte length, threshold voltge, gte thickness. Mnuscript received ; ccepted for puliction Introduction The size of CMOS trnsistor hs een shrinking drmticlly in less thn 40 yers time. Trnsistors with the size of 50 µm in the 1960s hve shrunk to less thn 0.18 µm in 2000s [1]. In this work, 0.14 µm CMOS ws simulted nd studied. The friction process ws simulted using the THEN module from the Silvco irtul Wfer F (WF) tools; wheres, the electricl chrcteristics were vlidted vi the TLS module. The 0.14 µm CMOS ws scled from n existing 0.13 µm CMOS [3]. Constnt field scling with scling fctor of 0.93 ws pplied to the following prmeters: the effective chnnel length (L g ), gte thickness (T ox ), nd threshold voltge ( th ) djustment implnttion [5]. s the chnnel length flls within the sumicron regimes, the performnce of the device my e susceptile to high field effects. Thus, in order to ensure proper opertion, the following techniques hve een implemented to minimize high field effects: shllow trench isoltion (STI), sidewll spcer, silicide formtion, lightly doped drin (LDD) implnttion, nd retrogrde well implnttion [5]. 2. Simultion process In order to simplify the simultion process, NMOS nd PMOS trnsistors were fricted seprtely. The friction processes for oth trnsistors were similr. The min differences lie within the types nd density of dopnt pplied to the sustrte. Initilly p-type single crystl silicon (Si) wfer ws prepred. Screen ws first grown on the 2006,. Lshkryov Institute of Semiconductor Physics, Ntionl cdemy of Sciences of Ukrine 40

2 Semiconductor Physics, Quntum Electronics & Optoelectronics, , N 2. P surfce of the sustrte. With the sustrte tilted y 7º nd rotting, high implnttion ws performed to crete p- nd n-wells for NMOS nd PMOS, respectively. The ojective of growing screen nd tilting the sustrte ws to minimize the chnneling effect; wheres the ojective of rotting the wfer ws to minimize the shdowing effect [1]. nneling nd drivein ws lter performed to repir the lttice dmge [1]. STI is employed to isolte the neighoring devices. Initilly, pd is grown vi dry oxidtion. Liquid plsm chemicl vpor (LPCD) technique is lter pplied to deposit silicon nitride Si 3 N 4. Pd cts s strin uffer to void crcks in the nitride film; wheres the nitride film cts s msk for silicon etching [1]. photoresist is then deposited nd pttern is developed using photolithogrphy. The nitride film nd pd is etched. The re protected under the Si 3 N 4 msk is known s the ctive region. fter stripping the photoresist lyer, the sustrte ws treted y rective ion etching (RIE) to form trenches. thin lyer of rrier ws grown in the trenches so s to lock impurities from diffusing into the sustrte during chemicl vpor (CD) process. Then tetrethyl-oxy-silne (TEOS) CD process ws pplied to fill the trenches with. The t the surfce of the sustrte ws removed using chemicl-ndmechnicl polishing (CMP) technique. STI ws completed fter ws performed nd Si 3 N 4 msk nd pd were etched. thin lyer of gte ws grown vi dry oxidtion. Then th djust implnttion ws performed; fter which the sustrte ws nneled. Susequently, lyer of polysilicon ws deposited on the sustrte. Then the sustrte ws etched nd nneled to form polysilicon gte. LDD ws implnted to suppress hot electron effect in sumicron MOSFET [1]. fter tht, CD ws pplied to deposit lyer of Si 3 N 4. Then the nitride film ws etched to form sidewll spcer. This ws followed y source/drin implnttion. nneling process ws performed to ctivte the dopnts. lyer of titnium ws deposited on the sustrte surfce. Rpid therml (RT) ws employed to form titnium silicide on the gte. Then the unrected titnium ws etched. Premetl dielectric (PMD) ws formed y depositing lyer of oron phosphor silicte glss (BPSG) on the sustrte surfce. PMD cts s n insultor for multilevel interconnection [2]. fter tht the is performed, BPSG is etched to form source/drin contcts. The first level of metlliztion is formed y depositing nd etching luminum on the contcts. The second level of interconnection cn e chieved y depositing nother lyer of BPSG on the surfce. This lyer is lso known s intermetl dielectric (IMD) [2]. The simultion process is completed when l is deposited onto the contcts formed y etching IMD. summry of the prmeters used in NMOS nd PMOS friction is shown in Tle 1. Tle 1. Prmeters of CMOS friction. Process step NMOS prmeters PMOS prmeters Silicon cm 3 oron cm 3 sustrte 100 orienttion oron Retrogrde well implnttion STI isoltion Gte th djust implnttion Polygte LDD implnttion Sidewll spcer Source/drin implnttion Silicide formtion PMD 0.02 µm screen cm 3 oron 100 ke implnt 7º tilt 30 min, 900 ºC 36 min, 970 ºC 0.01 µm pd 0.15 µm Si 3 N µm trench depth 15 min, 900 ºC 100 orienttion 0.02 µm screen cm 3 oron 100 ke implnt 7º tilt 100 min, 950 ºC 46 min, 970 ºC 0.01 µm pd 0.15 µm Si 3 N µm trench depth 15 min, 900 ºC µm gte µm gte cm cm 3 oron oron 5 ke implnt 5 ke implnt 0.25 µm polysilicon 26 min, 850 o C cm 3 phosphorous 23 ke implnt 20 min, 800 ºC 0.25 µm polysilicon 26 min, 850 ºC cm 3 oron 5 ke implnt 0.15 min, 850 ºC 0.12 µm Si 3 N µm Si 3 N cm 3 rsenic cm 3 phosphorous 25 ke implnt 55 min, 800, 850, 900 ºC 0.12 µm titnium 0.02 min, 1100 ºC RT 0.1 min, 910 ºC 20 min, 850 ºC cm 3 oron 10 ke implnt 45 min, 800 ºC 0.12 µm titnium 0.02 min, 1100 ºC RT 0.1 min, 910 ºC 20 min, 850 ºC Metl µm l 0.10 µm l IMD 15 min, 950 ºC 15 min, 950 ºC Metl µm l 0.30 µm l 2006,. Lshkryov Institute of Semiconductor Physics, Ntionl cdemy of Sciences of Ukrine 41

3 Semiconductor Physics, Quntum Electronics & Optoelectronics, , N 2. P Simultion results nd discussions Fig. 1 nd shows the complete cross-sections of NMOS nd PMOS, respectively. s clerly shown from the dopnt density distriutions, high- well implnttion hs resulted in the highest dopnt density concentrted t certin depth elow the sustrte surfce. s compred to conventionl well implnttion, in which the highest dopnt density lies t the surfce of the sustrte, such retrogrde wells re effective in minimizing punch through. With STI isoltion technique implemented in this simultion design, the ird s ek effect, which is commonly found prolem in locl oxidtion of silicon (LOCOS) technique, hs een successfully eliminted. Two sidewll spcers deposited t the polysilicon gte llows LDD implnttion to e performed. s cn e seen in Figs 1 nd, the lightly doped phosphorous (for NMOS) nd oron (for PMOS) right eneth the spcers llow reduction in the doping grdient etween drin/source nd the chnnel. This, in turn, lowers the electric field t the chnnel in the vicinity of the drin. lyer of titnium silicide is formed t the surfce of the polygte. The lyer of silicide, which hs much lower resistivity thn polysilicon is necessry to reduce power consumptions nd RC time dely for sumicron MOSFET locl interconnection. Some of the importnt prmeters such s th, T ox, nd L g re mesured nd extrcted from the TLS module. In order to vlidte the results, these prmeters re compred with the stndrd prmeters pulished y interntionl technology rodmp for semiconductor (ITRS) nd Berkeley predictive technology model (BPTM) [4]. Since only the stndrd prmeters for 70 nm, 0.10 µm, 0.13 µm, nd 0.18 µm CMOS cn e found s pulished, the polynomil regression technique (using MTLB tools) hs een pplied to chieve the required prmeters for 0.14 µm CMOS. Tle 2 shows comprison etween the prmeters derived from TLS nd the stndrd ones otined using the polynomil regression. ll the simulted prmeters for th, T ox, nd L g lie within the tolernce rnge of the prmeters otined through regression technique. Hence, it cn e concluded tht the results otined from the simultion process re vlid. The I D - D nd I D - g electricl chrcteristic curves re plotted using TLS simultor. Figs 2 nd show the NMOS I D - D reltionships efore nd fter metlliztion 2 is performed; wheres, Figs 3 nd show the NMOS I D - g reltionships efore nd fter metlliztion 2. Similrly, the I D - D reltionships for PMOS re shown in Figs 4 nd, respectively; wheres, PMOS I D - g reltionships re shown in Figs 5 nd, respectively. comprison etween efore nd fter second level interconnection is mde. The results re summrized in Tles 3 to 6. Fig µm NMOS (), PMOS (). Fig. 2. NMOS I D - D reltionship efore () nd fter () metlliztion ,. Lshkryov Institute of Semiconductor Physics, Ntionl cdemy of Sciences of Ukrine 42

4 Semiconductor Physics, Quntum Electronics & Optoelectronics, , N 2. P Fig. 3. NMOS I D - g reltionship efore () nd fter () metlliztion 2. Fig. 4. PMOS I D - D reltionship efore () nd fter () metlliztion 2. Fig. 5. PMOS I D - g reltionship efore () nd fter () metlliztion 2. It cn e oserved tht for oth NMOS nd PMOS the I D - D nd I D - g reltionships still retin fter the second lyer of metlliztion. This shows tht the level of interconnection does not ffect the electricl chrcteristics of the device. However, s the level of interconnection increses, the drin current (I D ) increses. Since the power consumption is directly proportionl to I D, n increse in the level of interconnection will give rise to power consumption. 2006,. Lshkryov Institute of Semiconductor Physics, Ntionl cdemy of Sciences of Ukrine 43

5 Semiconductor Physics, Quntum Electronics & Optoelectronics, , N 2. P Tle 2. Comprison etween simulted results nd stndrd prmeters for 0.14 µm sumicron CMOS. CMOS Prmeters TLS results Stndrd prmeters NMOS th ± 12.7% T ox nm ± 4% nm L g µm 0.14 ± 15% µm PMOS th ± 12.7% T ox nm ± 4% nm L g µm 0.14 ± 15% µm Tle 3. Comprison of I D efore nd fter metlliztion 2 in I D - D NMOS grph. g, D, I D efore level 2 I D fter level 2 Rte of increse in I D, % Tle 4. Comprison of I D efore nd fter metlliztion 2 in I D - g NMOS grph. g, D, I D efore level 2 I D fter level 2 Interconnection, Rte of increse in I D, % Tle 5. Comprison of I D efore nd fter metlliztion 2 in I D - D PMOS grph. g, D, I D efore level 2 I D fter level 2 Rte of increse in I D, % Tle 6. Comprison of I D efore nd fter metlliztion 2 in I D - g PMOS grph. g, D, I D efore level 2 I D fter level 2 Rte of increse in I D, % Conclusion With the implement of retrogrde well implnttion, STI, sidewll spcer, silicide formtion, nd LDD implnttion to help to minimize high field effects, the design of 0.14 µm sumicron CMOS hs een successfully simulted nd vlidted. The results show tht power consumption tends to increse fter the second metlliztion ws performed. References 1. H. Xio, Introduction to semiconductor mnufcturing technology, Prentice Hll, M. Quirk nd J. Serd, Semiconductor mnufcturing technology, Prentice Hll, Rosfriz t. Rdzli, Friction nd chrcteriztion of 0.13 micron device, M.Sc. Thesis, University Kengsn, Mlysi, S. Xiong nd J. Ding, Impct of prmeter vrition on future circuit performnce, technicl report. [Online] ville: ~jgding/ee241/. 5. C.K. Chen, C.L. Chen, P.M. Gouker, P.W. Wytt, D.R. Yost, J.. Burns,. Sunthrlingm, M. Fritze, nd C.L. Kest, Friction of self-ligned 90 nm fully depleted SOI CMOS SLOTFETs // IEEE Electron Device Lett. 22 (7), p (2001). 6. Y.. Ponomrev, P.. Stolk, C.J.J. Dchs, nd.h. Montree, 0.13 µm poly-sige gte CMOS technology for low-voltge mixed signl pplictions // IEEE Trns. Electron Devices 47 (7), p (2000). 7. H. Koike, H. Ohtsuk, F. Mtsuok, M. Kkumu, nd K. Meguchi, Process simplifiction in deep sumicron CMOS friction // IEEE/UCS/SEMI Interntionl Symposium Semiconductor Mnufcturing, (1995). 8. D. Prent, E. Bshm, Y. Dessouky, S. Gleixner, G. Young, E. llen, Improvements to microelectronic design nd friction course // IEEE Trns. Eduction 48 (3), p (2005). 2006,. Lshkryov Institute of Semiconductor Physics, Ntionl cdemy of Sciences of Ukrine 44