Interface Properties of La-silicate MOS Capacitors with Tungsten Carbide Gate Electrode for Scaled EOT

Transcription

1 ECS-PRiME 2012, Hawaii Interface Properties of MOS Capacitors with Tungsten Carbide Gate Electrode for Scaled EOT K. Tuokedaerhan a, R. Tan c, K. Kakushima b, P. Ahmet a,y. Kataoka b, A. Nishiyama b, N. Sugii b, K. Tsutsui b, K. Natori a, T. Hattori a, H. Iwai a a Frontier Research Center, Tokyo Institute of Technology, Japan b Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Japan c Faculty of Information Science and Engineering, Ningbo University, Ningbo, China 1

2 Out line of our work Introduction Process for tungsten carbide formation Tungsten carbide as a gate metal for Conclusion 2

3 for direct contact of High-k/Si La 2 O 3 + nsi + mo 2 La(SiO 4 ) n La-rich (k~20) small (s) n large Supply of oxygen atoms Si-rich (k~8) High dielectric constant (k= 8~20) ide band-gap (E g ~ 6.3 ev) 2nm 800 o C, 30min (k~16) T. Kawanago, IEEE Trans. ED, pp. xxx (2012) Charge pumping current [A] D it = 2 x [cm -2 /ev] 500 o C 700 o C 800 o C D it = 5 x [cm -2 /ev] D it = 1.6 x [cm -2 /ev] Frequency [Hz] Capacitance [µf/cm 2 ] FGA700 o C 30min 20 x 20µm 2 10kHz 100kHz 1MHz Gate Voltage [V] Capacitance [µf/cm 2 ] FGA800 o C 30min x 20µm 2 10kHz 100kHz 1MHz Gate Voltage [V] Direct contact of high-k/si can be achieved with formation ith high temperature annealing, D it can be as low as cm -2 /ev 3

4 Issues of for EOT scaling V fb (V) EOT (nm) FGA800 o C 30min D it (cm -2 ev -1 ) 1.0x x x x x x x EOT (nm) FGA800 o C 30min Scaling with Larger flat band voltage shift High interface state density 4

5 Possible mechanism for higher Dit K. Kakushima, et. al., SSE(2010) X X XX X X X X XX EOT scaling Si sub. Si-sub. Creation of defects Presumably due to the presence of grain boundaries in the metal layer T. Kawanago, IEEE Trans.ED, pp. 269 (2012) Suppression grain boundaries in metal layer might solve the scaling issues Metal with small grains or amorphous metal 5

6 Metal with small grains or amorphous metal Ta Si 10 C Ru Mo amorphous metal 70 small grain size (<10nm) XRD plan TEM M. E. Grubbs, Appl. Phys. Lett., (2010) Amorphous up to 1120 o C Complex deposition system (4 elements) Composition control (depth profile) K. Ohomori, IEDM, 409 (2008) Simple process (2 elements) Variability in grain size Our approach e attempt to use 2 C with grain size (<2nm) as metal gate electrodes 6

7 Purpose of this work Investigate interface property of high-k with tungsten carbide metal gate 7

8 Process for tungsten carbide formation Deposition methods of carbides 1. Sputtering from carbide alloy target H, Romanus, Thin solid Films 146, (2000) Carbon deficiency formation during annealing 2. Sputtering with CH 4 gas Hydrogen to produce carbon deficiency 3. Solid reaction of C and layers Interface reaction and grows grains multi-stacking of /C layers carbon tungsten carbon tungsten carbon tungsten Gate oxide Si sub. Deposition of several sets of carbon and tungsten layers Advantage annealing Carbide formation 1. Layered reaction to suppress excess growth of grain size 2. Content of carbon can be controlled 3. Tungsten carbide can be formed at low temperature 8

9 Tungsten carbide formation Intensity (Count) Sheet resistance (Ω/sq.) (100) (002) (101) (102) amorphous (110) GIXD 750 o C 2 C (103) (200) (112) (201) (004) (202) Grain size = 1.9nm 2 C (due to reaction of SiO 2 ) Annealing temperature ( o C) 10nm /C multi layers 18nm SiO 2 (400nm) Si sub. 750 o C Ѳ (deg) 2 C with small grain size can be obtained at 725 o C~825 o C 9

10 Sheet resistance (Ω/sq.) Tungsten carbide with excess carbon atoms :C=1:1 2 C with excess carbon atoms :C=1:0.5 Different Carbon ratio Annealing temperature ( o C) Excess supply of carbon atoms increases the sheet resistance Small 2 C grains in amorphous metal layer 10

11 Devices fabrication process in-situ Substrate SPM and HF cleaning La 2 O 3 deposition with graded thickness /C multi-stacking layer by RF sputtering Different Carbon ratio Gate patterning (RIE) :C=1:0.5 :C=1:0.8 :C=1:1 deposition (Ar:N 2 =9:1) by RF sputtering Si deposition (100nm) by RF sputtering Si C C Annealing C La 2 O 3 18 set 1 cycle Annealing in F.G ambient at 800 Si removal by TMAH Backside Al contact Si C FGA (3% H 2 ) at 420 o C for30min Measurement CV measurement Conductance measurement 11

12 Electrical characteristics with 2 C (:C=1:0.5) Capacitance [µf/cm 2 ] kHz 20x20µm 2 EOT~1.0nm Gate voltage [V] 2 C Capacitance [µf/cm 2 ] Ideal CV curve Gate voltage [V] 2 C ith 2 C Small hump in C-V Curve 12

13 Interface state density with 2 C (:C=1:0.5) V fb (V) EOT (nm) 2 C 1x10 12 D it (cm -2 ev -1 ) 1x EOT (nm) 2 C Interface state density was suppressed by 2 C gate electrode Scalable for small EOT 13

14 Impact of excess carbon atoms on D it D it (cm -2 ev -1 ) x10 11 F.G.A 800 o C 30min 9 C 8 :C=1:0.5 7 C 6 5 C 4 :C=1: :C=1:1 Different Carbon ratio 0 :C=1: :C=1:0.8 :C=1:1 EOT (nm) 18 set 1 cycle Interface state density was suppressed by excess carbon concentration ( D it < cm -2 ev -1 ) Scalable for small EOT 14

15 Effective mobility improvement with excess C atoms in 2 C layer µ eff (cm 2 /Vsec) :C=1:1 :C=1:0.5 EOT~0.75nm E eff (MV/cm) µ eff (cm 2 /Vsec) / 2 C//nFET L/=10µm/10µm :C=1: EOT (nm) Higher effective mobility of 165cm 2 /V.s with small EOT 0.63nm were achieved by using 2 C with excess C atoms 15

16 Possible explanation for small D it with 2 C X XX X X 2 C X X X 2 C with excess carbon X Si sub. Si sub. Si sub. Interface state density was suppressed by small 2 C grains in amorphous metal layer K. Kakushima, et. al., SSE(2010) Gate metal Gate metal X X X X X X D it EOT scaling Gate metal X X X Si sub. Increase in D it at small EOT can be considered as defects 16

17 Conclusions A novel stacked C/ process was introduced and formation of carbides were confirmed Interface state density was suppressed by 2 C gate electrode than by gate electrode Interface state density was suppressed by excess carbon concentration ( D it < cm -2 ev -1 ) Higher effective mobility of 165cm 2 /V.s with small EOT 0.63nm were achieved by using 2 C (:C=1:1) gate electrodes 17