Wolfspeed SiC and GaN Materials Catalog

Transcription

1 Wolfspeed SiC and GaN Materials Catalog

2 Wolfspeed SiC and GaN Materials Industry-Leading Portfolio, Innovation and Scale Wolfspeed is a fully integrated materials supplier with the largest and most diverse product portfolio serving our global customer base with a broad range of applications. We are the technology commercialization leader with the capacity and scale to bring large diameter wafers to the market in mass production volumes. Wolfspeed has long-proven expertise in SiC and GaN materials technology advancement with the focus and commitment to bring high-quality solution platforms across all applications. N-TYPE SiC Substrates HPSI High Purity Semi-insulating SiC Substrates SiC EPITAXY n-type and p-type Epitaxial Layers NITRIDE EPITAXY GaN, AlGaN, InGaN Epitaxial Layers APPLICATIONS SiC and GaN materials enable faster, smaller, lighter and more powerful electronic systems. Wolfspeed is committed to providing our customers with the materials needed to facilitate the rapid expansion and adoption of the technology within the industry. Our materials enable devices that power Renewable Energy, Base Stations & Telecom, Traction, Industrial Motor Control, Power Management and Automotive applications. RENEWABLE ENERGY BASE STATIONS TELECOM TRACTION INDUSTRIAL MOTOR CONTROL POWER MANAGEMENT AUTOMOTIVE 1

3 PHYSICAL PROPOPERTIES Polytype Supported Diameters Crystal structure Bandgap Thermal conductivity (n-type; ohm-cm) Thermal conductivity (HPSI) Lattice parameters Single-Crystal 4H 100mm & 150mm Hexagonal 3.26 ev a~4.2 W/cm 298 K c~3.7 W/cm 298 K a~4.9 W/cm 298 K c~3.9 W/cm 298 K a=3.073 Å c= Å Mohs hardness 9 DIMENSIONAL PROPERTIES, TERMINOLOGY, AND METHODS DIAMETER The linear dimension across the surface of a wafer. Measurement is performed manually with ANSI-certified digital calipers on each individual wafer. THICKNESS, CENTER POINT Measured with ANSI-certified non-contact tools at the center of each individual wafer. SURFACE ORIENTATION Denotes the orientation of the surface of a wafer with respect to a crystallographic plane within the lattice structure. In wafers cut intentionally off orientation, the direction of cut is parallel to the primary flat, away from the secondary flat. Measured with x-ray goniometer on a sample of one wafer per ingot in the center of the wafer. ORTHOGONAL MISORIENTATION In wafers cut intentionally off orientation, the angle between the projection of the normal vector to the wafers surface onto a {0001} plane and the projection on that plane of the nearest <1120> direction. 2

4 How to Order 0 = Standard MPD V = Very-Low MPD ( 5/cm2) U = Ultra-Low MPD ( 1/cm2) B = Low BPD ( 1500/cm2), MPD ( 1/cm2) F = 100mm (4 ) G = 150mm (6 ) C = R = 1E5 X = = None S = Standard SiC (<30um) T = Thick SiC ( 30um) G = GaN Epitaxy N = n-type T = HPSI W = Standard 4 = 4-H SiC P = Production R = Research 0 = On-Axis 4 = 4 Off-Axis C1 = 350um Thickness N = 500um Thickness w/ notch (150mm HPSI) Note: This digit only applicable to 150mm wafers. 2 = Double-side Polish, Si-Face CMP 6 = Double-side Polish, C-Face CMP SiC Epitaxy: 0 = No Epitaxy 1 = 1 Layer 2 = 2 Layer 3 = 3 Layer 4 = 4 Layer GaN Epitaxy: A = HEMT 25% Al E = HEMT > 25% Al I = Other HEMT 3

5 Our Products

6 n-type SiC Substrate PRODUCT DESCRIPTIONS The Materials Business Unit produces a wide assortment of n-type conductive SiC products ranging in wafer diameters up to 150mm. This material is manufactured upon a high-volume platform process that provides our customers the highest degree of material quality, supply assurance and economies of scale. Part Number Description W4NRF0X H-SiC, n-type, Research Grade, 100mm, On-Axis, ohm-cm, Standard MPD, 500um Thick, Double- Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NRF4C-U200 4H-SiC, n-type, Research Grade, 100mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, 350um Thick, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NPF4C-U200 4H-SiC, n-type, Production Grade, 100mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, 350um Thick, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NRF4C-B200 4H-SiC, n-type, Research Grade, 100mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, Low BPD 1500/cm2, 350um Thick, Double Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NPF4C-B200 4H-SiC, n-type, Production Grade, 100mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, Low BPD 1500/cm2, 350um Thick, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NRG4C-C1-V200 4H-SiC, n-type, Research Grade, 150mm, 4 Off-Axis, ohm-cm, Very Low MPD 5/cm2, 350um Thick w/ 47.5mm Flat, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NPG4C-C1-V200 4H-SiC, n-type, Production Grade, 150mm, 4 Off-Axis, ohm-cm, Very Low MPD 5/cm2, 350um Thick w/ 47.5mm Flat, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NRG4C-C1-U200 4H-SiC, n-type, Research Grade, 150mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, 350um Thick w/ 47.5mm Flat, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4NPG4C-C1-U200 4H-SiC, n-type, Production Grade, 150mm, 4 Off-Axis, ohm-cm, Ultra Low MPD 1/cm2, 350um Thick w/ 47.5mm Flat, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate *C-faced polished wafers and 150mm LBPD substrates available upon request, lead times dependent on volume and requirements FLAT LENGTH PRIMARY FLAT PRIMARY FLAT ORIENTATION SECONDARY FLAT Linear dimension of the flat measured with ANSI-certified digital calipers on a sample of one wafer per ingot (see Figure 1). The flat of the longest length on the wafer, oriented such that the chord is parallel with a specified low-index crystal plane. The primary flat is the {1010} plane with the flat face parallel to the <1120> direction. Measured with Laue back reflection technique. A flat of shorter length than the primary flat, whose position with respect to the primary flat identifies the face of the wafer. Not applicable to 150mm wafers. Wafer Diameter XXXXXX-XX Primary Flat Secondary Flat Figure 1. Diameter, primary and secondary flat locations and marking orientation, carbon face up for silicon face polished wafers SECONDARY FLAT ORIENTATION MARKING The secondary flat is the {11-20} plane with the flat face parallel to the <1010> direction. Measured with Laue back reflection technique. For silicon-face polished material, the carbon face of each individual wafer is laser-marked with OCR-compatible font, similar to definitions and characteristics in SEMI M12 (see Figure 1). For carbonface-polished material, the silicon face of each individual wafer is laser-marked (see Figure 2). Secondary Flat XXXXXX-XX Primary Flat Figure 2. Primary and secondary flat locations and marking orientation, silicon face up for carbon face polished wafers 5

7 PRODUCT SPECIFICATIONS 100mm Diameter n-type Substrates Diameter mm +0.0/-0.5 mm Thickness On-axis Off-axis Dopant Primary flat length Secondary flat length 500 μm ± 25 μm μm ± 25.0 μm Nitrogen 32.5 mm ± 2.0 mm 18.0 mm ± 2.0 mm Surface orientation On-axis {0001} ± 0.25 Off-axis 4.0 toward <1120> ± 0.5 Surface finish Back face optical polish, epi-face CMP Orthogonal misorientation ± 5.0 Primary flat orientation <1120> ± 5.0 Secondary flat orientation TTV Warp LTV (average, 1 cm2 site) 90.0 CW from primary ± 5.0, silicon face up 15 microns, full substrate 45 microns, full substrate 4 microns, full substrate Edge chips by diffuse lighting Production-grade Research-grade none permitted 0.5mm width and depth qty mm width and depth 150mm Diameter n-type Substrates Diameter mm ± 0.25 mm Thickness C1 specification Dopant Primary flat length Secondary flat length 350 μm ± 25 μm Nitrogen 47.5 mm ± 1.5 mm None Surface orientation 4.0 toward <11-20> ± 0.5 Surface finish Back face optical polish, epi-face CMP Orthogonal misorientation ± 5.0 Primary flat orientation Secondary flat orientation TTV <11-20> ± 5 N/A 10 μm Warp Production-grade Research-grade 40 μm 60 μm LTV (average, 1 cm2 site) Production-grade Research-grade 2 μm 4 μm Edge chips by diffuse lighting Production-grade Research-grade none permitted 0.5mm width and depth qty mm width and depth 6

8 High Purity Semi-Insulating SiC Substrate PRODUCT DESCRIPTIONS The Materials Business Unit produces a wide assortment of semi-insulating SiC products ranging in wafer diameters up to 150mm. Wolfspeed s High-Purity Semi-Insulating wafers are not vanadium-doped. Part Number Description W4TRF0R H-SiC, HPSI, Research Grade, 100mm, On-Axis, 1E5 ohm-cm, Standard MPD, 500um Thick, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4TPF0R H-SiC, HPSI, Production Grade, 100mm, On-Axis, 1E5 ohm-cm, Standard MPD, 500um Thick, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4TRG0R-N H-SiC, HPSI, Research Grade, 150mm, On-Axis, 1E5 ohm-cm, Standard MPD, 500um Thick w/ Notch, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate W4TPG0R-N H-SiC, HPSI, Production Grade, 150mm, On-Axis, 1E5 ohm-cm, Standard MPD, 500um Thick w/ Notch, Double-Sided Polish Si Face CMP Epi Ready, Bare Substrate FLAT LENGTH PRIMARY FLAT PRIMARY FLAT ORIENTATION SECONDARY FLAT SECONDARY FLAT ORIENTATION MARKING MM HPSI MARKING AND NOTCH: Linear dimension of the flat measured with ANSI-certified digital calipers on a sample of one wafer per ingot (see Figure 1). The flat of the longest length on the wafer, oriented such that the chord is parallel with a specified low-index crystal plane. The primary flat is the {1010} plane with the flat face parallel to the <1120> direction. Measured with Laue back reflection technique. A flat of shorter length than the primary flat, whose position with respect to the primary flat identifies the face of the wafer. Not applicable to 150mm wafers. The secondary flat is the {11-20} plane with the flat face parallel to the <1010> direction. Measured with Laue back reflection technique. For silicon-face polished material, the carbon face of each individual wafer is laser-marked with OCR-compatible font, similar to definitions and characteristics in SEMI M12 (see Figure 1). All 150mm HPSI products have a 1.0mm (+0.25, -0.00) notch depth with a <1120> ± 5.0 notch orientation. The laser markings are offset right when looking at the silicon face (see Figure 2). Secondary Flat Wafer Diameter XXXXXX-XX Primary Flat Bisector of notch Figure 1. Diameter, primary and secondary flat locations and marking orientation, carbon face up for silicon face polished wafers Figure 3. Notch location and marking orientation, carbon face up for silicon face polished 150mm HPSI wafers 7

9 PRODUCT SPECIFICATIONS 100mm Diameter Semi-Insulating Substrates Diameter Thickness Primary flat length Secondary flat length mm +0.0/-0.5 mm μm ± 25.0 μm 32.5 mm ± 2.0 mm 18.0 mm ± 2.0 mm Surface orientation {0001} ± 0.25 Surface finish Back face optical polish, epi-face CMP Orthogonal misorientation ± 5.0 Primary flat orientation <1120> ± 5.0 Secondary flat orientation TTV Warp LTV (average, 1 cm 2 site) 90.0 CW from primary ± 5.0, silicon face up 15 microns, full substrate 45 microns, full substrate 4 microns, full substrate Edge chips by diffuse lighting Production-grade Research-grade none permitted 0.5mm width and depth qty mm width and depth 150mm Diameter Semi-Insulating Substrates Diameter Thickness Notch Depth mm ± 0.25 mm 500 μm ± 25 μm 1.0 mm mm, mm Notch Orientation <1120> ± 5.0 Surface orientation {0001} ± 0.25 Surface finish Back face optical polish, epi-face CMP Orthogonal misorientation ± 5.0 TTV Warp LTV (average, 1 cm 2 site) < 15 for 150mm HPSI <60 μm 4 μm Edge chips by diffuse lighting Production-grade Research-grade none permitted 0.5mm width and depth qty mm width and depth 8

10 SiC Substrate SURFACE FINISH SPECIFICATIONS Attribute Production-Grade Research-Grade Edge chips/indents by diffuse lighting none permitted 0.5mm width and depth mm width & depth Cumulative area defects* Quantitative by 200X microscopic inspection Striations by diffuse lighting, 20 allowed 10% area 30% area 3 allowed 3 mm each 7 mm each Polytype areas by diffuse lighting* 5% area 20% area Area contamination (stains) by high intensity light none permitted none permitted Cracks by high-intensity light none permitted none permitted Hex plates by high-intensity light* cumulative area 10% cumulative area 30% Scratch length by Lasertec Confocal Microscope 150mm 150mm Notes: * Defect limits apply to entire wafer surface except for edge exclusion area, 3 mm for and mm substrates. 9

11 SURFACE FINISH DESCRIPTIONS (AREA) CONTAMINATION Any foreign matter on the surface in localized areas which is revealed under high-intensity (or diffuse) illumination as discolored, mottled, or cloudy appearance resulting from smudges, stains or water spots. CRACKS A fracture or cleavage of the wafer that extends from the front-side surface of the wafer to the back-side surface of the wafer. Cracks must exceed in length under high-intensity illumination in order to discriminate fracture lines from allowable crystalline striations. Fracture lines typically exhibit sharp, thin lines of propagation, which discriminate them from material striations. EDGE CHIPS Any edge anomalies (including wafer-saw exit marks) in excess of 1.0 mm in either radial depth or width. As viewed under diffuse illumination, edge chips are determined as unintentionally missing material from the edge of the wafer. EDGE EXCLUSION The outer annulus of the wafer is designated as wafer handling area and is excluded from surface finish criteria (such as scratches, pits, haze, contamination, craters, dimples, grooves, mounds, orange peel and saw marks). This annulus is 3mm for 100mm and 150mm substrates. HEX PLATE Hexagonal-shaped platelets on the surface of the wafer which appear silver in color to the unaided eye, under diffuse illumination. FOREIGN POLYTYPES (also referred to as Inclusions or Crystallites ) Regions of the wafer crystallography which are polycrystalline or of a different polytype material than the remainder of the wafer, such as 6H mixed in with a 4H type substrate. Foreign polytype regions frequently exhibit color changes or distinct boundary lines, and are judged in terms of area percent under diffuse illumination. SCRATCHES A scratch is defined as a singular cut or groove into the front-side wafer surface with a length-towidth ratio of greater than 5 to 1, and detected and classified by Lasertec SICA. STRIATIONS Striations in silicon carbide are defined as linear crystallographic defects extending down from the surface of the wafer which may or may not pass through the entire thickness of the wafer, and generally follow crystallographic planes over its length. TOTAL USABLE AREA A cumulative subtraction of all noted defect areas from the front-side wafer quality area within the edge exclusion zone. The remaining percent value indicates the proportion of the front-side surface to be free of all noted defects (does not include edge exclusion). 10

12 SiC Epitaxy PRODUCT DESCRIPTIONS Wolfspeed produces n-type and p-type SiC epitaxial layers on SiC substrates, and has the widest range of available layer thickness from sub-micron to >200µm. Unless noted otherwise on the product quotation, the epitaxial layer structure will meet or exceed the following specifications. Additional comments, terms and conditions may be found in the specification document. Substrate Orientation: SiC Epitaxy is available only for off-axis substrates Conductivity n-type p-type Dopant Nitrogen Aluminum Net doping density N D -N A N A -N D Silicon face 9E14 1E19/cm3 9E14 1E20/cm3 Carbon face 1E16 1E19/cm3 Not available Tolerance ±25% ±50% Thickness range Silicon face microns ±10% of selected thickness ±10% of selected thickness Thickness range Carbon face microns ±10% of selected thickness Not available PRODUCT SPECIFICATIONS Characteristics Maximum Acceptibility Limits Test Methods Defect Definitions (See pg. 11) Methodology (See pg. 11) 100.0mm 20 Large-point defects D mm 25 Scratches 5 lines <2x wafer diameter Diffuse Illumination D2 Backside cleanliness 95% clean D5 M1, M2 Edge chips See Substrate Specifications D6 M2 Epi defects 25/cm 2 Candela CS20 D7-D8 M3 Net doping See specification table Hg probe CV - M4 Thickness See specification table FTIR - M5 Note: 3mm edge exclusion for and 150.0mm 11

13 SiC Epiwafer DEFINITIONS CV MEASUREMENT POINTS (EPI DOPING): D1. LARGE-POINT DEFECTS Defects which exhibit a clear shape to the unassisted eye and are > 50 microns across. These features include spikes, adherent particles, chips and craters. Large point defects less than 3 mm apart count as one defect. D2. SCRATCHES Grooves or cuts below the surface plane of the wafer having a length-to-width ratio of greater than 5 to 1. Scratches are specified by the number of discrete scratches times the total length in fractional diameter. D5. BACKSIDE CLEANLINESS Verified by inspecting for a uniform color to the wafer backside. Note there is a darker region near the center of some higher-doped wafers. Back-side cleanliness specified as percent area clean. D6. EDGE CHIPS Areas where material has been unintentionally removed from the wafer. D7. EPITAXY DEFECTS The sum of discrete defect counts. These include 3C inclusions, comet tails, carrots, particles, pits, falldown, and silicon droplets. D8. CANDELA ACCURACY & DEFECT CLASSIFICATION Defect maps are provided only as representations of wafer quality. Defect classification, location, and count will not be absolutely accurate. Pt. x_mm y_mm FTIR POINTS (EPI THICKNESS): METHODOLOGY M1. 3 mm edge exclusion for and mm. M2. Inspection performed under diffuse illumination. M3. Candela CS20 M4. Net doping is determined as an average value of multiple points along radius opposite major flat using Hg probe CV. M5. Thickness is determined as an average value across the wafer using FTIR, or mass difference for layers <5um. Pt. x_mm y_mm Pt. x_mm y_mm

14 Nitride Epitaxy PRODUCT DESCRIPTIONS Wolfspeed produces GaN, Al x Ga 1-x N and In y Ga 1-y N epitaxial layers on SiC substrates. Unless noted otherwise on the product quotation, the epitaxial layer structure will meet or exceed the following specifications. Additional comments, terms and conditions may be found in the specification document. STRUCTURAL LAYER SPECIFICATIONS Nitride Epitaxial Layer Specifications Property Value or Range Precision Measurement Technique Substrate On-axis SiC (n-type or Semi-Insulating) - - Composition Al x InʸGa 1-x-y N, 0 x 0.4, 0 y 0.2, certain restrictions apply Δ x = ± 0.015, Δ y = ± 0.02 XRD peak splitting - mid-radius Thickness (2) μm to 10.0 μm GaN 0.2 nm to 1.0 μm AlN μm to 3.0 μm Al x In y Ga 1-x-y N 10.0 nm to nm SiN (Cap Layer) Average thickness within ± 15% of target thickness and uniformity <10%. (3) X-ray or white light interferometry GaN Crystallinity < 250 arcsec (3 μm layer on SiC substrate (5)) - Al 0.25 Ga 0.75 N < 500 arcsec (3 μm layer on SiC substrate (5)) - XRD (0006) FWHM (center point) XRD (0006) FWHM (center point) (4) Visible Defects < 50 / cm 2 - Differential interference microscopy at 50x in cross pattern with 5 mm edge exclusion Dislocation Density <1E9 / cm 2, total - X-ray/AFM 13

15 ELECTRICAL LAYER SPECIFICATIONS Nitride Epitaxial Layer Specifications Property Value or Range Precision Measurement Technique Dopant type n-type (Si) p-type (Mg) - - Carrier concentration (undoped, substrate dependent) < 1E16 cm -3, n-type - Hg probe CV Carrier concentration (n-type, Si doped) 1E16 to 2E19 cm -3 ± 50% Hg probe CV (wafer center, room temperature) Carrier concentration (p-type, Mg doped) 5E16 to 5E17 cm -3 (activated) ± 50% Hg probe CV (wafer center, room temperature) Carrier Concentration of HEMT structure >8E12 cm 2 (25% Al / 25 nm AlGaN) - Contactless non-destructive carrier concentration Mobility of HEMT structure μalgan 1600 cm 2 V -1 s -1 (25.0% Al / 25.0 nm AlGaN) - Contactless non-destructive mobility Sheet resistivity < 5% uniformity - Contactless non-destructive sheet resistivity 1. Certain additional restrictions may apply and will be presented on the product quotation. 2. Range given for undoped layers. Maximum achievable thickness for doped layers or heterostructures will be reduced. 3. Precision specification applies only to layers 0.01 μm thick. Uniformity = (100 x standard deviation / mean). 4. Please specify epitaxy structure details upon submission of RFQ (i.e. thickness, doping, composition, for each layer) 14

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