Contact Resistance Study on. Polycrystalline Silicon Thin-Film. Solar Cells on Glass. Lei Shi. Masters Thesis

Transcription

1 Contact Resistance Study on Polycrystalline Silicon Thin-Film Solar Cells on Glass by Lei Shi Masters Thesis School of Photovoltaic and Renewable Energy Engineering The University of New South Wales Sydney, Australia June 2008

2 i Originality Statement I hereby declare that this submission is my own work and to the best of my knowledge it contains no materials previously published or written by another person, or substantial proportions of material which have been accepted for the award of any other degree or diploma at UNSW or any other educational institution, except where due acknowledgement is made in the thesis. Any contribution made to the research by others, with whom I have worked at UNSW or elsewhere, is explicitly acknowledged in the thesis. I also declare that the intellectual content of this thesis is the product of my own work, except to the extent that assistance from others in the project's design and conception or in style, presentation and linguistic expression is acknowledged. Lei Shi Sydney, 18 December 2007

3 ii In memory of my beloved grandfather, fatherly concern for me whenever, and wherever.

4 iii The fabrication of ohmic contacts is still more of an art than a science E. H. Rhoderick and R. H. Williams, 1988

5 iv Abstract Thin-film solar cells are widely recognised to have the potential to compete with fossil fuels in the electricity market due to their low cost per peak Watt. The Thin-Film Group at the University of New South Wales (UNSW) is engaged in developing polycrystalline silicon (poly-si) thin-film solar cells on glass using e-beam evaporation technology. We believe our solar cells have the potential of significantly lowering the manufacturing cost compared to conventional, PECVD-fabricated thin-film solar cells. After years of materials research, the focus of the Group s work is now moving to the metallisation of evaporated solar cells. Minimising various kinds of losses is the main challenge of the cell metallisation procedure, within which the contact resistance is always a big issue. In this thesis, the contact resistance of aluminium contacts on poly-si thin-film solar cells on glass is investigated. To the best of the author s knowledge, this is the first ever contact resistance investigation of Al contacts on evaporated poly-si material for photovoltaic applications. Various transmission line models (TLM) are employed to measure the contact resistance. An improved TLM model is developed to increase the measurement precision and, simultaneously, to simplify the TLM pattern fabrication process. In order to accommodate the particular requirements of poly-si coated glass substrates, a TLM pattern fabrication process using photolithography is established. Furthermore, a Kelvin sense tester is set up to ensure an accurate measurement of the contact resistance. After establishment of the TLM technique at UNSW, it is successfully tested on singlecrystalline silicon wafer samples. The thermal annealing process of the contacts is also optimised. Then, the general behaviour of Al contacts on uniformly doped poly-si films (i.e., no p-n junction) is investigated using the verified TLM technique. The long-term stability of the contacts is also studied. This is followed by an investigation of the contact resistance of the back surface field and emitter layers of different types of poly-si thin-film solar cells. Finally, a novel contact resistance measurement model is proposed that is believed to be able to overcome the measurement bottleneck of the transmission line models.

6 v Acknowledgements This postgraduate work would not have been successful without the assistance and support from some people. First of all I would like to extend my gratitude to my supervisor, Prof. Armin Aberle, for his academic and financial support. He is the person who guided me to the great family of solar energy enthusiasts and consequently changed my professional career. The two years of research under your supervision were tough, but rewarding. Not only my knowledge and skills but also my views on life and values improved dramatically during this period. Thanks Armin, you gave me a turning point of my life. A huge Thank you! goes to Dr. Tim Walsh who acted as my co-supervisor and mentor during his PhD candidature in 2005 and Armin gave me an opportunity to do research, and Tim trained me to become a qualified researcher. Tim, I wish you a successful career in China and I believe our friendship will last for good. I would like to express my appreciation to Daniel Inns who offered several high-quality samples, which led to a breakthrough of my research. My appreciation also goes to Oliver Kunz for the valuable help and discussion of my work, as well as proof reading parts of this thesis. It has been a fantastic experience of working with him. I thank our ingenious undergraduate PV student, Dawei (David) Di, for assisting me in some lab work. I am honoured to know you and work with you, David. Bernhard Vogl is my dear office mate. We are always the last guys to leave the office everyday and it is always a pleasure to have someone staying up together for work and for helpful and interesting talk of semiconductor, research, life, and other things. Lots of thanks go to my other colleagues in the PV Centre: Dr. Nicholas Shaw and Mark Silver for offering me a part-time job; Nancy Sharopeam for kind encouragements when I was in low spirits; Ivan Perez-Wurfl for photomask design; The list is almost endless. All in all, it was a dreamlike experience to work with these first-class people in this first-class institute.

7 vi Finally and most importantly, a special thanks to my family for their love and constant self-giving support.

8 vii Contents Originality Statement...i Abstract...iv Acknowledgements...v 1 Introduction 1.1 Thin-Film Solar Cells Poly-Si Thin-Film Solar Cells on Glass at UNSW EVA Solar Cell ALICIA Solar Cell ALICE Solar Cell Key Processes and Glass Aims of this Thesis Contact resistance and the transmission line models 2.1 Metal-semiconductor contacts (MS contacts) Ohmic contacts and contact resistance Metal typically used Lumped series resistance of solar cells The transmission line models Variable gap transmission line model (TLM) Improved variable gap TLM The contact end resistance measurement Ladder network transmission line models Circular transmission line model (CTLM) Practical requirements of the transmission line models Sample fabrication and characterisation 3.1 Sample cleaning Aluminium evaporation Photolithography and pattern fabrication Photolithography procedures Photomask design Pattern fabrication Process optimisation and the results Plasma etching...48

9 viii 3.5 Wet-chemical etching with coloured HF Sheet resistance profiling Spectroscopic measurements Dark I-V measurements Four-point probe tester Curve tracer Kelvin sense measurement setup Contact resistance results on sc-si wafer samples 4.1 Motivation Sample preparation Results Boron-diffused sc-si surfaces Phosphorus-diffused sc-si surfaces The influence of baking time and temperature Discussion and conclusions Contact resistance results on uniformly doped poly-si films on glass 5.1 Motivation Sample preparation Results Boron-doped Si films Phosphorus-doped Si films with and without SiO x interlayer Discussion Conclusions Contact resistance results on poly-si thin-film diodes on glass 6.1 Motivation Contacts to the back surface field layer of PLASMA cells Sample preparation Results Contacts to the back surface field layer of EVA cells Contacts to the back surface field layer of ALICIA cells Contacts to the emitter layer of PLASMA cells Contacts to the emitter layer of EVA cells Conclusions A novel contact resistance measurement model 7.1 Motivation...120

10 ix 7.2 Fabrication and underlying theory Structure Suggested fabrication procedure Theory Discussion and conclusions Summary and conclusions 8.1 Summary and conclusions Possible future work List of symbols List of references List of original contributions List of publications...141

11 1 Introduction 1 1 Introduction 1.1 Thin-Film Solar Cells The world is becoming increasingly aware of the significant problems associated with global warming, such as more frequent and more intense heat waves, cold waves, floods, droughts and storms. A major contribution to global warming comes from greenhouse gas emissions such as carbon dioxide (CO 2 ), 45% of which are from electricity production [IPCC 2006]. Nuclear energy is powerful, but it is also well known for its risks and hence does not seem to be suitable for worldwide use. As an alternative, people have been developing various kinds of carbon free, sustainable and renewable energies such as wind power, hydropower, biomass, geothermal, solar thermal and photovoltaic energy. Although most of these energies are still more expensive than fossil fuel, it is deemed that they will make a large contribution to the worldwide energy supply in the medium to long term, reducing the dependence on fossil fuels. While not being the cheapest renewable technology at present, photovoltaic (PV) energy has a number of advantages such as its excellent scalability, noiseless and lowmaintenance operation, and temporal peak load matching (especially in countries with heavy use of air conditioners). The currently prevailing commercial PV technology is based on approximately 200 m thick single- or multicrystalline silicon (c-si) wafers. However, practically, only a small fraction of the 200 m thick silicon wafers is used to convert the sunlight into electricity, representing a significant waste of expensive silicon material. Moreover, the rapid growth of the PV industry in the last decade has led to a shortage of silicon wafer feedstock material, which currently limits the growth of the PV industry as well as the popularisation of solar energy. The oil price has risen sharply in recent years and now exceeds US$ 80 per barrel. Somewhat ironically, however, the relative increase of the price of silicon feedstock has been even higher in recent years, driven by the surging

12 1 Introduction 2 demand from the PV sector. Unfortunately, being limited by the sawing loss and other technical problems, it is not possible to simply cut the silicon ingots into thinner and thinner wafers. As a consequence, a less material intensive technology - a thin-film technology - seems necessary for a large-scale application of PV. Thin-film solar cells, which are sometimes referred to as second-generation solar cells, have two main advantages over conventional silicon wafer-based solar cells. Firstly, the amount of raw materials used in thin-film cells is significantly reduced. As mentioned above, most energy-rich solar photons are absorbed within a few microns from the illuminated silicon surface. Thus, an efficient c-si solar cell can be made from less than 10 m thick films. By adding a light-trapping scheme that increases the optical pathlength of the photons through the semiconductor (resulting in a higher probability of being absorbed), the required material thickness can be further reduced to less than 3 m. This represents a massive reduction of the Si consumption of over 99% compared to conventional 200 m thick wafers (which have a wafering-related kerf loss of about 200 m). Therefore, moving towards thin-film PV cell production will allow a much greater increase in manufacturing capacity compared to installing new assembly lines for Si wafer cells. The second advantage is a streamlined production process due to the fact that thin-film cells can be deposited onto large-area superstrates (such as glass). They can be scribed into many long subcells and these can be interconnected using various techniques. This provides more freedom with regards to shape, size, and output voltage of the module, while at the same time minimises the costs associated with cell interconnection. In first generation (wafer-based) solar cell technology, encapsulation by a strong front-side glass cover is usually indispensable to protect the cells from the environment (humidity, dust, hail, wind), while this step can be omitted in thin-film fabrication process. To sum up, the above two factors result in one single advantage: greatly reduced manufacturing cost ($/Watt) of PV modules. Various materials are currently used for thin-film solar cells. Some of them are briefly reviewed.

13 1 Introduction 3 Amorphous silicon (a-si:h) is the first commercialised thin-film solar cell technology. The silicon film is deposited at low temperature ( C) using plasma-enhanced chemical vapor deposition (PECVD). Amorphous Si PV modules are cheap but they have low stabilised efficiency of about 6% for large areas. One reason behind this low stable efficiency is the light-induced degradation effect (Staebler-Wronski effect) [Staebler & Wronski 1977]. Researchers have developed an amorphous/microcrystalline silicon (a-si:h/c-si) tandem structure [Keppner 1999] to obtain higher stable efficiency. PV modules based on this tandem structure now have about 8-10% stable efficiency [Tawada 2003] Both these materials are deposited on large areas by PECVD and require a full-area Transparent Conductive Oxide (TCO) contact on the illuminated surface for lateral current transport due to their high sheet resistance. A compound semiconductor for PV applications is cadmium telluride (CdTe) which has around 7-9% commercial PV efficiency [First Solar 2007]. CdTe uses toxic materials and may harm the environment, which is a limiting factor for worldwide use. Another remarkable compound semiconductor for thin-film solar cells is copper indium gallium diselenide (CIGS) and its related materials (such as CIS). Although 19.5% efficiency has been obtained for small laboratory cells, its potential for mass production is doubted due to the use of a very rare element, indium. There is increasing interest in polycrystalline silicon (pc-si) thin-film material. Compared to alternative materials, there are several advantages of using polycrystalline silicon: silicon is comparatively cheap, non-toxic, abundant and widely used in the semiconductor industry. Poly-Si PV cells do not degrade and TCO is not necessary for contacting. The latter factor makes local contact schemes possible, which significantly enlarges the scope for the methods of metallising and interconnecting the cells. CSG Solar (formerly Pacific Solar), a spin-off company of UNSW, has developed and commercialized a poly-si on glass thin-film PV technology that is based on solid phase crystallisation (SPC) of a PECVD-deposited a-si precursor diode. This technology (CSG) uses borosilicate glass superstrates and achieves mini-module efficiencies of 10.4% [Keevers 2007].

14 1 Introduction Poly-Si Thin-Film Solar Cells on Glass at UNSW At the University of New South Wales (UNSW), research is underway aiming at the realisation of efficient, low-cost poly-si thin-film solar cells on glass. The scientific innovation of the work lies in the use of novel methods for glass texturing, Si diode formation, and solar cell metallisation and interconnection. Si deposition is performed by PECVD (industry standard, but low deposition rate) and e-beam evaporation. Vacuum evaporation has a number of advantages over the PECVD technique such as high deposition rate (up to 1 m/min), good Si source material usage, and avoidance of toxic gases. Six different thin-film solar cell structures are investigated in parallel. Their fabrication sequence is illustrated in Figure 1.1. Figure 1.1: Process sequence of the six poly-si on glass thin-film solar cells presently under development at UNSW. All cells are designed for the superstrate configuration, i.e., the sunlight enters the cells through the glass [Aberle 2006a]. Three of these six thin-film solar cells - EVA, ALICE and ALICIA - have been investigated in the course of this thesis and hence their fabrication sequence is explained in more detail in the following Sections. EVA and ALICIA are fabricated using a non-uhv e-beam evaporation technology, whereas ALICE can be fabricated by e-beam evaporation or PECVD.

15 1 Introduction EVA Solar Cell EVA stands for solid phase crystallisation of EVAporated Si. With the exception of the Si deposition process, EVA cells are similar to the PLASMA cells shown in Figure 1.1. The EVA cell structure is glass/sin/n + /p - (or n - )/p +. The a-si is evaporated at low temperature (~200 C) in a non-uhv environment (deposition pressure ~10-7 Torr, no hydrogen added) and then crystallised ex-situ by atmospheric-pressure SPC in a N 2 -purged tube furnace at 600 C for 24 h [Aberle 2006a]. The grain size is about 1-2 m. Table 1.1 lists the typical design features of EVA solar cells. Table 1.1: Typical design parameters of EVA cells [Aberle 2006a]. Parameter Details Glass 3 mm (planar or textured, borosilicate) AR coating SiN (~75 nm, n ~2.0) Emitter n + (~150 nm, up to cm -3 P, ~200 /) Base p (~1500 nm, ~ cm -3 B) BSF p + (~150 nm, up to cm -3 B, ~400 /) RTA C or C Hydrogenation ~15 about 600 C, remote plasma Metal Al (500 nm, front & rear) ALICIA Solar Cell ALICIA stands for ALuminium-Induced Crystallisation Ion-Assisted deposition [Aberle 2005]. The idea is to epitaxially grow the crystalline absorber layer on a hydrogen-terminated seed layer made on glass by Aluminium Induced Crystallisation (AIC). Because AIC seed layers have a large grain size of m, it seems possible that ALICIA cells have better crystal quality than EVA and PLASMA cells. The epitaxial growth is via Ion-Assisted Deposition (IAD). This vacuum evaporation method is capable of high-rate pc-si growth at low temperatures of ~600 C. From sample heating to unloading, epitaxial growth of the Si cell typically takes less than 30 min. Owing to the contradictory demand of the temperature between H-terminated seed layer surface and good epitaxial growth, an elaborate heating procedure was developed at UNSW [Inns 2005]. Figure 1.2 schematically shows an ALICIA solar cell.

16 1 Introduction 6 Figure 1.2: Schematic of an ALICIA pc-si thin-film solar cell on glass. Grain size and layer thickness are not to scale [Aberle 2005] ALICE Solar Cell ALICE stands for ALuminium-Induced Crystallisation solid-phase Epitaxy [Aberle 2006b]. The idea is to deposit the absorber onto an H-terminated AIC seed layer at very low temperature (~200 C) as amorphous material, and then to crystallise the amorphous material in a thermal anneal at elevated temperature ( C). Due to the presence of the seed layer, the crystallisation process is Solid Phase Epitaxy (SPE) rather than SPC. The a-si precursor diode can be deposited by either e-beam evaporation or PECVD [Aberle 2006]. Table 1.2 summarizes the design features of p + nn + ALICIA cells. Table 1.2: Typical parameters of p + nn + ALICIA cells [Aberle 2006b]. Parameter Details Glass 3 mm (planar or textured, borosilicate) AR coating SiN (~75 nm, n ~2.0) Emitter p + (~150 nm, ~ cm -3 Al+B, ~1000 /) Base n (~1500 nm, ~ cm -3 P) BSF n + (~100 nm, ~ cm -3 P, ~1000 /) RTA 1000 C or C Hydrogenation ~15 about 620 C, remote plasma Metal Al (500 nm, front & rear)

17 1 Introduction Key Processes and Glass The key processes and the glass used for the fabrication of the above three solar cells are summarised below: Glass All the solar cells investigated at UNSW have the glass superstrate configuration. Glass is a standard component of today s PV modules. It has lots of advantages, but the disadvantage is the limited thermal stability. To minimise this drawback, Borofloat33 glass is used due to good thermal stability at around 600 C. Glass texture A novel glass texturing method has been developed at UNSW, which is termed Aluminium Induced Texture (AIT) [Chuangsuwanich 2004]. It creates a random array of sub-micron sized dimples at the glass surface. The AIT process starts with the deposition of a thin (~100 nm) aluminium film onto the glass, followed by thermal annealing at about 600 C for 30 minutes and subsequent wet-chemical etching of the Al and the reaction products. The AIT process is performed on the silicon-facing surface of the glass. SiN After texturing, a silicon nitride layer (typical thickness 75 nm) is deposited onto the silicon-facing side of the glass via either PECVD or RF sputtering. This SiN film acts both as an antireflection coating in the final device and a barrier layer against contaminants from the glass during silicon material manufacturing. Seed Layer A crucial component of ALICIA and ALICE cells is a large-grained seed layer made on glass by the AIC (Aluminium-Induced Crystallisation) process of a-si. This technology was pioneered at UNSW in 1998 [Nast 1998] and is a prerequisite for good SPE material quality. It is realised by evaporation of an Al film onto an intrinsic a-si layer (formed by PECVD or sputtering), followed by annealing at around 500 C for 12 hours in an atmospheric-pressure tube furnace and removal of the excess Al and Si. Apart from the AIC method, a seed layer can also be formed by SPC of a heavily-doped a-si layer at about 600 C for 24 h. The heavily doped a-si layer (n + or p + )

18 1 Introduction 8 is formed by e-beam evaporation or PECVD. The solar cells grown on SPC seed layers are termed SOPHE (crystallised via SPE) or SOPHIA (epitaxial growth via IAD), see Figure 1.1. Note that in the case of ALICIA and SOPHIA, the base layer and the BSF layer of the cells are immediately grown as crystalline silicon ( epitaxial Si growth ), whereas in the case of ALICE and SOPHE, these layers are deposited in amorphous form and then crystallised in a subsequent furnace anneal. Post-deposition Treatments After silicon material deposition, all types of solar cells are treated by RTA and hydrogenation processes. The RTA process uses a lamp-based system that rapidly heats the samples to the desired temperature ( C), maintains the peak temperature for a certain time (in the range of 1 s to 8 min), and then lowers the sample temperature in a controlled manner to values below 200 C. Hydrogenation is performed at a sample temperature in the range of C, using a remote plasma tool (modified LPCVD machine). The RTA process reduces the density of point defects and activates the dopants, while hydrogenation helps to passivate many of the remaining defects (grain boundary defects, extended defects, point defects). The open-circuit voltage approximately doubles due to hydrogenation treatment [Terry 2006]. Metallisation All thin-film poly-si solar cells at UNSW are metallised with aluminium only. A novel metallisation method for poly-si thin-film cells on glass has been developed at UNSW. It is based on two interdigitated comb-like grid structures (see Figure 1.3) and is referred to as the SAMPL method ( Self-Aligned Maskless PhotoLithography ) [Walsh 2005]. A comb-like aluminium electrode is formed on the rear (air-side/bsf) surface of the cell using Al evaporation and photolithographic structuring. Using the rear metal (air-side electrode) as a mask, the Si film which is not covered by Al is removed by plasma etching (PE). PE is not an isotropic etching process and hence a sloped Si side wall is formed along each edge of the etched region. Next, positive photoresist is applied to the rear surface. After pre-bake, it is then exposed to collimated UV light, incident from the substrate side of the device, such that the remaining silicon film acts as a self-aligned photomask, and only the photoresist on the plasma etched region is exposed. After development and post bake, a layer of Al (~500 nm) is deposited over the rear surface of the device and then a photoresist lift-off process is performed,

19 1 Introduction 9 leaving Al only in the etched region, acting as the glass-side electrode. Figure 1.4 shows a FIB image of a metallised PLASMA solar cell. Si side wall Air side Al contact Glass side Al contact Figure 1.3: Schematic of an interdigitated poly-si thin-film solar cell on a glass [Aberle 2006b]. Figure 1.4: Cross-sectional FIB image of the BSF and emitter contacts of a metallised PLASMA solar cell. Most of the effort at UNSW over the past several years has been devoted to improving the open-circuit voltage of the cells. However, the focus of the work is now moving to the metallisation of the solar cells. Minimising various kinds of losses is the main challenge of the cell metallisation procedure, within which the contact resistance is always a big issue. 1.3 Aims of this Thesis The aims of this thesis are to measure and optimise the contact resistance of the front and rear contacts of EVA, ALICIA and PLASMA cells. To the best of the author s knowledge, the present thesis represents the first ever contact resistance characterisation study performed on poly-si PV materials made from evaporated a-si. The first task of the thesis is the establishment of a reliable and accurate measurement technique for the contact resistance of metal/silicon contacts.

20 1 Introduction 10 The established method is then applied to heavily doped SPC seed layers so as to investigate the general behaviour of Al contacts to evaporated poly-si. Then it follows the study of the contact resistance on the back surface field (BSF) layer of completed solar cells. The next task then is the investigation of emitter contacts. The effect of thermal annealing ( baking ) of the contacts and other surface treatments are also investigated on both SPC seed layers and completed diodes. For these tasks, several different test structures are tried to gain a better understanding of the strengths and weaknesses of each structure. Afterwards, a new measurement structure is to be proposed which is able to overcome the weaknesses of the other tested structures. Finally, process recommendations are to be established for the realisation of ohmic contacts with low contact resistance on doped poly-si materials.

21 2 Contact resistance and the transmission line models 11 2 Contact resistance and the transmission line models Ohmic contacts are indispensable for metallising photovoltaic devices including poly-si thin-film solar cells. The contact resistance is used to quantitatively evaluate the ohmic property, while the transmission line models are used to measure the contact resistance. The aim of this Chapter is to lay out the relevant theories to better facilitate understanding of the experimental results presented in the subsequent chapters. A temperature of 300 K is assumed in all discussions if not stated otherwise. The silicon refers to singlecrystalline silicon. 2.1 Metal-semiconductor contacts (MS contacts) A highly conductive material (e.g. metal) is indispensable for extracting current from the bulk of the semiconductor to external circuits without significant resistive losses. When a metal and a semiconductor are brought into intimate contact, a potential barrier arises which is well-known as the Schottky barrier [Sze 1969, Yu 1969, Rhoderick & Williams 1988]. If the Fermi levels E F of the semiconductor and the metal differ, which is usually the case, electrons flow from the material with larger E F to that with lower E F, creating a space charge region. The means that the conduction band E C and the valence band E V of the semiconductor are bent at the interface of the contact. The electron transfer process continues until a constant Fermi level has established itself across the entire sample, and forms the built-in potential barrier. The entire process is analogous to the formation of a one-sided abrupt junction (p + -n or n + -p). Both Schottky barrier and built-in potential impede the transport of electrons and holes between the semiconductor and the metal. Figure 2.1(a) and (b) illustrate the theoretical barrier formation of Al/n-Si contacts. Due to the different Fermi levels (work functions), a depletion region is formed after the two materials are brought into contact.

22 2 Contact resistance and the transmission line models 12 Vacuum level Vacuum level q m q m q s E C E F q Bn q bi q s E C E F E Fi E Fi Aluminium n-type Silicon E V Aluminium n-type Silicon E V (a) (b) Figure 2.1: Band diagram of Al and n-type Si. m is the work function of Al. s is the work function of Si. (a) Before contact formation. Note that q m > q s ; (b) Band diagram of the Al/n-Si contact structure. The Schottky barrier q Bn, the built-in potential q bi and the Fermi level of intrinsic Si E Fi are also shown. [Sze 1969] The band diagram in Figure 2.1(b) represents a rectifying contact, which is unwanted for photovoltaic devices. Ohmic contacts are usually achieved via the quantum mechanical effect of tunnelling. 2.2 Ohmic contacts and contact resistance The width of the depletion region depends on the doping level of the semiconductor. More precisely, it depends inversely on the square root of the doping concentration at the surface. And the tunnelling probability increases exponentially with decreasing deletion region width. In brief, in order to have an ohmic contact with low tunnelling resistance, the surface doping density needs to be as high as possible. However, owing to other restraining factors from device design such as poor blue response, the surface doping level cannot be increased arbitrarily. Therefore, knowing the contact resistance is important in terms of device design optimisation. An ohmic contact is indispensable for most semiconductor devices. It is defined as a metal-semiconductor contact that has a negligible junction resistance relative to the total resistance of the semiconductor device. The contact resistance, also known as the specific contact resistance or contact resistivity, c (cm 2 ), is an important

23 2 Contact resistance and the transmission line models 13 figure-of-merit for evaluating the quality of ohmic contacts. It is a resistance value that is normalised to the area. Mathematically it is defined as the reciprocal of the derivative of the current density with respect to the voltage across the interface, at V = 0: 2.1 c dj dv 1 V 0 J is the applied current density. More detailed expressions of c are given below. Figure 2.2 depicts the three main current transport mechanisms of metal-silicon contacts. When the doping density is low (< ~ cm -3 ), the depletion region is too wide (> 400 Å) to enable tunnelling. Therefore, only electrons with high energy have a chance to overcome the barrier. The process is called thermionic emission (TE). The contact resistance is heavily Schottky barrier height dependent. When the doping is extremely high (> ~ cm -3 ), the depletion region is narrow enough (< 40 Å) for low-energy electrons to tunnel through it rather than travelling over it. The contact resistance is heavily dependent on the doping level. This process is called field emission (FE). High doping concentration may also slightly lower the Schottky barrier height [Rhoderick & Williams 1988]. At intermediate doping levels, both current transport mechanisms occur simultaneously. This situation is referred to as thermionic-field emission (TFE). In the TFE process, the electrons have an energy above the conduction band edge but enter the metal through tunnelling rather than thermionic emission. The contact resistance is determined by both the Schottky barrier height and the surface doping density. E Fm q Bn e (a) V F E C E Fs B c exp (kt >> E 00 ) kt

24 2 Contact resistance and the transmission line models 14 E Fm e (b) V F E C E Fs B c exp (kt E 00 ) E00 N D coth kt E Fm e (c) V F E Fs Ec B c exp (kt << E 00 ) N D Figure 2.2: Band diagrams of MS contacts under forward bias, for an n-type semiconductor: (a) thermionic emission, (b) thermionic-field emission, (c) field emission. The functional dependence of the specific contact resistance for each mechanism is also listed on the right-hand side, whereby B is the barrier height for the majority carriers in the semiconductor (i.e., B = Bn in the case shown here). [Yu 1970]. Both TFE and FE are responsible for ohmic contacts. In UNSW s thin-film solar cells, TFE is believed to be the dominant current transport mechanism. In Figure 2.2 (right), E 00 is an important characteristic energy and related to the tunnelling probability. The ratio kt/ E 00 is a measure of the relative importance of the thermionic process in relation to the tunnelling process. E 00 is defined as [Yu 1970]: 2.2 E 00 qh 4 N D * m where q is the electronic charge, h is Planck s constant, N D is the donor concentration, is the permittivity of the semiconductor, and m * is the effective mass of the tunnelling electron which depends on the surface crystal orientations, doping type and doping density. Figure 2.3 depicts the theoretical contact resistance vs. doping concentration for a range of Schottky barrier heights. For large barrier heights, the contact resistance drops steeply with increasing doping. All curves converge for doping levels above cm -3 confirming that the barrier height becomes less important in the high doping region.

25 2 Contact resistance and the transmission line models 15 Figure 2.3: Numerically calculated specific contact resistance R c on (a) n-type and (b) p-type <100> Si surface for various barrier heights (in ev) at room temperature. The effective mass m* is a function of doping density. (After Kg & Liu 1990) 2.3 Metal typically used Aluminium is the most commonly used metal for forming electrodes in the IC industry as well as the PV industry due to its low cost, high conductivity, good stability at room temperature, etc. Moreover, it is especially suitable for forming ohmic contacts as it is a good oxide absorber during thermal annealing of Al/Si contacts. One problem for achieving ultra-low contact resistance (< 10-6 cm 2 ) is the elimination of the oxide film that normally exists at Al/Si interfaces, even after an HF dip. When annealing Al/Si contacts at moderate temperature (~ C), aluminium atoms react with silicon oxides to enable fresh Al atoms to diffuse through the aluminium oxide and reach the silicon interface to form intimate Al/Si contacts [Neamen 2003]. This process will be further explained and discussed in Section 4.4. All UNSW s thin-film solar cells on glass are metallised with aluminium only. The metal sheet resistance is found to be around 0.1 / for a typical 500 nm thick Al layer

26 2 Contact resistance and the transmission line models 16 evaporated at a background pressure of around 10-5 Torr. 2.4 Lumped series resistance of solar cells The lumped series resistance, R s, is the figure-of-merit for evaluating the metallisation quality. In the case of solar cells, R s depends on a number of parameters, including the emitter sheet resistance, the bulk resistance, the metal finger/busbar resistance and the metal/semiconductor contact resistances of the two electrodes. In conventional 1-Sun solar cells, the power loss associated with the contact resistances of the front and rear contacts is usually insignificant compared to other sources of power loss, especially when the back metallisation is a full-area contact. However, contact resistance becomes very important if a low surface doping level or a point-contact metallisation scheme is applied. For a thin-film solar cell, light trapping is of particular importance, which usually makes a full-area back contact unacceptable. Moreover, the emitters of the thin-film solar cells developed by our group at UNSW are metallised laterally along the exposed sidewalls (see Section 1.2.4). Due to the thinness of the emitter, the emitter contact area is very small. Therefore, a contact resistance study is indispensable to optimise the metallisation scheme of our thin-film cells. Figure 2.4 plots the fractional power loss of a typical EVA cell due to the emitter contact resistance against the metal finger width. The curves are generated using the equations and parameters listed in Table 2.1. The bus bar and the air-side (BSF) contact resistance are not accounted. The total fractional power loss is the sum of each power loss. By taking the derivative of the sum expression to zero, the minimum power loss (y axis) is found with respect to the varied metal finger width and contact resistance. Table 2.1: The equations and parameters used to plot Figure 2.4. S is the distance between the middle points of the neighbouring metal fingers (BSF or emitter). It is optimised for each W F value in Figure 2.4 [Green 2006].. Factional power loss due to resistive BSF metal fingers p rbf R sheetmb J V mp mp S W F Current density and voltage at max power point: J mp = 15 ma/cm 2

27 2 Contact resistance and the transmission line models 17 Fractional power loss due to resistive emitter metal fingers Fractional power loss due to shading by emitter fingers p ref p sf W F S 2 R sheetme J V mp mp S W F V mp = 380 mv Sheet resistance of metal fingers: For BSF, R sheetmb = 83 m/ For Emitter, R sheetme = 36 m/ Factional power loss due to contact resistance p cf J c V mp mp S W F Sheet resistance of BSF and emitter layers: Fractional power loss due to lateral current flow in resistive BSF layer Fractional power loss due to lateral current flow in resistive emitter layer p p Bl El R 12 sheetb R 12 sheete J V J V mp mp mp mp S S 2 2 For BSF, R sheetb = 800 / For Emitter, R sheete = 300 / Specific contact resistance: c = varied Metal finger width: W F = varied (BSF = emitter) As can be seen in Figure 2.4, the power loss due to poor contact resistance may reach 10% in a typical EVA solar cell. Low contact resistance gives more flexibility for optimising other parameters, such as the metal finger width. For the case of Figure 2.4, a specific contact resistance of below 10-4 cm 2 is believed to be sufficiently low. Figure 2.4: Fractional power loss of a typical EVA cell due to the contact resistance and the metal finger width of glass-side electrode in a bifacial interdigitated scheme.

28 2 Contact resistance and the transmission line models The transmission line models The cross bridge Kelvin resistor [Proctor 1983], the contact end resistor [Chern & Oldham 1984] and the transmission line model [Burger 1969] are most commonly used to determine the contact resistance on planar devices. In this thesis, the transmission line model (TLM) is chosen due to its good accuracy and simplicity. Moreover, the TLM also includes the contact end resistance measurement which will be discussed later in this section. All models can only be applied to ohmic contacts because the contact resistance of Schottky contacts depends on the current density. Furthermore, the contacts are required to be uniform across the investigated area. TLM can be further categorized into three different structures. They are variable gap TLM, ladder network TLM and circular TLM. Each one has specific advantages and disadvantages with respect to pattern fabrication, measurement, data analysis. However, the results obtained by any of these models should be identical if they are correctly applied. All three models are tested, and used in the course of this thesis. No matter what model is used, the central concept remains the same which is the so-called current transfer length, L T (cm), as illustrated in Figure 2.5. When contacting a planar device, the current does not flow uniformly into the contact. Assuming equipotential metal contact, the decay of the voltage underneath the contact, arising from the semiconductor resistance and the contact resistance is approximately exponential rather than linear [Meier & Schroder, 1984]. Similarly, the voltage increases approximately exponentially when current flows out of the contact. These mean most current flows into or out of the contact at the contact edges. This conclusion comes from the circuit model which is presented later. The core contribution of the transfer length concept is that the contact resistance is equivalent to the resistance of an additional length of semiconductor sheet. This equivalent length is the current transfer length. It is a characteristic distance over which the current transfers from the metal contact pad to the semiconductor sheet or vice versa. In other words, it assumes that the current flows only in the semiconductor sheet underneath the metal before it reaches L T. Therefore, the specific (i.e., area-normalised) contact resistance, c (cm 2 ), can be obtained from measuring the transfer length, L T,

29 2 Contact resistance and the transmission line models 19 and the semiconductor sheet resistance, R sheet (/) [Meier & Schroder 1984]: 2.3 c R sheet L 2 T This equation will be derived in Section L Metal L T L T I Semiconductor Figure 2.5: Current flow paths under an electrically long contact (L > L T ). (After Meier & Schroder, 1984). It is noted that L T is just a characteristic parameter arising from the circuit model to be discussed below. Practically, there is still current flowing into the contact after the transfer length if the contact is longer than L T. Three different TLM structures exist based on this concept, as discussed below Variable gap transmission line model (TLM) The original TLM structure, also known as the variable gap structure, is shown in Figure 2.6(a). The fabrication and operating principle of the variable gap structure is as follows: Several metal bars are deposited and photolithographically patterned on a semiconductor sample, whereby the spacing between adjacent metal bars is variable. A mesa etch step is then performed by means of plasma etching to define the active area of the semiconductor sample (the gap between the metal bars and the edge of the active area must be minimised). The details of the fabrication process are described in Chapter 3. Then, an I-V curve is measured between every two adjacent contacts. The total

30 2 Contact resistance and the transmission line models 20 resistance between two adjacent contact bars consists of the resistance of the semiconductor material (R semi ) and the contact resistance of two contacts (R c ), as shown in Figure 2.6(b): 2.4 Rtotal Rsemi 2 Rc Then the measured voltages (the current is constant for all the I-V measurements) are plotted versus the spacing of the neighbouring contact bars, giving a straight line using the least square fit. See Figure 2.6(c). The transfer length L T and the semiconductor sheet resistance R sheet are obtained from the x intercept and the slope of the fitted straight line, respectively. The detailed mathematical model will be derived later in this section. The y axis intercept corresponds to zero contact spacing and hence is 2 times the contact resistance (not area-normalised). The specific contact resistance c (cm 2 ) is then obtained from the L T and R sheet as given by Equation 2.3. At least two I-V measurements are required in order to fit a straight line. Extra measurements will increase the measurement accuracy. A/V A/V Z L d (a) R c R semi (b) R c (c) (d) Figure 2.6: Variable gap TLM (a) top view of original structure; (b) a simple model of R total (cross-sectional view); (c) TLM characteristic curve; (d) circuit model of R c (the components are explained in the text). The mathematical model for the conventional TLM is based on the resistor network shown in Figure 2.6(d). The current in the semiconductor enters the contact at its leading edge which is at point 0 and exits the semiconductor via the metal contact with

31 2 Contact resistance and the transmission line models 21 a length of L and a width of Z. Assuming that R 1 (each of the vertical resistors in the graph) is the contact resistance (not area-normalised) and R 2 is the resistance of a fixed length of semiconductor material, it follows [Zeghbroeck 2007]: 2.5 R 1 c Z x R 2 R sheet Z x R 3 is the resistance of a fixed length of metal and close to zero, combining Kirchoff's laws and Equation 2.5, one obtains the following relations [Zeghbroeck 2007]: I( x) Rsheet x V ( x x) V ( x) V ( R2 ) Z V ( x) Z x I ( x x) I( x) I( R1 ) c Thus, a set of differential equations can be constructed: dv I( x) R dx Z di V ( x) Z dx c sheet The negative marks indicate the decay of the voltage and the current. Combining Equations 2.8 and 2.9 gives: 2 d I I( x) R 2.10 sheet 0 2 dx c Equation 2.10 is a second-order homogeneous linear differential equation whose general solution is: x 2x I( x) c1e c2e The characteristic roots are: ,2 R sheet c

32 2 Contact resistance and the transmission line models 22 The current transfer length L T is defined as , 2 L T Note that Equation 2.3 is just the transform of the positive root of Equation Two boundary conditions are needed to define the constants c 1,2 in Equation 2.11: R sheet c 2.14 I( 0) I 0 I ( L) 0, where L is the length of the contact. Solving Equation 2.10 and utilising the transformations between the potential functions and the hyperbolic functions, we obtain: 2.15 I( x) I 0 L x sinh( ) LT L sinh( ) L T Then the expression of V(x) can be obtained by substituting Equation 2.15 into Equation 2.8: 2.16 V ( x) I 0 L T R Z sheet L x cosh( ) LT L sinh( ) L T The total resistance arises from the contact resistance: 2.17 R c V (0) I(0) L T R Z sheet coth( L L T ) R c Z sheet L coth( L T ) Using Equation 2.4, the full expression for the I-V characteristic of the TLM is:

33 2 Contact resistance and the transmission line models 23 Rsheet L 2.18 V I [ d 2 LT coth( )], Z L T where d is the spacing between two adjacent contact bars. The expression for R c can be simplified for two limiting cases: If the length of the contact is large enough (electrically long, L>>L T ) as shown in Figure 2.5, one obtains: 2.19 R c R c Z sheet L T R Z sheet L T c Z L > 2L T is sufficient to reduce the error to below 4%. The equation indicates that the contact resistance does NOT drop with the increasing contact length. The effective contact area is Z L T. Similarly, the I-V expression 2.18 can also be simplified: Rsheet 2.20 V I ( d 2LT ) Z If the length of the contact is electrically short (L << L T ), one obtains: 2.21 R c c L Z L < 0.4L T is sufficient to ensure an error of below 5%. The equation indicates that the contact resistance drops with increasing contact length. The effective contact area is Z L. In this case, the contact is equivalent to a full-area contact. Practically, for solar cell applications, L (the width of the metal contact) is always at least several tens of times longer than L T. Therefore, one can not simply obtain the specific contact resistance by using Equation 2.21, because the contacts are usually not full-area contacts. However, the author has found that TLM is often misused in this way in practice. Generally, Equation 2.19 is used for solar cell applications.

34 2 Contact resistance and the transmission line models Improved variable gap TLM Conventional TLM pattern fabrication requires a mesa etch step which demands a precise alignment during photolithography step to minimise the spacing between the contacts and the active layer edges (see Figure 2.6(a)). In order to minimise the measurement error arising from the non-uniformity of the sheet resistance, the TLM pattern is usually fabricated in a small area. Therefore, the contacts are usually too small to uniformly distribute a large current. Owing to the above two disadvantages, an improved variable gap TLM structure is developed in the course of this thesis as shown in Figure 2.7. Figure 2.7: Top view of the improved variable gap TLM structure; the darker area is the contact, lighter area is the semiconductor The improved structure has a similar theory but modifies the original TLM in the following way: Two large metal pads are added at the ends to supply the current so that the current is more uniformly distributed and a larger current can be applied. The voltage is again measured between neighbouring metal bars. The mesa etch defines an area that is narrower than the width Z of the metal bars so that the error arising from the spacing between the ends of the metal bars and the edges of the active area is eliminated (mesa etching does not affect the metal and the buried semiconductor layer). As the width of the active semiconductor layer can be designed mush smaller than Z, no precise alignment is needed when mask the area from being mesa etched during the photolithography step (lighter area in Figure 2.7). Therefore, the fabrication process is significantly simplified. The semiconductor underneath the metal which is outside the active area does not affect the measurement providing that the metal sheet resistance is negligible. The improved model is also compatible with the conventional measurement. The details of the fabrication process are described in chapter 3.

35 2 Contact resistance and the transmission line models 25 The mathematical model for the improved variable gap structure (Figure 2.6(b)) is slightly different from the conventional one but very similar to the improved ladder network structure which is described in Section The contact end resistance measurement The R sheet used to determine the contact resistance is, strictly speaking, the sheet resistance directly under the contact. The transmission line models assume that the sheet resistance of the semiconductor under and outside the contact is identical. However, exceptions can occur when sintering or alloying the contacts, leading to metal-semiconductor reactions. As a result, the sheet resistance underneath the contact may differ from that in the metal-free regions [Reeves & Harrison 1982]. Therefore, a so-called contact end resistance (R E ) measurement has to be conducted to obtain the sheet resistance value under the contact. Most TLM structures are compatible with such a measurement, which is schematically shown in Figure 2.8. Figure 2.8: Experimental methods for contact end resistance measurement. (After Reeves & Harrison 1982) The contact end resistance (R E ) can be measured via either of the two following ways [Reeves & Harrison 1982]:

36 2 Contact resistance and the transmission line models V R E I R E ( R1 R2 R3 ) 2 However, if the contact resistance R c is much small than the total resistance between two contacts, Equation 2.22 is preferred. The relation between R E and R c is given by: Rc L 2.24 cosh( ) R L E T R c can be yielded by the intercept of the characteristic curve shown in Figure 2.6(c). Thus the transfer length L T can be found and the specific contact resistance c can be obtained by: 2.25 R E c 1 L L T Z sinh( L T ) Then the modified sheet resistance under the contact R SK is given by: c 2.26 RSK 2 L T Reeves and Harrison (1982) reported that significant sheet resistance alteration only occurs when sintering contacts on lowly doped silicon. Low-temperature annealing of the contacts on heavily doped silicon does not cause significant reaction of the contact interface. The annealing temperature for almost all contacts in the course of this thesis is below 300 C which was found to negligibly change the sheet resistance under the contact, both theoretically and experimentally.

37 2 Contact resistance and the transmission line models Ladder network transmission line models A. Conventional structure The key feature of the ladder network is that the spacing between neighbouring contact bars is constant. The conventional structure is shown in Figure 2.9. A constant current is supplied via two contact pads at the ends. Then the voltage is measured between one large contact pad and each of the small contact bars. During the measurement, the spacing between two terminals is variable so that this structure becomes equivalent to the variable gap TLM structure. The resulting voltage versus spacing curve has a slope that is also identical to the characteristic curve of variable gap structure. However, the width of the contact bars must be narrower than the transfer length so that no significant error builds up when moving from left to right in Figure 2.9. Fundamentally, this technique is always accompanied with errors and is not suitable for samples with small transfer length. V A Z L d Figure 2.9: Top view of the conventional ladder network structure. (After Mak 1989) B. Improved structure An improved structure, proposed by Meier and Schroder (1984), is shown in Figure 2.10(a). It is mathematically similar to the improved variable gap TLM (Figure 2.7) but different to the conventional structure in operation principle. The transfer length is obtained via I-V measurements between contact pads a and b, whereas the sheet resistance is obtained via I-V measurements using pads b and c.

38 2 Contact resistance and the transmission line models 28 (a) (b) Figure 2.10: (a) top view of the improved Ladder network structure; (b) circuit model. (After Meier and Schroder 1984) The corresponding resistor network is shown in Figure 2.10(b). The mathematical model is similar to that of the conventional variable gap TLM structure. The difference is that the current flow into the contact at L/2 and flow out at L/2. L is the contact length. Therefore, the boundary conditions in Equation 2.14 change to the following: L 2.27 I ( ) I 0 2 L 2 I( ) I 0 Assuming zero sheet resistance of the metal (i.e., R 3 = 0 in Figure 2.10b), one obtains the I-V characteristics [Meier and Schroder 1984]: ni 0Rsheet L 2.28 V ab d 2LT tanh( ), Z 2LT where n is the number of gaps between pads a and b. The contact resistance is accumulated over n gaps to improve the precision. R sheet is obtained from I-V measurements via pads b and c:

39 2 Contact resistance and the transmission line models R sheet V I bc Z S As mentioned in Section 2.5.2, the I-V expression of the improved variable gap TLM is similar to Equation The only difference is that d and Rsheet are obtained via fitting of the characteristic curve. And n is omitted as the spacing between the neighbouring contacts is variable. Equation 2.28 can be further reduced if L/2L t > 2 (with error < 4%): ni 0Rsheet 2.30 Vab ( d 2LT ) Z This equation is very similar to the simplified I-V expression of conventional variable gap structure (Equation 2.20). The improved ladder network model significantly simplifies the measurement and analysis process because no curve fitting is required, but demands a relatively rigorous photolithography process as the number of metal bars involved is usually more than several tens and the spacing must be strictly constant. Moreover, the resistance of the semiconductor sheet between pad b and c must be much larger than the corresponding contact resistance, and the sheet resistance uniformity must be superb across the entire active area so that R sheet between pads b and c can be used to represent R sheet between pad a and b. Due to these restrictions, this technique is convenient but not as reliable as the variable gap TLM given the available equipments in the course of this thesis. Therefore, the ladder network TLM was only used at the beginning of this thesis work and was later abandoned Circular transmission line model (CTLM) Marlow and Das (1982) proposed the circular TLM structure shown in Figure It is similar to the variable gap TLM but uses a circular structure. This clever change saves the mesa etch step because the active semiconductor area is surrounded by the metal

40 2 Contact resistance and the transmission line models 30 contact, which dramatically simplifies the fabrication process. By passing a constant current from the large metal pad to each of the isolated contact circles, the voltage drop over each semiconductor ring can be measured. Then a curve of voltage against spacing can be plotted. The transfer length and the sheet resistance of the semiconductor are obtained by using Equation 2.31 to fit the voltage curve (least square non-linear fitting, see Figure Figure 2.11: Top view of the circular TLM structure. The grey area is the metal and the white ring-like area is the exposed semiconductor. I R r sheet V [ln( ) LT ( )] 2 r d r r d, where r is the radius of the outer circle of the semiconductor ring and d is the width of the ring (current pathlength between the outer contact pad and inner contact circle). Note that Equation 2.31 is a simplified one and only valid when r-d is 4 times greater than L T [Marlow & Das 1982], which is usually the case in practice. It can be further reduced to Equation 2.20 (conventional variable gap TLM) with 2r = Z, if r >> d. The error caused by this linear approximation is experimentally investigated in Figure 2.12 and Table 2.2, where the results yielded from non-linear fitting (solid lines) and the linear fitting (dashed lines) are compared.

41 2 Contact resistance and the transmission line models 31 voltage (mv) voltage_measured non-linear fit linear fit y = x R 2 = spacing (µm) (a) voltage (mv) voltage_measured non-linear fit linear fit 4 2 y = x R 2 = spacing (µm) (b) Figure 2.12: Linear (dashed lines) and non-linear (solid lines) fitting of the CTLM data measured from on a sc-si wafer with p + surface. (a) Larger error; (b) Smaller error Table 2.2: Comparison of results obtained from linear and non-linear fitting of CTLM data with different d/r ratio. Curve Fitting d / r R sheet (/) L T (μm) c (cm 2 ) Error Linear (a) 14.5% % Non-linear (a) 14.5% NA Linear (b) 9% % Non-linear (b) 9% NA Practically, non-linear curve fitting is adopted due to the following two factors: i) it is not wise to make CTLM patterns fulfilling the condition of r >> d owing to the restrictions of the available photolithography technique and large lateral variations in the sheet resistance; ii) the mathematical modelling of non-linear fitting is substantially facilitated by resorting to numerical methods such as Excel.

42 2 Contact resistance and the transmission line models 32 In the course of this thesis, the CTLM was used most, followed by the improved variable gap structure. The improved ladder network structure was only used in the initial stages of the research until its the structural unreliability was understood. As discussed in Section 2.5.4, a constant spacing between the metal bars is difficult to achieve with the equipment available for this research Practical requirements of the transmission line models The main difficulty of measuring a small contact resistance (R c ) on a substrate with high sheet resistance lies in the fact that R c is usually much smaller than the resistance arising from the semiconductor sheet (R semi ) if TLM technique is employed. It is a task similar to looking for a needle in a haystack. In order to distinct the needle (R c ), the only two solutions are to either make the needle as large as the haystack (R semi ) or to make the haystack as small as the needle. Usually, the latter solution is more realistic. Equation 2.4 explains this contact resistance measurement guideline in a mathematical way: 2.32 Rtotal Rsemi 2 Rc R total is easy to obtain. However, R c is usually so small that it can be easily smeared by R semi. Theoretically, the spacing d between neighbouring contact bars does not influence the measurement. However, practically, this parameter can be the dominant factor of measurement reliability because no material is absolutely uniform in lateral. From the viewpoint of device design, it is not realistic to arbitrarily decrease the sheet resistance. Therefore, in order to reliably measure the specific contact resistance, the spacing must be kept as small as possible. To do this, a good photolithography process is essential. This is discussed in the next Chapter.

43 3 Sample fabrication and characterisation 33 3 Sample fabrication and characterisation 3.1 Sample cleaning Piranha solution is used to clean the silicon sample surface by mixing 1 volumetric unit of 98% sulphuric acid (H 2 SO 4 ) and 1 volumetric unit of 30% hydrogen peroxide (H 2 O 2 ). The mixing process is exothermic and heats the resultant solution to about 120 C. The reaction of the above two liquids can be viewed as the energetically favourable dehydration of hydrogen peroxide to form hydronium ions, bisulphate ions, and, transiently, atomic oxygen [Wikipedia 2007]: 3.1 H SO H O H O HSO O The final mixture removes most organic matter as it is a strong oxidizer, and metal particles as well due to its high acidity. It also hydroxylates the silicon surface (adds OH groups), making it extremely hydrophilic. Therefore, the sample is typically dipped in 5% hydrofluoric acid (HF) to make the surface hydrophobic. The chemical reaction equation is shown below. After the HF dip, the dangling bonds of the silicon atoms at the surface are passivated by hydrogen atoms. Therefore, the surface is hydrophobic. For the formation of metal contacts, the silicon cleaning process is usually immediately followed by metal evaporation to minimize the chance of surface contamination and oxidization. Within less than one hour (maximum time for handling and preparing for metallization), less than 7 Å of native oxide grows on the Si surface, which does not harm the contact properties [SNF 2007]. 3.2 SiO2 4HF SiF4 2H 2O

44 3 Sample fabrication and characterisation Aluminium evaporation This is the key step of metallization. Aluminium deposition is accomplished in a vacuum chamber via resistive evaporation, whereby a large current is passed through a tungsten boat loaded with aluminum filaments. The process is performed in vacuum because this allows vapor particles to travel directly to the target object, where they condense back to the solid state. The lower the base pressure, the lower is the rate for Al atoms to be oxidized before they reach the sample, hence the better the contact quality. However, achieving high-vacuum conditions (< 10-6 Torr) is very time-consuming with the equipment available for this thesis work. The base pressure generally used in this thesis is therefore 10-5 Torr, which gives fairly good contact resistance and metal sheet resistance. 3.3 Photolithography and pattern fabrication In order to measure specific contact resistances of below 10-4 cm 2 on a substrate with 1000 /sq sheet resistance, the measurement patterns must be fabricated as small as possible. Therefore, a good-quality photomask and good pattern transfer are the most important prerequisites for accurate contact resistance measurements Photolithography procedures Photolithography is the key step for fabricating contact resistance measurement patterns. Its basic principle is using a photosensitive and etchant resistive material (resist) to selectively protect the substrate material by using a photomask. Subsequently, the unprotected/exposed area of the substrate material is removed by the etchant. As a consequence, the patterns on the photomask are accurately transferred to the substrate material after photoresist stripping. Each photolithography process transfers one layer of the patterns. Alignment is usually necessary when transferring multiple layers of the patterns. Modern IC fabrication typically requires several tens of layers. The process procedures are as follows (also see Figure 3.1):

45 3 Sample fabrication and characterisation 35 Sample cleaning Adhesion promotion (Photo)Resist coating Inspection Prebake Alignment Exposure Post-exposure bake Development Measurement and inspection Postbake The steps in italic are optional. Figure 3.1: Routine procedures of photolithography.

46 3 Sample fabrication and characterisation 36 Sample cleaning: The surface of the Si sample is piranha (or oxygen plasma) cleaned to get rid of organics and other foreign particles which may increase the surface roughness or create observable defects after spinning the resist. Acetone and isopropanol clean is performed prior to the piranha clean in order to strip the photoresist if the sample is found unqualified after resist coating step. Adhesion promotion: Resists typically do not adhere well to untreated Si surfaces and Si-containing materials such as silicon dioxide and silicon nitride. To ensure proper adhesion, the wafer surfaces are treated prior to resist coating, whereas this step is omitted when coating resists on aluminium due to excellent adhesion. Resist coating: Resist is typically comprised of organic polymers applied from a solution. It is typically photosensitive, hence also called photoresist. Photoresist is usually deposited by spinning at several thousands rpm and forms a thin film (typically m) of solid resist. The high resist film thickness homogeneity of the resist as well as the short coating times makes spin coating the most-applied resist coating technique in the microelectronics industry. However, in case of non-rotation-symmetric substrates, the resist forms a pronounced edge bead near the substrate edges due to the strong air turbulences. Some regions of such samples might not be coated at all. Photoresists can also be applied by spray coating and dip coating [Levinson 2004]. The spray coating technique works with all arbitrary sized and shaped substrates, even with three-dimensional bodies. Substrates with pronounced surface roughness are also easy to be spray-coated. However, the roughness is relatively high and the attained edge bead coverage is not satisfactory. Dip coating applies to large-scaled and arbitrary-shaped substrates. Its thickness uniformity changes over the dimension of the substrate. All sides of the substrate are coated, which may be an advantage or disadvantage. The only coating technique used in this thesis is spin coating, despite the large number of non-rotation-symmetric substrates being used in this thesis. Inspection: Check by bare eye if there are any defects/contaminations. In the case of small non-rotation-symmetric substrates, care has to be taken to ensure that most of the

47 3 Sample fabrication and characterisation 37 surface area is coated. If the spin coating fails, restart the whole process (including the sample cleaning step). Prebake: The photoresist is liquid right after the resist coating step and will easily stain and stick to the contact photomask during the exposure step. Its density is also insufficient to support wet-chemical processing and may create many problems such as bubbling. A bake is therefore indispensable for densifying the resist film, driving off residual solvent and promoting adhesion. Alignment: When transferring multiple pattern layers, good alignment ensures the new patterns are placed at the correct position on top of the preceding layers within allowable tolerances. Detailed alignment techniques will be discussed in Section Exposure: A mercury lamp is installed in the mask aligner to provide a broadband UV/near-UV spectrum (Figure 3.2) and is well matched to the photoresists used (Figure 3.3 and Figure 3.4). Positive photoresists become soluble after exposure and can be removed by a suitable solution, while negative photoresist behaves oppositely. Post-exposure bake: This optional step drives additional chemical reactions or the diffusion of components within the resist. Figure 3.2: Hg light without optical selective filters contains g- (wavelength 436 nm), h- (405 nm) and i-line (365 nm), with an i-line intensity of ~40% of the total emission between 440 and 360 nm [Microchemicals 2007].

48 3 Sample fabrication and characterisation 38 Figure 3.3: Absorption spectra of negative photoresists ma-n400 and ma-n1400. The negative photoresist used in this thesis is ma-n400, which has very similar properties as the ma-n400 [Rohm & Haas 2007]. Figure 3.4: Absorption spectrum of positive photoresist S1813, which has very similar properties as the S1818 photoresist [Microresist tech. 2007]. Development: This is a wet-chemical step by which resist is removed depending upon whether it has been made soluble by the exposure step. Measurement and inspection: This operation is for determining if the resist features on the substrates are sized correctly, properly overlay preceding patterns, and are sufficiently free from defects. Although this is an optional step in industry, it is always necessary for lab-scale processing. Failed samples have to be re-processed, starting with the cleaning step. Postbake: This is another optional process. Postbake is used to crosslink the photoresist molecules, drive out volatile organic materials and water in order to (i) preserve the vacuum integrity of the etch equipment and (ii) to further densify the resist film. The temperature is much higher than that of the prebake.

49 3 Sample fabrication and characterisation Photomask design It goes almost without saying that a high-quality photomask plays the most important role in photolithographic processes. Several photomasks were designed in the course of this thesis. The best one is presented and discussed in this section. The whole design consists of two layers, metal layer and mesa layer. The metal patterns are first fabricated via the metal layer mask. Then the mesa layer mask is used to define the active area of each pattern on the substrate. (Remark: A mesa etch is not required for the CTLM structure). Figure 3.5 gives an overview of one cell of the two-layer design drawn with the program LAZI CAD. The main feature of the design is that each type of pattern is repeated many times. The cell shown in Figure 3.5 is repeated 6 times to form a complete mask for 5 by 5 cm 2 samples. Such an approach ensures flexibility with regards to pattern fabrication and electrical measurements on samples featuring non-idealities such as wrinkles or curved surfaces. C E D A B F Figure 3.5: Overview of one cell of the 2-layer mask design (purple = metal layer; red hatch = mesa layer). The area shown measures about 24 mm by 16 mm. Detailed views of each of the different patterns (A-F) are presented below.

50 3 Sample fabrication and characterisation 40 Detailed views of each of the patterns are shown in Figure 3.6. The patterns CTLM (A) and TLM (B) are for measurements of the specific contact resistance c. The area of each pattern is well below 5 mm 2 (note that 4-point probe measurements require a minimum area of about 50 mm 2 ), which helps to reduce problems associated with samples featuring spatially non-uniform sheet resistance. The current pathlength between neighbouring metal contacts is very short (in the 5-60 m range), making the contact resistance comparable with the resistance of the semiconductor sheet. The measurement capabilities versus the semiconductor sheet resistance of these patterns are listed in Table 3.1. (A) (B) (C) (D) (E) (F) Figure 3.6: A: Circular TLM pattern; B: In-line TLM pattern; C: Metal sheet resistance measurement pattern; D: Hall effect measurement pattern; E: Semiconductor sheet resistance pattern; F: Alignment marks and patterns.

51 3 Sample fabrication and characterisation 41 Table 3.1: Relationship between the smallest measurable specific contact resistance and the sheet resistance of the contacted silicon layer. R sheet (/) < > c (cm 2 ) < Figure 3.6(C) shows a pattern for measuring the sheet resistance of a metal film. It forces the current to flow along a long distance of the metal sheet so that the total resistance is large enough to be measurable. The mesa etch can be omitted if the sheet resistance of the semiconductor is much larger than that of the metal. The metal sheet resistance is about 0.1 / for a 500 nm thick Al film, as given in Section Figure 3.6(D) shows a Hall effect measurement pattern. It can be used to measure the free carrier concentration and the Hall mobility of the semiconductor layer. To avoid parasitic effects due to the MS contacts, a buffer area (four red hatched pads) is designed to connect the active area (one smaller pad at the centre) and the metal. However, due to the unavailability of a Hall effect measurement set-up, this pattern was not used in this thesis. The pattern in Figure 3.6(E) is used to measure the sheet resistance of the semiconductor without any data fitting. Figure 3.6(F) presents the alignment marks and the vernier patterns. The horizontal and vertical venier patterns can be used to estimate misalignments. Each one consists of two layers, metal and mesa. When there is no misalignment, the 0 m slot of the metal venier is fitted by a gear of the mesa venier. When misalignment happens, for example if the left and the top 20 m slots of the metal venier are fitted by the mesa gears, the patterns on the mesa mask are misaligned leftwards and upwards by about 20 m, respectively. Two example photos are shown in Figure 3.12 (lower two photos) Pattern fabrication The measurement models/patterns presented in Section 2.3 can be fabricated through either positive photoresist plus standard photolithography or negative photoresist plus a lift-off process. These two schemes, which reach the same goals via different routes, are

52 3 Sample fabrication and characterisation 42 schematically shown in Figure 3.7. The two-step photolithography process used in this thesis is shown in Figure 3.7. Step 1 refers to metal etching and step 2 refers to mesa etching. In step 2, both the aluminium layer and the photoresist layer act as a protecting mask for the silicon layer during plasma etching. Plasma etching is used as it is a selective process that has a fast etch rate for silicon but a slow etch rate for both photoresist and metal. Etching is always a hazardous process. Thus, the lift-off process is more widely used by people because it saves chemical etching as well as photoresist stripping steps. And isotropical etching (e.g., wet-chemical etching) undercuts the metal underneath the photoresist, which creates the curved sidewalls of the metal. Wide sidewalls (> 1 μm) encumber the dimension measurements of the semiconductor gaps. Moreover, photoresists do not have good adhesion on all types of metal. On the other hand, the lift-off process demands a very steep photoresist sidewall after the exposure step and a relatively thin metal layer (less than half the thickness of the PR), which requires (i) a very collimated light beam; (ii) intimate contact between the photomask and the sample (can be relaxed for a well-collimated light beam); (iii) no light reflection inside the sample during exposure.

53 3 Sample fabrication and characterisation 43 Standard photolithography with positive photoresist Lift-off photolithography with negative photoresist Aluminium deposition Al Si Glass PR coating and exposure PR coating and exposure Development Development Aluminium deposition Aluminium etching Aluminium lift-off PR stripping 2nd photolithography step Collimated UV light beam Photomask (opaque area) Aluminium film Photoresist (PR) PR coating, alignment, UV exposure Development Silicon thin-film Glass Plasma etching and PR stripping Figure 3.7: Process flow of pattern fabrication (not to scale).

54 3 Sample fabrication and characterisation 44 However, given the available equipment for this thesis, the first and second requirements are very difficult to fulfil (see Figure 3.8). The available light beam is not very collimated. Overexposure creates undercut of the photoresist after development, while underexposure creates positive-angled sidewall and enables metal to almost fully cover the sidewall, which hinders the metal from being lifted off. Furthermore, most of the solar cell samples investigated in this thesis are not flat (the glass bends upwards at the corners due to the solid-phase crystallisation step at 600 C or is wrinkled on the silicon side due at the rapid thermal anneal (RTA) step at about 900 C). Therefore, there is always a gap between the photomask and the sample surface. In case of not using vacuum to suck the sample onto the mask, the gap is even larger. This gap and the rough sample surface are the main problems for the photolithography process, as they lead to a non-uniform exposure of the investigated samples (typical size 5 by 5 cm 2 ). Although underexposure seems to be helpful for the lift-off process (as it creates an undercut), underexposure of the whole surface often leads to some areas to be too weakly exposed and hence creates incomplete patterns and lines, which may render the sample useless. UV lamp UV light (not collimated) Rough surface Gap Photomask Photoresist Glass substrate with rough Si film (texture not shown) Exposed area in underexposure situation Extra exposed area in overexposure situation Figure 3.8: Cross-sectional view when UV-exposing a sample with a rough surface (not to scale). Another limitation of the lift-off process is the required thinness of the metal layer (< 50% of the PR layer thickness), which results in a large metal sheet resistance in those cases where a thin photoresist layer has to be used. If the metal sheet resistance is not negligible compared to the silicon sheet resistance, the analysis of TLM measurements is significantly more complicated than in the standard case. The power

55 3 Sample fabrication and characterisation 45 loss associated with current flow in the metal layer will also increase. For all these reasons, the standard photolithography process is preferred for the investigations of this thesis. Although it may also suffer from the non-uniform exposure problem, a few process control methods/procedures were developed to alleviate its disadvantage. As a result, a robust photolithography process on wrinkled poly-si samples was established. Moreover, the adhesion of the photoresist on aluminium is excellent Process optimisation and the results The evaporated Al layer should be thin enough to avoid a wide sidewall after wet-chemical etching but thick enough to ensure a negligible sheet resistance. The thickness is ideally in the range of 300 to 500 nm. The gap between the photomask and the sample caused by the curved glass substrate (after crystallisation) is usually much more problematic than wrinkles (after RTA). One should always try to get the sample RTA d, not only to improve its flatness, but also to reduce the density of point defects in the Si film as well as to activate the dopants [Terry 2006]. If the glass is still bent after RTA, then it is recommended to do another, short RTA to flatten the glass. The flatness can be tested by placing the glass on a level polished metal surface. If the glass does not rotate when a small rotational force is applied, then the flatness is good enough. A high-quality photomask is essential for a successful photolithography process. By using vacuum, an intimate contact can be achieved during UV exposure. Placing the mask directly on the sample without vacuum always creates a wide gap. The exposure time is the second-most important parameter in the photolithography process. A large number of experiments performed in the course of this thesis indicate that 5 s exposure time is ideal for the negative photoresist, while s is best for the positive photoresist. These are the reference times for moderately wrinkled poly-si films. For heavily wrinkled samples or exposure

56 3 Sample fabrication and characterisation 46 without a vacuum, or both, the exposure time should be increased by at least 20%. Remove the sample immediately from the mask aligner after exposure, as there is still some UV light emitted by the machine. The ideal development time for both types of photoresist was found to be s. When using hot phosphoric acid to etch the aluminium, care should be taken to not produce too many bubbles. The bubbles are H 2 created by the chemical reaction. The regions covered by the bubbles are etched much more slowly, and consequently a large number of small Al islands will remain when most areas are free of Al. A short dip in DI water after every s etching interval was found to be very helpful. The etchant temperature should be kept below 60 C to avoid severe overetching. A Measurement and inspection step should always be performed after the PR development step and the phosphoric etching step. The chromium photomask should be regularly Piranha-cleaned (for example whenever it has been used 30 times). Below are two images representing good (left) and bad (right) photolithography processes. The bad process can be avoided by applying the above-mentioned process control methods.

57 3 Sample fabrication and characterisation 47 Figure 3.9: Optical microscope image of a sample with a 5 m wide arc with smooth edges. The dark area is aluminium and the bright area is silicon. Figure 3.10: Optical microscope image of a sample with a nominally 5 m wide ring. Due to underexposure, some regions are thinner than 5 m which renders this sample useless. The dark area is aluminium and the bright area is silicon. A photo of a finished 5 by 5 cm 2 sample is presented in Figure Figure 3.11: Photo of a finished 5 cm by 5 cm sample. The yellowish areas at the edges and corners are silicon layers which arise from edge defects of the photolithography process.

58 3 Sample fabrication and characterisation 48 Figure 3.12 shows a series of optical microscope images (transmission mode) of finished patterns. The black area is metal, the dark brown area is silicon, and the light brown area is glass covered with a very thin SiN residual layer (the SiN film was thinned by the plasma etching step). The numbers above the verniers in the lower two images have critical dimensions of less than 3 m. Considering that the minimum line width obtainable with the UV exposer used in this work is 1-2 m, the photolithography optimisation can be considered as successful. (a) (b) (c) (d) Figure 3.12: (a) Part of CTLM and TLM patterns; (b) Hall effect pattern; (c) Horizontal vernier with ~18 m leftward misalignment; (d) Vertical vernier with ~20 m downward misalignment. 3.4 Plasma etching A plasma etcher with CF 4 or SF 6 gas is used to dry-etch the silicon. It consists of two

59 3 Sample fabrication and characterisation 49 parallel plates as two electrodes in a vacuum chamber with moderate vacuum conditions. The sample sits on the bottom plate which is grounded. A RF (radio frequency) power generates an oscillating electric field which ionizes the feed gas molecules by stripping off some of their electrons, creating a plasma. Fluorine-containing plasma species then attach themselves to the exposed silicon surface, which leads to the creation of SiF x molecules via dry chemical reactions. SiF x molecules then leave the reacting positions via volatilizing in the forms of SiF 2 or SiF 4 [Campbell 2001]. Due to the use of a low power level and the grounding of one electrode, the etching process is not accomplished through physical collisions. Therefore, the plasma etching process is more isotropic than RIE. A U shaped sidewall is typically created by the plasma etch process, which favours emitter electrode formation (contacting the exposed sidewall of the emitter layer). 3.5 Wet-chemical etching with coloured HF Coloured HF is a way to wet-etch silicon isotropically. The solution consists of potassium permanganate (KMnO 4 ) and 5% HF in a certain proportion and has a purple colour. The whole process can be divided into two steps. First, KMnO 4 oxides the silicon; second, HF removes the oxidized layer. The two etch recipes for coloured HF shown in Table 3.2 are used for different material and purposes. The etch rate for poly-si materials is approximately 15 times faster than that for sc-si. Therefore Recipe 1 is usually used for sheet resistance profiling and surface treatment of poly-si thin-films or solar cells, while recipe 2 is usually used for sheet resistance profiling of c-si wafers. Table 3.2: The recipes of the coloured HF. Recipe No. 1 2 KMnO 4 (g) 6 6 DI water (ml) % HF (ml) Total volume of solution (ml) HF concentration of solution, % KMnO 4 concentration of solution (g/100ml) 3 3 Etch rate for c-si (nm/s) The reason why coloured HF etches poly-si much faster than sc-si is believed to be due

60 3 Sample fabrication and characterisation 50 to the grain boundaries. Coloured HF etches grain boundaries more quickly than the bulk of the grains, as can be seen in Figure These images were taken with an optical microscope in the transmission mode (left column) and reflection mode (right column), respectively. The contrast due to the boundaries is getting stronger with increasing etch time. The grain size is approximately 5 m. (a) (d) (b) (e) (c) (f) Figure 3.13: (a)-(c) Images in transmission mode for 20 s, 45 s and 70 s etching in coloured HF; (d)-(f) Corresponding images in reflection mode.

61 3 Sample fabrication and characterisation Sheet resistance profiling In order to examine the doping uniformity of solid-phase crystallised (SPC) poly-si thin-films and the surface doping concentration of c-si wafers with p + or n + -diffused surfaces, a sheet resistance profiling method is employed [Di 2007]. A thin layer of silicon with thickness preferably in the nm range is removed per etching step, using either coloured HF (KMnO 4 + HF) or plasma etching (SF 6 ). The Si etching rate of each of these methods is approximately constant over time. The sample thickness is thus stepwise reduced. Sheet resistance and hot-probe measurements are conducted before every etching step, whereby the hot-probe technique determines the doping polarity of the exposed surface. In order to minimize measurement error and to obtain better data analysis, the sheet resistance profile curves are fitted with fourth-order polynomials. Higher-order polynomials were found to be unsuited because they often introduce significant errors with data fitting at low etching depths (i.e., close to the original sample surface). Because the doping concentration at/near the original silicon surface is most relevant for metallization work and contact resistance studies, the data points in the range nm are fitted with a second-order polynomial instead of a fourth-order polynomial. Examples for this procedure are shown in Figure The R 2 values are close to 1, indicating good fit quality. Figure 3.14: Measured sheet resistance profiles (symbols) and corresponding second-order polynomial fits (lines) of the surface regions of three p + -diffused singlecrystalline n-si wafers.

62 3 Sample fabrication and characterisation 52 Assuming a uniform doping concentration within each removed thin Si layer (22 nm in Figure 3.14), the fitted polynomials allow the determination of the resistivity of each removed Si layer. This procedure involves a simple circuit model consisting of two parallel resistors, as shown in Figure The thinner each removed layer, the more accurate the method will be. Figure 3.15: Method of obtaining the Si resistivity from the measured sheet resistance. R tot is the sheet resistance of the specimen in / measured before an etching step. R etched is the sheet resistance of the layer that is removed in this etching step. R remaining is the sheet resistance of the specimen in / measured after this etching step. The sheet resistance R etched of the removed layer in this etching step can be calculated by 3.3 R etched 1 R tot 1 R 1 remaining The resistivity etched of this thin layer is the product of its sheet resistance and its thickness: R t 3.4 etched etched etched The depth-dependent resistivity profile of the silicon sample can thus be obtained. As an example, Figure 3.16 shows the corresponding results for the three Si wafer samples of Figure From the resistivity profile, the majority carrier profile (i.e., the profile of electrically active dopants) can be determined using graphs, data books or numerical silicon device simulators such as PC1D [SPREE 2007]. As an example, Figure 3.17

63 3 Sample fabrication and characterisation 53 shows the corresponding results obtained from the data of Figure They suggest that the highest doping densities do not occur right at the surfaces of these boron-diffused Si wafers but at a depth of nm below the original surfaces. This behaviour is a well known feature of boron-diffused and subsequently oxidised Si wafers [Sze 2001]. Figure 3.16: Resistivity profiles of the three Si wafer samples of Figure Figure 3.17: Active dopant profiles of the three Si wafer samples of Figure The results were obtained using PC1D modelling.

64 3 Sample fabrication and characterisation Spectroscopic measurements The thickness of the investigated thin-films is obtained via reflectance measurements using a spectrophotometer (Varian CARY 5G). This instrument is able to measure the spectrum of reflected (or transmitted) light in the range nm (ultraviolet to near-infrared). The CARY 5G is a dual-beam system. The first beam is used for reference purposes, while the second beam is directed onto the sample using lenses and mirrors. The set-up features an integrating sphere (diameter ~15 cm), whereby the sample can be mounted on the rear port of the sphere (for reflectance measurements) or on the front port (for transmission measurements). Alternatively, the sample can be mounted inside of the sphere ( centre-mount ) for absorption measurements. In the case of reflectance measurements, the second beam gets partly reflected at the sample surface and the reflected light intensity is recorded by a detector located near the bottom of the sphere. Two lamps are used in this system, one formeasurements in the nm range and one for the nm range. After the raw reflectance data have been obtained, the average thickness value can be obtained by using the wavelength and refractive index of every two adjacent interference peaks. However, significant error can be produced when picking these two parameters. Therefore a modelling program called Wvase32 is applied to acquire the thickness value. Figure 3.18 illustrates two reflectance curves and the corresponding fitting curves. Combined with sheet resistance measurements, the resistivity of a uniformly doped silicon layer can be easily worked out.

65 3 Sample fabrication and characterisation Model Fit Exp urb 8 Generated and Experimental Reflection Wavelength (nm) (a) Model Fit Exp urb 8 Generated and Experimental 0.50 Reflection Wavelength (nm) Figure 3.18: Wvase reflectance curve fitting of (a) an EVA cell (1945 nm Si and 43 nm SiN) and (b) an SPC layer (933 nm Si and 60 nm SiN). (b) 3.8 Dark I-V measurements Four-point probe tester A four-point probe tester from Signatone is used in this thesis to quickly measure the sheet resistance of a film or a solar cell. Figure 3.19 demonstrates the operating principle [Wenham 2006].

66 3 Sample fabrication and characterisation 56 Figure 3.19: Use of a four-point probe to measure the sheet resistance of a p-n junction diode. The junction depletion region between the n and p-doped layers acts as an insulating barrier. The system used in this thesis has a probe spacing s of 1.25 mm. t is the thickness of the layer to be measured. Assuming an infinitely large sample (practically a sample with the length larger than 5s and the width larger than 2s, where s is the spacing between neighbouring needles of the four-point probe system) with a laterally uniform sheet resistance, the sheet resistance can be obtained from the voltage and current readings. If the layer thickness t is much smaller than the probe spacing s, the sheet resistance is given by [Trapp 1980]: V R sheet ln 2 I Curve tracer A Tektronix 370 programmable curve tracer is used to obtain an I-V curve over a wide voltage range. This tracer is particularly helpful for checking if a given metalsemiconductor contact is ohmic or rectifying. However, this machine only provides workable two-point measurements. Therefore, a four-point measurement station was set up in the course of this thesis to enable reliable measurements on samples with low contact resistance Kelvin sense measurement setup Four-point measurements (two probes for applying the current and two probes for measuring the voltage) can also be called Kelvin sense measurements to avoid

67 3 Sample fabrication and characterisation 57 confusion with the four-point probe tester discussed in Section The series resistance of a typical two-point I-V measurement setup is generally about 1 when using two palladium probes on a highly conductive sample. This extra series resistance is a parasitic effect that causes severe problems when measuring samples having a low total resistance. An example for this is given in Figure Therefore, a Kelvin sense measurement set-up is crucial for accurate measurements of contact resistances. It applies a constant current via one needle pair and measures the potential next to each current-carrying needle with a separate needle. Therefore, if the current is plotted vs. the potential difference (voltage) measured by the second needle pair, an I-V curve is obtained (upper curve in Figure 3.20) that is free of the parasitic effect caused by the contact resistance between the current-carrying needle and the sample. Using this approach, lower contact resistances can be measured than with a two-point I-V tester. Figure 3.21 shows photos of the Kelvin sense measurement set-up used in this thesis. 1.2E E E E-04 Current(A) 4.0E E-04 2point probe measurement Kelvin Sense measurement Linear (Kelvin Sense measurement) Linear (2point probe measurement) Voltage(V) 0.0E E E E E E E-01 Figure 3.20: Comparison of I-V curves measured on the same sample with two different measurement methods. The setup has the following main components (see Figure 3.21):

68 3 Sample fabrication and characterisation 58 The shading canvas is used to block the room light. However, when measuring a sample with a heavily doped layer and with tiny exposed area (micron scale), the shading canvas is not necessary. Advantest is a current/voltage generator as well as a voltage/current monitor. It is the core part of the system for providing reliable Kelvin sense measurements. It can perform an I-V scan over a wide current/voltage range. Advantest can be operated manually or numerically by Darkstar (a Labview program, installed in the computer behind the microscope). Manual operation gives more accurate voltage measurements. The size of the patterns is often smaller than 10 m. Therefore, a microscope and a light source are indispensable. Voltage probes with sharp tips (diameter ~5 m) are mounted on two black micro-positioners. These are essential for a precise positioning of the probes. Shading Canvas Lamp Microscope Advantest Darkstar Measurement Station (a)

69 3 Sample fabrication and characterisation 59 Lamp Microscope Current Probes Sample Voltage Probes (b) Figure 3.21: (a) Photo of the Kelvin sense measurement setup used in this thesis; (b) Detailed view of the current and voltage probes of the set-up.

70 4 Contact resistance results on sc-si wafer samples 60 4 Contact resistance results on sc-si wafer samples 4.1 Motivation Due to their well-behaved nature (no grain boundaries, laterally uniform sheet resistance), singlecrystalline silicon wafers are excellent test vehicles for verifying the TLM and CTLM structures established at UNSW in the course of this thesis. Such a verification is important before applying the methods to less well behaved samples such as thin-film materials. 4.2 Sample preparation The experiments reported in this Chapter were performed on samples that were cut off from p-type and n-type singlecrystalline Si (sc-si) wafers with a diameter of 4 inch. The surfaces of the n-type wafers were heavily boron-diffused while those of the p-type wafers were heavily phosphorus-diffused, forming a p-n junction below each surface. The diffusion processes were conducted at high temperature in tube furnaces, using atmospheric pressure. Upon wet-chemical removal of the surface oxides, the sheet resistance of all diffused layers was measured and found to be about 120 /sq, regardless of the position on the wafers. Each wafer was then cut into four pieces of equal size. Figure 4.1 shows the cross-sectional structures of the samples at this stage. Formation of the contact resistance structures started with a piranha clean, followed by a dip in 5% HF to remove any oxides. The resulting surfaces were thus hydrophobic. The samples were then rinsed for 10 min in DI water, followed by drying with a nitrogen gun. The samples were then immediately loaded into the evaporator chamber (no loadlock). The chamber was then pumped down during about 60 minutes to a pressure

71 4 Contact resistance results on sc-si wafer samples 61 of about 10-5 Torr. Then nm of aluminium was evaporated onto the samples, using resistively heated evaporation from a tungsten boat. The evaporation rate was Å/s. The TLM/CTLM structures were then photolithographically patterned. A mesa etch done by plasma etching (PE) was then conducted to constrain the current in the silicon to only flow directly between the contact pads (not necessary for CTLM patterns). p + n + n - p - p + (a) n + (b) Figure 4.1: Structures of the investigated sc-si wafer samples (not to scale). (a) n-type wafer with p + surface diffusions; (b) p-type wafer with n + surface diffusions. 4.3 Results The contact resistances were measured before and after baking the samples at room temperature (~300 K), using the Kelvin sense measurement system presented in Section Different transmission line models were applied, and different annealing processes are compared. All annealing processes were conducted in a nitrogen-purged oven. All fabricated contacts were found to be ohmic. The specific contact resistance values obtained are compared with values reported in the literature Boron-diffused sc-si surfaces The specific contact resistances were measured on three p + diffused sc-si samples using the improved variable gap structure and the circular TLM structure, before and after

72 4 Contact resistance results on sc-si wafer samples 62 baking at 250 C for 30 min in a N 2 purged oven. Then the TLM/CTLM patterns were stripped, followed by the sheet resistance profiling technique to determine the surface doping concentrations. Figure 4.2 shows the resulting characteristic curves (fitted lines) for (a) the variable gap structure (linear fitting) and (b) the circular TLM structure (non-linear fitting). Figure 4.2 indicates that the mathematical models fit the experimental results very well, which also implies uniform contact properties and uniform sheet resistance of the wafers. The measurements in Figure 4.2 are all from the same sample. The results obtained on the other two samples are similar and therefore not shown here. 3.5E+1 3.0E+1 DV_i DV_i,fit 2.5E+1 2.0E+1 1.5E+1 V(mV) 1.0E+1 5.0E+0 d(um) 0.0E (a) 3.0E+1 2.5E+1 DV_i DV_i,fit 2.0E+1 1.5E+1 V(mV) 1.0E+1 5.0E+0 d(um) 0.0E (b) Figure 4.2: The measurement results and characteristic curves of (a) the variable gap TLM structure (linear fitting) and (b) the circular TLM structure (non-linear fitting). These results were measured on a sc-si sample with p + diffused surfaces.

73 4 Contact resistance results on sc-si wafer samples 63 All experimentally obtained specific contact resistance values (before and after baking) are depicted in Figure 4.3 as a function of the surface doping level. The data points represent the average of the values measured for different currents (ranging from 50 A to 5000 A). The error bars represent the 95% confidence interval. As can be seen, thermal annealing improves the specific contact resistances by about an order of magnitude. The measured values lie well within the experimental band of values reported in the literature (dashed region). This verifies that the transmission line models set up at UNSW in the course of this thesis can reliably measure the specific contact resistance of Al/p + -Si contacts Specific contact resistance (-cm 2 ) F7-7-3 VG F7-7-3 VG c before baking c after baking c experimental range (after Schroder & Meier 1984) F7-7-2 CTLM F7-7-2 CTLM F7-7-1 VG F7-7-1 VG Reported range 4x x x x x10 19 Surface doping density (atoms/cm 3 ) Figure 4.3: Specific contact resistances measured on three boron-diffused c-si wafer surfaces with the variable gap structure (VG) and the circular TLM structure (CTLM), before and after baking at 250 C for 30 minutes. The error bars * represent the 95% confidence interval. The corresponding sample name is shown under each data point. The dashed region represents the range of experimentally determined c values of Al/p-Si contacts reported in the literature (after Schroder & Meier 1984). * All error bars shown in this thesis represent 1.96 standard deviations of the corresponding measurements and thus represent the 95% confidence interval.

74 4 Contact resistance results on sc-si wafer samples Phosphorus-diffused sc-si surfaces The specific contact resistance measurements of Al/n + -Si contacts (before and after baking) are presented in Figure 4.4. The data points represent the average of the values measured for different currents (ranging from 1 ma to 100 ma). The error bars again represent the 95% confidence interval. The surface doping concentrations were determined using the sheet resistance profiling technique. As can be seen, the improvement arising from thermal annealing is much less than in the case of Al/p + -Si contacts. Possible reasons for this are discussed in Section 4.4. The specific contact resistances measured on Al/n + -Si contacts again lie well within the band of values reported in the literature (dashed region in Figure 4.4). Moreover, the measured specific contact resistances are below cm 2 and exhibit relatively small error bars. These are clear indications that the measurement models and measurement system (Kelvin Sense) are functioning well and reproducibly Specific contact resistance (-cm 2 ) c before baking c after baking c experimental range (after Schroder & Meier 1984) Reported range Surface doping density (atoms/cm 3 ) Figure 4.4: Specific contact resistances measured on phosphorus-diffused Si wafer surfaces using the circular TLM structure, before and after baking at 250 C for 30 min. The error bars represent the 95% confidence interval. The error bars of the unbaked samples are not shown in the graph. The dashed region represents the band of experimentally determined c values of Al/n-Si contacts reported in the literature [Schroder & Meier 1984].

75 4 Contact resistance results on sc-si wafer samples The influence of baking time and temperature In the early stages of this thesis, most samples were baked sequentially ( sequential baking ) while some were baked only once. In order to distinguish between the effects of the baking time and baking temperature, two types of annealing experiments were conducted on p + diffused Si wafer samples. These small samples were cut from the samples that were cut from the 4-inch wafers. Due to the good lateral uniformity of the p + diffusion across the 4-inch wafers, the small samples all had essentially the same surface properties. Thus, the lateral deviation of the doping density across the entire sample produces a negligible error in the contact resistance. In the first experimental run, three p + diffused samples were used. Each bake had a duration of 30 minutes. The first sample was baked at 150 C, then at 200 C, and then at 250 C (sequential baking). The second was baked at 200 C, while the third was baked at 250 C. As can be seen from Figure 4.5, a single 30-min bake at 250 C gives better contact resistance than a 150/200/250C sequential bake. Thus, for a fixed bake duration of 30 minutes, sequential baking does not seem to be advantageous compared to a single bake. As shown in Chapter 3, the contact edges are exposed to the air. The edges are the critical part to determine the contact resistance rather than the whole contact area. Both the aluminium and the silicon at the contact edges can be slightly oxidized when cooling the sample at the air after baking. And the sequential baking has more cooling times than a single bake. Therefore, sequential baking improves the contact slightly less than a single bake.

76 4 Contact resistance results on sc-si wafer samples 66 Specific contact resistance c (-cm 2 ) 1E-3 1E-4 1E-5 1E Sequential Baking 200 C Baking 250 C Baking No Baking Baking temperature ( C) Figure 4.5: Al/Si specific contact resistance of three p + diffused Si wafer samples after baking under different baking conditions. The sheet resistances (in /) are shown next to each data point. The above finding is further supported by the second experimental run where three p + diffused samples were baked at a fixed temperature of 250 C. The first was baked for 30 min, the second for 60 min, and the third for 90 min. The contact resistance results are presented in Figure 4.6. Considering the slightly different starting values for c, the specific contact resistance values after the bake reveal that a bake duration of 30 minutes is fully sufficient at 250C.

77 4 Contact resistance results on sc-si wafer samples 67 Specific contact resistance c (-cm 2 ) 1E-4 1E-5 1E-6 1E m Baking 60 m Baking 30 m Baking Baking time (minute) Figure 4.6: The specific contact resistance of three p + diffused Si wafer samples as a function of the baking time at 250 C. The sheet resistances (in /) are shown next to each data point. Combining the results from both experimental runs, the conclusion can be drawn that the baking temperature is the dominant parameter for the specific contact resistance of Al contacts on heavily doped singlecrystalline silicon surfaces. The effect of the baking time on the contact resistance saturates for annealing times above about 30 minutes. However, sequential baking can be helpful for samples with poor lateral doping uniformity, as shown in Chapter Discussion and conclusions In this chapter, Al contacts on n + and p + diffused singlecrystalline Si wafer surfaces were investigated. All TLM structures were found to give specific contact resistance values that lie well within in the band of experimental values reported in the literature. Baking at low temperatures ( C) had little effect on the contact resistance of n + samples, whereas it improved the contact resistance massively for p + samples. The reason for this different behaviour of p + and n + samples has to do with the fact that real silicon surfaces, even if carefully cleaned and HF dipped, have a thin (< 10 Å)

78 4 Contact resistance results on sc-si wafer samples 68 native oxide layer on them [SNF 2007]. If an Al film is evaporated onto this thin oxide layer ( tunnel oxide ), the structure shown in Figure 4.7(a) results. It is well known in the literature [Blakers & Green 1981] that the resulting as-fabricated (i.e., not baked) MIS contact has good ohmic properties if the silicon is n-type but poor ohmic properties if the silicon is p-type doped. Thus, baking will have a negligible effect on the ohmic properties of Al/n + -Si contacts, a behaviour confirmed by the results in Figure 4.4. As metallised Increasing thermal budget Al Al Al < 10 Å SiO x AlO y AlO y SiO x SiO x heavily doped Si heavily doped Si heavily doped Si (a) (b) (c) Figure 4.7: Cross-sectional view showing structural changes of Al/SiO x /Si contacts due to increasing thermal budget. (a) Al/(SiO x /)Si contacts as metallised; (b) Si oxides converting into Al oxides during thermal annealing; (c) Al spikes through the interface layers and into the silicon substrate due to higher baking temperature (~300 C) [Bierhals 1998]. (not to scale) The reason why Al/oxide/n + -Si contacts are ohmic is the reduction of the band bending and the Schottky barrier height at the silicon surface due to a sheet of fixed positive charge within the oxide, and the passivation of interface states at the Si-SiO x interface which reduces the negative charge trapped at this interface [Sze & Ng 2007] [Sritharathikhun. 2007]. To understand why baking helps p-type contacts, it is necessary to consider the structural changes that occur in Al/oxide/silicon contacts during baking [Bierhals 1998]. These structural changes are schematically shown in Figure 4.7. They are due to the fact

79 4 Contact resistance results on sc-si wafer samples 69 that Al is more reactive (less noble) than Si, leading to the conversion of the upper regions of the SiO x film into AlO y : 4.1 4Al + 3SiO 2 2Al 2 O 3 + 3Si If the baking is continued for a sufficient amount of time (increased thermal budget), Al spikes will start to locally penetrate into the AlO y and SiO x layers, see Figure 4.7(b). For even higher thermal budget the Al spikes will eventually penetrate through the oxide layer into the underlying silicon material. The Al spikes locally shunt the insulating layers and provide good ohmic contact regions to the underlying heavily doped silicon. In the non-spiked regions the device has poor ohmic properties due to the band bending at the semiconductor surface caused by workfunction differences between Al and Si and the fixed oxide charge [Sritharathikhun 2007]. In conclusion, the contact resistance measurements performed in this chapter on heavily doped singlecrystalline silicon surfaces demonstrate that the transmission line models set up at UNSW in the course of this thesis can reliably measure the specific contact resistance of Al on both n + and p + doped silicon. The dominant parameter in the baking process for the contact resistance is the baking temperature, whereby hotter is better. Baking has negligible effects on the ohmic properties of Al on n + -Si surfaces, however, the specific contact resistance of Al on p + -Si surfaces improves massively (factor 10 or more) due to baking at sufficiently high temperature and for sufficiently long times. As the aim of this chapter is to preliminarily test the contact resistance measurement system before applying this technique to the different poly-si thin-film solar cells investigated at UNSW, and due to the fact that the performance of those cells degrades after annealing at higher temperatures (> ~300 C) [Terry 2007], the effect of baking at temperatures higher than 250 C is not systematically investigated in this Chapter.

80 5 Contact resistance results on uniformly doped poly-si films on glass 70 5 Contact resistance results on uniformly doped poly-si films on glass 5.1 Motivation Uniformly doped evaporated polycrystalline silicon thin-films on glass (i.e., no p-n junctions) are well suited to investigate the contact resistance because of their simpler structure and better surface quality (no hydrogenation-induced damage) as compared to completed solar cells. The results can be a good reference when moving the scope to completed solar cells. As Al/Si contacts on singlecrystalline wafers are well studied and understood, comparing the results presented in this Chapter to the results based on sc-si reported in the literature can give a good insight into the general features of aluminium contacts on evaporated silicon material for solar cell application. All TLM structures which were verified in Chapter 4 (except the conventional ladder network model) were employed in this Chapter. 5.2 Sample preparation All experiments reported in this Chapter were performed on uniformly doped SPC poly-si thin-films. The fabrication sequence is as follows: First, a phosphorus or boron-doped a-si film (thickness in the range of nm) was evaporated onto SiN-coated glass substrates (planar or textured) using e-beam evaporation. Then the a-si film was crystallised by SPC (solid-phase crystallisation) in a nitrogen-purged furnace at 600 C for 48 hours [Song 2006]. Most of the samples then received a rapid thermal anneal (RTA) at 900 C for 4 minutes to activate dopants and reduce the density of point defects [Terry 2007]. RTA also flattens the glass substrates which can deform significantly during the SPC process. The importance of having a flat substrate for TLM patterning was discussed in Chapter 3. The samples did not receive any hydrogenation

81 5 Contact resistance results on uniformly doped poly-si films on glass 71 treatment. All films have fairly uniform thickness (the deviations from the average value are < 10%). The doping density is above cm -3 for all films (both p-type and n-type). To quantify the active doping level, the thickness of each poly-si film was measured via spectroscopic measurements and from this together with the measured sheet resistance, the films electrical resistivities were determined. For heavily doped poly-si thin-films, the active doping concentration is only slightly higher than that of singlecrystalline Si wafers with the same resistivities. The doping ratio of these two materials varies less than a factor of 2 [Seto 1975, Monkowski 1979]. Formation of the contact resistance structures started with a piranha clean, followed by a dip in 5% HF to remove the surface oxide. The resulting surfaces were found to be hydrophobic. The samples were then rinsed for 10 min in DI water, followed by a blow dry in N 2 gas. Then, the samples were immediately loaded into the evaporator chamber (no loadlock). The chamber was pumped down during about 60 min to a pressure of about 10-5 Torr. A nm thick Al film was then evaporated onto the samples at Å/s, using resistively heated evaporation from a tungsten boat. Prior to the Al evaporation, some of the n-type poly-si samples were baked in an atmospheric oven at 150 C for 30 min in order to form an Al/SiO x /n + poly-si contact structure. Finally, the TLM patterns (conventional/improved variable gap, improved ladder network, circular TLM) were made via photolithographic structuring of the Al film. A mesa etch done by plasma etching (PE) was then conducted to constrain the current in the silicon to only flow directly between the contact pads (not necessary for CTLM patterns). 5.3 Results All contact resistance measurements were performed at room temperature (~300 K), before and after baking the samples by using the Kelvin sense measurement system described in Section In order to ensure good measurement precision, the current range used for each measurement covered three orders of magnitude, within the range of 5 A to 100 ma. All transmission line models discussed in Chapter 2, except the conventional ladder network model, were applied. The long-term stability and the thermal annealing effect of Al/poly-Si contacts are studied. Moreover, the specific

82 5 Contact resistance results on uniformly doped poly-si films on glass 72 contact resistance values of SPC poly-si films are compared to the reported experimental values obtained on sc-si wafers and LPCVD-grown poly-si films, and analysed in terms of doping density and Schottky barrier height. Note that the term poly-si used in this thesis refers to evaporated SPC poly-si films fabricated at UNSW. Other technologies used are explicitly mentioned. Al/Si contacts have been reported to be long-term stable [Ponpon & Siffert 1978] at room temperature, provided the Al film is thick enough (> 100 Å) to prevent the diffusion of atmospheric oxygen through the Al. To verify this behaviour for Al/poly-Si contacts, the specific contact resistance of several baked samples (both p + and n + poly-si) were re-measured after 3 months of storage in air. As can be seen from Figure 5.1, the contact resistance of all samples was stable. Specific contact resistance c (-cm 2 ) Al/SiO x /n-si Al/n-Si 1 Al/n-Si 2 Al/p-Si 0 3 Months of storage Figure 5.1: The measured contact resistance of baked Al/poly-Si samples before and after storage in air for 3 months. Prior to the first measurements, the samples were baked at 250 C for 30 minutes. The maximum error bar of each set of measurements is shown in the legend.

83 5 Contact resistance results on uniformly doped poly-si films on glass Boron-doped Si films A. Evidence of ohmic contact All p + doped poly-si films were metallised without intentionally growing an oxide layer on the surface. Figure 5.2 shows an example of I-V measurements taken on two adjacent Al bars/pads/circles separated by a resistive p-type poly-si film. The contact was not baked. As can be seen, the I-V curve is linear over the entire measured voltage range of ± 3.5 V, showing that Al makes good ohmic contact to p + doped poly-si films without baking. amps 1.E-02 8.E-03 R 2 = 1 6.E-03 4.E-03 2.E-03 0.E E volts -4.E-03-6.E-03-8.E-03-1.E-02 Figure 5.2: A typical measured I-V curve between two Al contacts on p + doped poly-si (resistivity = 25.5 mcm). The measurement was performed on as-metallised (i.e., non-baked) samples. B. The effect of thermal annealing on the specific contact resistance Figure 5.3 shows the improvement of the Al/p + poly-si contact resistance due to sequential baking at increasing temperature in a N 2 -purged oven. The duration of each bake was 30 min. The number next to each data point is the electrical resistivity of the poly-si film in units of mcm. It can be seen that baking improves the specific contact resistance by more than one order of magnitude. Good contact resistance values of

84 5 Contact resistance results on uniformly doped poly-si films on glass 74 about cm 2 were obtained after sufficient baking. However, the effect of annealing on the specific contact resistance saturates for annealing temperatures higher than 250 C. This is due to the fact that most of the silicon oxide film that exists on the Si surface prior to the aluminium evaporation is consumed by Al during low-temperature baking (< 250 C). This oxide film is detrimental to Al/p-Si contacts as it contains fixed positive charges, as discussed in Chapter 4 [Sze & Ng 2007]. Because intimate contacts are already formed, additional baking at 300 and 350 C does not further improve the specific contact resistance of the Al/p + poly-si contact Specific contact resistance c (-cm 2 ) No Baking Annealing temperature ( C) Figure 5.3: The specific contact resistance of Al/p + poly-si contacts during successive bakes at increasingly hotter temperature. The duration of each bake was 30 min. The electrical resistivities of the films are also shown beside the data points (in mcm). The error bars represent the 95% confidence interval. C. Doping density dependence of the specific contact resistance Figure 5.4 illustrates the relation between the silicon resistivity and the specific contact resistance of Al/p + poly-si contacts (before and after a single bake at 250 C for 30 min).

85 5 Contact resistance results on uniformly doped poly-si films on glass 75 The data points (all symbols) represent the experimental measurements on evaporated p + doped poly-si films. Only a random selection of samples was baked after the first contact resistance measurement. Note that the resistivity decreases with increasing doping level. For heavily doped poly-si, the active doping concentration is only slightly higher than that of singlecrystalline silicon with the same resistivity. As can be seen, the specific contact resistance drops dramatically with reducing Si resistivity (increasing doping level). Generally, baking reduces c by more than one order of magnitude on average, which is in good agreement with the baking experiments on p-type contacts presented in Figure 5.3 and Chapter Doping level (cm -3 ) Specific contact resistance c (-cm 2 ) 10-2 c of Al/p + poly-si contact before baking c of Al/p + poly-si contact after baking 10-3 c of Al/p + poly-si contact before baking (O contaminated) c of Al/p + poly-si contact after baking (O contaminated) 10-4 Experimental c range of Al/p + sc-si contact (after Schroder & Meier 1984) Experimental c range of Al/p + poly-si 10-5 contact (after Ford 1983) Resistivity of Si layer (m-cm) Figure 5.4: Measured specific contact resistance of Al/p + poly-si contacts versus Si resistivity at room temperature (~300 K), before and after a single bake at 250 C for 30 min (not all samples were baked). The two parallel dot-dashed lines outline the trend of these measurements. The band of experimental c values of Al/p-Si contacts on sc-si wafers (dash-hatched area) reported by Schroder and Meier [1984] and Al/p-Si contacts on poly-si (dot-hatched area) reported by Ford [1983] are also presented. The doping level axis shown on the top is produced from the corresponding sc-si resistivity. For heavily doped poly-si, the active doping concentration is higher than the one of sc-si with the same resistivity by a factor of less than 2. For the sake of clarity, no error bars are shown for the experimental data points. Representing 95% confidence interval, the error of each data point is generally ±40%.

86 5 Contact resistance results on uniformly doped poly-si films on glass 76 In Figure 5.4, the results with triangle symbols (filled and empty ) are outside the main data region (defined by the two parallel dash-dotted lines) of measured values. These results represent samples which were very likely heavily oxygen-contaminated during a-si deposition and/or the rapid thermal annealing process. One supporting evidence for this interpretation is that, after dipping these samples in 5% HF for a sufficient time in order to remove the surface oxide before metallisation, the surfaces were not completely hydrophobic. The normal samples did not show this behaviour. Moreover, these abnormal samples were all fabricated in one experimental run. Oxygen contamination is always detected in the UNSW thin-film solar cells through SIMS measurements [Terry 2007]. The oxygen atom density near the surface can even be one to two orders of magnitude higher than the intended density of dopant atoms. Oxygen is known to be able to act as an n-type dopant in silicon and hence introduces donor states at the silicon surface. It is noted that only a certain fraction (<< 50%) of the existing oxygen atoms in silicon show donor-like behaviour [Kimerling & Benton 1981, Ourmazd 1984]. Under thermal equilibrium, these donor states are positively charged resulting in heavier silicon band bending at the interface. A high interface state density may cause the silicon Fermi level at the surface to be pinned [Rhoderick 1988, Sze & Ng 2007]. This effect, together with the heavier band bending, causes the Schottky barrier height of p-si to be increased. Both the higher Schottky barrier height and the heavier surface band bending (depletion conditions) cause poorer ohmic properties than in the cases of low O contamination. Therefore, as can be seen in Figure 5.4, to reach the same specific contact resistance level as for the normal samples (lightly O contaminated) (squares ), the heavily O-contaminated samples (triangles ) need the resistivities to be about 5 times lower (higher doping level). Thermal annealing may eliminate the fixed positive charge due to the SiO x interfacial layer as discussed previously, but cannot annihilate the positive charges arising from O contamination. Therefore, thermal annealing at 250 C for 30 min does not offer a significant improvement of the specific contact resistance for heavily O contaminated p + poly-si samples. Another interesting finding from Figure 5.4 results from a comparison of the experimental specific contact resistance values of Al/p-Si contacts made from i) evaporated poly-si (lightly O contaminated, squares ); ii) LPCVD poly-si (dot-hatched region) [Ford 1983]; iii) sc-si (dash-hatched region) [Schroder & Meier

87 5 Contact resistance results on uniformly doped poly-si films on glass ]. In the figure, the two parallel dash-dotted lines define the measurement range for normal category i) samples and exhibit the trend of the specific contact resistance versus the silicon resistivity (doping density). The dot-hatched region shows the trend of c for Al contact on LPCVD-fabricated poly-si, and the dash-hatched region shows the trend of c for Al contact on sc-si. The LPCVD poly-si was reported to be deposited on a SiO 2 layer grown on a <100> n - sc-si wafer and then doped via ion implantation. Then, a 10 Å thick Al film (with a Si content of 1.5%) was evaporated onto the sample. The samples were then annealed at 450 C for 20 min in forming gas. Note that the silicon was added to the Al to minimise silicon diffusion into the aluminium film during postmetallisation annealing. This Si content has negligible impact on the specific contact resistance if a sufficiently hot and long annealing process is conducted [Faith 1982]. It can be seen in Figure 5.4 that c of Al/ LPCVD poly-si contacts is slightly higher than that of Al/sc-Si contacts at high doping levels, but the slopes of their trends are similar. The higher c is due to the granular nature and higher tunnelling effective masses of poly-si [Ford 1983]. However, the trend of c of Al/evaporated poly-si contacts (region defined by the two parallel dash-dotted lines) exhibits a much steeper slope than for the other two contacts. In other words, c drops much more quickly with decreasing resistivity than for the other two contact types. The cross-over occurs at a Si resistivity of about 10 mcm. Thus, the specific contact resistance of evaporated p-type poly-si is better than the one of LPCVD poly-si and sc-si if the silicon is more heavily doped (> ~ /cm 3 ). Furthermore, it can be also seen in Figure 5.4 that c of Al/poly-Si contacts cover a larger range than for Al/sc-Si contacts. This is believed to be due to the random crystal orientations of poly-si films crystallised via SPC [Song 2006]. So far, to the best of the author s knowledge, there is no solid model to explain the behaviour of Al/poly-Si contacts. Furthermore, Figure 5.4 reveals that the evaporated SPC poly-si films made at UNSW behave differently compared to poly-si samples reported in the literature. For relatively lowly doped silicon (< ~ /cm 3 ), c of Al/evaporated poly-si contacts is higher than for the other two types of contacts considered in the figure. This difference is believed to be due to the higher Schottky barrier height which dominates the specific contact resistance for metal contacts on lowly or moderately doped silicon, where the dominant current transport mechanism is

88 5 Contact resistance results on uniformly doped poly-si films on glass 78 thermionic emission over the barrier [Sze & Ng 2007]. Grain boundaries can increase the barrier height because interface states and depletion layers at grain boundaries produce variable potential barriers to carrier flows [Monkowski 1979]. The grain size for evaporated solid phase crystallised poly-si is μm [Song 2006]. In more highly doped region (> ~ /cm 3 ), c of Al/poly-Si contacts is found to be lower than that of the other two types of contacts. The potential barrier which arises from grain boundaries reduces significantly. Furthermore, it is speculated that evaporated p + poly-si has lower tunnelling effective mass and hence higher effective Richardson constant than both LPCVD p + poly-si and p + sc-si, which in turn reduces the electron tunnelling resistance. The possible reason is as follows. If the silicon surface is heavily or degenerately doped, the dominant current transport mechanism is free carrier tunnelling through the depletion region whose width is inversely proportional to the surface doping level [Sze & Ng 2007]. Decreasing the tunnelling resistance will definitely increase the tunnelling current. More detailed modelling and discussion are given in Section Phosphorus-doped Si films with and without SiO x interlayer A. Evidence of ohmic contact Figure 5.5 shows an example of I-V measurements taken on two adjacent Al bars/pads/circles separated by a resistive n-type poly-si film. The contact was not baked. As can be seen the I-V curve is linear over the entire measured voltage range of ± 3.5 V, showing that Al makes good ohmic contact to n + doped poly-si films without baking. Al/SiO x /n + poly-si contacts were also found to be ohmic before and after baking.

89 5 Contact resistance results on uniformly doped poly-si films on glass 79 amps 1.E-02 8.E-03 R 2 = 1 6.E-03 4.E-03 2.E-03 0.E E volts 4-4.E-03-6.E-03-8.E-03-1.E-02 Figure 5.5: A typical measured I-V curve between two Al contacts on n + doped poly-si (resistivity = 26.2 mcm). These measurements were performed on as-metallised (i.e., non-baked) samples. B. The effect of thermal annealing on the specific contact resistance Figure 5.6 shows the improvement of the Al/n + poly-si contact resistance due to sequential bakes at increasing temperature in an N 2 -purged oven (sequential baking). The duration of each bake was 30 min. It can be seen that baking improves the contact resistance by less than an order of magnitude. Good contact resistance values of about cm 2 are obtained after sufficient baking. However, the improvement is not as significant as in the case of Al/p + poly-si films (see Figure 5.3). This finding agrees well with that obtained on sc-si in Chapter 4. The reason for this behaviour has been discussed in detail in Chapter 4. Baking at 300 C in a N 2 -purged oven is found detrimental to Al/n + poly-si contacts, which agrees with the findings on sc-si material reported in the literature [Faith 1983]. Being a p-type dopant in silicon, Al introduces ionised acceptor atoms at the n-si surface during the annealing process, which may even lead to an Al/p + -Si/n-Si contact structure [Finetti 1980]. Baking at 300 C may not yet cause a heavily doped p-type poly-si interfacial layer, but will definitely deteriorate Al/n + poly-si contacts and hence increase the specific contact resistance.

90 5 Contact resistance results on uniformly doped poly-si films on glass 80 Specific contact resistance c (-cm 2 ) Al/n + poly-si_sample1 Al/n + poly-si_sample No Baking Baking temperature ( C) Figure 5.6: The specific contact resistance of Al/n + poly-si contacts during sequential bakes at increasing temperature. The duration of each bake was 30 min. The resistivities of the films are also shown beside the data points (mcm). The error bars represent the 95% confidence interval. The thermal annealing experiments were also conducted on Al/SiO x /n + poly-si contacts. The baking process is again the sequential baking. The duration of each bake was 30 minutes. As can be seen in Figure 5.7, there is no significant improvement due to baking up to the temperatures of 200 C. However, the specific contact resistance drops abruptly during baking at 250 C, which implies that at this temperature aluminium penetrates into the SiO x interfacial layer and approaches the optimum distance from the silicon interface where the remaining SiO x interfacial layer is thin enough to be easily tunnelled by the electrons while thick enough to maintain a high density of fixed positive charge (which helps n-type contacts). Finally, baking at 300 C increases the specific contact resistance. This is due to the elimination of the beneficial Si oxide interlayer and the interaction of Al and n-type poly-si as discussed above. The compound SiOx is stoichiometric when x = 2 and nonstoichiometric in all other cases.

91 5 Contact resistance results on uniformly doped poly-si films on glass Specific contact resistance c (-cm 2 ) Al/SiO x /n + poly-si_sample1-2 Al/SiO x /n + poly-si_sample2-2 No Baking Annealing temperature ( C) (a) Specific contact resistance c (-cm 2 ) Al/SiO x /n + poly-si_sample1-1 Al/SiO x /n + poly-si_sample2-1 Al/SiO x /n + poly-si_sample No Baking Annealing temperature ( C) (b) 2.02 Figure 5.7: The specific contact resistance of Al/SiO x /n + poly-si contacts during sequential bakes at increasing temperature. The duration of each bake was 30 minutes. The resistivities of the films are also shown beside the data points (mcm). The error bars represent the 95% confidence interval. (a) Samples with TLM patterns of smaller dimensions; (b) Samples with TLM patterns of larger dimensions. The measurement results are not affected by the dimensions of the TLM pattern used.

92 5 Contact resistance results on uniformly doped poly-si films on glass 82 Comparing Figure 5.6 and Figure 5.7 it can be seen that, for a given Si resistivity, Al/SiO x /n + poly-si contacts have much lower specific contact resistance than Al/n + poly-si contacts, after baking at sufficiently high temperature. This indicates that growing a thin native silicon oxide layer before Al deposition improves Al/n-type poly-si contacts significantly. C. Doping density dependence of specific contact resistance Figure 5.8 illustrates the relation between the silicon resistivity and the specific contact resistance (before and after a single bake at 250 C for 30 min) for Al/n + poly-si contacts as well as Al/SiO x /n + poly-si contacts. The data points (all symbols) represent the measurements on evaporated n + doped poly-si films. Only a random selection of samples was baked after the first contact resistance measurement. As can be seen, the specific contact resistance drops by more than three orders of magnitude if the Si resistivity decreases by a factor of about 5. A thin SiO x interfacial layer was formed on some of the samples (diamonds ) by baking in an atmospheric oven at 150 C for 30 minutes just before the Al evaporation step. Generally, baking slightly reduces c for contacts without SiO x interfacial layer () but significantly reduces c for contacts with SiO x interfacial layer (). This finding agrees well with the results of the baking experiments presented previously in this Chapter and in Chapter 4. Evidently, after sufficient baking, a thin SiO x interfacial layer improves Al contact on n + doped poly-si contact drastically.

93 5 Contact resistance results on uniformly doped poly-si films on glass Doping level (cm -3 ) Specific contact resistance c (-cm 2 ) Resistivity of Si layer (m-cm) Figure 5.8: Measured specific contact resistance of Al/n + poly-si and Al/SiO x //n + poly-si contacts versus the Si resistivity at room temperature (~300 K), before and after a single bake at 250 C for 30 min (not all samples were baked). The two parallel dot-dashed lines outline the trend of these measurements. The band of experimental c values of Al/n-Si contacts on sc-si wafers (dash-hatched area) reported by Schroder and Meier (1984) and Al/n-Si contacts on poly-si (dot-hatched area) reported by Ford (1983) are also presented. The doping level axis shown on the top is produced from the corresponding sc-si resistivity. For heavily doped poly-si, the active doping concentration is higher than the one of the sc-si with the same resistivity by a factor of less than 2. Error bars are omitted for the sake of clarity. Representing 95% confidence interval, the error of each and data point is generally ±15%; the error of each and data point is generally ±30%;the error of each and data point is generally ±70%..

94 5 Contact resistance results on uniformly doped poly-si films on glass 84 In Figure 5.8, the results with triangle symbols (filled and empty ) are outside the main data region (between the two parallel dash-dotted lines) of measured values. Similar to some of the results shown in Figure 5.4 (p-type contacts), these results were obtained from the samples fabricated in one experimental run, which got very likely heavily oxygen-contaminated during a-si deposition and/or the rapid thermal annealing process. As discussed in Section 5.3.1, oxygen introduces positive charges (ionised donors). Being different from the p-si case, these positive charges reduce the Schottky barrier height of Al/n-Si contacts, whose mechanism is similar to the fixed positive charge introduced by the SiO x interfacial layer. Thermal annealing may eliminate the oxide related fixed positive charge, but cannot annihilate the positive charges arising from O contamination, as discussed in Section Therefore, annealing does not bring those triangle data points back to the main data region. As the result of a lower Schottky barrier height, heavily O contaminated samples (triangles ) have better ohmic properties than lightly O contaminated samples (squares ). Thus, these samples reach the same c level with a resistivity that is almost one order of magnitude higher (i.e., lower doping level) than in the case of samples with low O contamination. Similar to the presentation in Figure 5.4 (Al/p-Si contacts), the comparison among the experimental specific contact resistance values of three types of Al/n-Si contacts are also given in Figure 5.8. They are Al contacts on i) e-beam evaporated n + poly-si (lightly O contaminated, filled and empty squares, ); ii) LPCVD n-type poly-si (dot-hatched region) [Ford 1983], and iii) n-type sc-si (dash-hatched region) [Schroder & Meier 1984]. The fabrication process of LPCVD n-type poly-si is the same as the one introduced in Section 5.3.1, except that the dopants are phosphorus atoms. Again, in the figure, the two parallel dash-dotted lines on the right define the range of main normal measurements of category i) samples (squares ) and exhibit the trend of the specific contact resistance versus the silicon resistivity (doping density). The trend of Al contact on n + poly-si fabricated by e-beam evaporation roughly agrees with the one of Al contacts on LPCVD n + poly-si and n + sc-si. Comparing Al/poly-Si contacts to Al/sc-Si contacts, the latter has higher c in lower doped region and has lower c when the silicon is more highly doped. This result is similar to the one presented in Figure 5.4 (Al/p-Si contacts), and the possible reasons were already given in Section

95 5 Contact resistance results on uniformly doped poly-si films on glass Discussion In order to further understand the behaviour of Al/poly-Si contacts, it is necessary to discuss their Schottky barrier heights. First of all, the barrier height of the well-studied Al/sc-Si contacts is briefly reviewed. The Schottky barrier height is a figure-of-merit of MS contacts. Under ideal conditions (i.e., no defects at the interface, no interface states, no barrier lowering, no insulator interfacial layer, no effect from the contacting metal or other anomalies), the Schottky contact barrier height can be predicted by the Schottky model if the metal work function m and semiconductor affinity are known. Figure 5.9 illustrates the band diagrams of ideal aluminium contacts on (a1) n-si and (a2) p-si, as well as the corresponding calculated Schottky barrier heights. If the Si is lowly doped, free carriers with high energy can overcome the barrier and form a current (thermionic emission). If the Si is highly doped, a current can be formed via thermionic emission as well as free carrier tunnelling through the barrier. The theoretical Schottky barrier heights q B are 0.27 ev for Al/n-Si contacts and 0.85 ev for Al/p-Si contacts [Neamen 2003]. Both the barrier height and the built-in voltage (arising from the band bending) are smaller for Al/n-Si contacts than for Al/p-Si contacts. However, experiments give the opposite result. It has been found that the Schottky model cannot be applied directly to practical cases [Sze 1969, Cheng 1977, Rhoderick & Williams 1988]. In practice, the Schottky barrier height is found to be relatively independent of the metal work function for common semiconductors like Ge, Si and GaAs. A rule of thumb is that the barrier height is roughly two-thirds of the bandgap for n-type semiconductors and one-third of the bandgap for p-type semiconductors [Schroder & Meier 1984], which indicates that the actual barrier heights are a function of the bandgap. The empirical (experimentally determined) Schottky barrier values are ev for Al/p-Si contacts and ev for Al/n-Si contacts [Yu 1970, Chang 1971, Andrews 1974, Pramanik & Saxena 1983, Schroder & Meier 1984, Neamen 2003, Sze & Nk 2007]. The equations below indicate that the Schottky barrier height B is determined by the metal work function m and the semiconductor affinity s, as well as semiconductor

96 5 Contact resistance results on uniformly doped poly-si films on glass 86 bandgap E g and the surface state neutral level 0, while the interface state density D it is a weighted factor [Rhoderick & Williams 1988]. where 5.1 q q ) (1 )( E q ), 5.2 B i 2 i ( m g 0 q D it i is the permittivity and is the thickness of the interfacial layer. Bardeen first pointed out the importance of the energy states in the bandgap induced by the imperfections or impurities at the semiconductor surface which are known as surface states or interface states [Bardeen 1947]. The atoms inside a crystalline solid are arranged in a well-ordered structure. However, the situation at the surface is different due to dangling (or unsatisfied) bonds which arise from the absence of neighbouring atoms. Surface states may also result from impurities and defects. There is generally a continuous distribution of surface states within the silicon bandgap at the surface, characterised by a neutral level q 0 which is measured from the top of the valence band. The states above the neutral level are of acceptor type and those below this level are of donor type. Due to these states the silicon surface is charged, which causes band bending even before depositing a metal film, see Figure 5.9(b1). Note that there is always a thin native oxide layer on the silicon surface before metallisation [SNF 2007]. The dangling or unsatisfied bonds at the semiconductor surface can be passivated by bonding other foreign atoms to form a more stable compound. Therefore, a native oxide layer helps to reduce the surface state density and causes the actual barrier height of the contact to be closer to the ideally expected value. Equation 5.1 can be simplified for two limit conditions: i) When D it 0, then 1 and 5.3 q q B m This case indicates a negligible interface state density and the classical Schottky model applies. The Schottky barrier height is determined by the metal work function m and the electron affinity s of the semiconductor. Practically, for Si, D it must be smaller than

97 5 Contact resistance results on uniformly doped poly-si films on glass ev -1 cm -2 [Schroder & Meier 1984, Rhoderick & Williams 1988]. ii) When D it, then 0 and 5.4 q E q0 B g This case indicates an infinite interface state density and the Bardeen model applies. The Fermi level at the interface is pinned by the interface states at the value q 0 above the valence band. The Schottky barrier height is independent of the metal work function and the electron affinity of the semiconductor but determined entirely by the property of the semiconductor surface. Practically, for Si, D it must be larger than ev -1 cm -2 in order to observe a strong Fermi level pinning [Rhoderick & Williams 1988]. In the Bardeen model, an interfacial SiO x layer must be assumed when the MS contact is formed. This layer is thin enough (< 50 Å) to allow electron tunnelling but thick enough to withstand an electric potential across it. As the Fermi levels of metal and semiconductor must line up after the MS contact is formed and the Schottky barrier and the built-in potential at the semiconductor surface are already fixed even before contacting the metal, the interfacial layer is then responsible for balancing the voltage/energy difference between systems (metal and semiconductor) after the contact is formed, see Figure 5.9(b2). The magnitude and polarity of the voltage drop across the oxide with thickness is determined by the metal work function m, semiconductor work function s and the built-in potential bi. Experimentally determined parameters of n-type silicon surfaces are summarised in Table 5.1. It can be seen that the surface state density of silicon is very high, approaching the threshold of the Bardeen limit (10 14 ev -1 cm -2 ). The value of q 0 can be used to calculate the Schottky barrier height q Bn for Al/n-Si contacts, which is 0.8 ev if assuming that the Fermi level is pinned (Equation 5.4). This value roughly agrees with the experimentally obtained q Bn value of ev. The corresponding value for Al/p-Si contacts q Bp can then be found via Equation 5.5 [Rhoderick & Williams 1988], giving 0.3 ev. This again roughly agrees with the experimentally obtained q Bp [Pramanik & Saxena 1983]. Note that Equation 5.5 holds regardless of whether the interface is ideal or not.

98 5 Contact resistance results on uniformly doped poly-si films on glass 88 Table 5.1: Selected properties of the surfaces of n-type sc-si (after Cowley & Sze 1965, Sze 2007) D it (ev -1 cm -2 ) q 0 (ev) q 0 /E g q Bn qbp E g Although the interface state density of silicon has been found to be very high, the Fermi level E F may not be completely pinned at the neutral level q 0. The Schottky barrier height still has to be found via Equation 5.1 rather than via the simplified equations. D it may also depend on the silicon fabrication technique and possible surface treatments. Moreover, because there is generally a thin silicon oxide layer on the silicon surface prior to metallisation (which introduces a fixed positive interface charge and which passivates the interface), the precise calculation of the Schottky barrier heights for both Al/n-Si and Al/p-Si contacts is further complicated. A large number of experiments on singlecrystalline silicon reported in the literature shows that the Schottky barrier heights are ev for Al/p-Si contacts and ev for Al/n-Si contacts. These values should be compared with the ideal ones, which are 0.85 ev for Al/p-Si contacts and 0.27 ev for Al/n-Si contacts. Owing to the large discrepancy of empirical and theoretical barrier height values, as well as the structures of MS contact band diagrams of Al/Si contacts, it can be speculated that the silicon interface states are mainly acceptor type. This produces a net negative charge at the interface, see Figure 5.9(b1) and (b2). This charge is detrimental to n-type contacts but beneficial to p-type contacts. If the silicon is heavily O contaminated (which introduces a large density of positive charge due to ionised donors), the overall interface charge arising from the interface states will be reduced, and hence cause the practical MS contact to become closer to the ideal situation. See Figure 5.9(c1) and (c2).

99 5 Contact resistance results on uniformly doped poly-si films on glass 89 Vacuum level Vacuum level q m q Bn e e e q s E C E F E Fi E V q m q Bp h h h q s E C E Fi E F E V Aluminium n-type Silicon q Bn = m = 0.27 ev (a1) Aluminium p-type Silicon q Bp = E g ( m ) = 0.85 ev (a2) q s Vacuum level q bi q Vacuum level q bi q 0 q bi q s E C E F q m q bi q s E C E F E Fi E V q Bn = E g - q 0 E Fi E V SiO x n-type Silicon (b1) Aluminium SiO x n-type Silicon (b2) Vacuum level Vacuum level Bn O contaminated E C E F E Fi E V Bp O contaminated E C E Fi E F E V Aluminium SiO x n-type Silicon q Bn = ev (c1) Aluminium SiO x p-type Silicon q Bp = ev (c2) Figure 5.9: Band diagrams of Al/Si contacts. (a1) and (a2) are ideal Schottky models; (b1) and (b2) are Bardeen models where the Fermi level is pinned; (c1) and (c2) are practical Al/Si contact band diagrams with and without heavy oxygen contamination of the silicon. The equations correspond to the contacts which are not heavily oxygen contaminated.

100 5 Contact resistance results on uniformly doped poly-si films on glass 90 Now let us move the focus to UNSW s poly-si films fabricated by SPC of e-beam evaporated silicon. As discussed in Chapter 2, if the silicon is moderately to heavily doped ( cm -3 ), the specific contact resistance of intimate metal/semiconductor contacts is a function of both the Schottky barrier height and the silicon doping density. However, this conclusion was drawn from (and is usually verified by) the contact resistance investigation on singlecrystalline silicon. It has not yet been verified on evaporated SPC poly-si films for solar cell applications. Figure 5.10 illustrates the dependence of the specific contact resistance of Al/poly-Si contacts on the Schottky barrier height and the silicon resistivity. As can be seen, c of Al contacts on both n-type and p-type poly-si drops dramatically with decreasing resistivity (i.e., increasing silicon doping density). More specifically, the specific contact resistance values of Al/p + poly-si contacts fall in the p-type barrier height range of ev. The specific contact resistance values of Al/n + poly-si contacts fall in the n-type barrier height range of ev and fit the specific contact resistance curve reported by Trapp [1980] (the corresponding barrier height is unknown). Overall, the Schottky barrier height dependence of c of both types of MS contacts shown in Figure 5.10 agrees with what is reported in the literature. More precisely, the barrier height of Al/p + poly-si contacts is close to the lower bound of the reported values while the barrier height of Al/n + poly-si contacts is close to the upper bound of the reported values. The sum of the p-type and n-type Schottky barrier heights of Al/poly-Si contacts is about 1.1 ev, which is the bandgap of sc-si (Equation 5.5). As discussed in Section and Section 5.3.2, some of the investigated samples are suspected to be heavily oxygen contaminated, giving rise to an abnormal specific contact resistance in terms of the silicon resistivity (doping density). The Schottky barrier heights of those samples are suspected to be altered due to this contamination. Figure 5.11 illustrates the Schottky barrier height and silicon resistivity dependence of those abnormal samples. As can be seen, the c values of Al contacts on heavily O contaminated n-type and p-type poly-si fall in the barrier height region of 0.4 ev (n-type) and ev (p-type), which is very different from the normal Al/Si barrier

101 5 Contact resistance results on uniformly doped poly-si films on glass 91 heights shown in Figure This finding agrees with the speculation discussed in Section and Section Specific contact resistance c (-cm 2 ) Bp =0.4eV <111> Bp =0.3eV <100> Bp =0.2eV <100> Bp =0.2eV <111> Bn =0.6eV <111> Bp =0.4eV <100> Trapp Bn =0.85eV <111> Bn =0.6eV <100> =0.7eV Bn =0.8eV Bn <100> <100> Resistivity of Si layer (m-cm) Figure 5.10: The Schottky barrier height and silicon resistivity dependence of the specific contact resistance of evaporated SPC poly-si films. Each Schottky barrier height curve is labelled with the barrier height value and the silicon crystal orientation. The doping density axis is not shown as both n-type and p-type contacts are plotted together. All the data points are taken from Figure 5.4 and Figure 5.8. Therefore, the error information is not repeated here.

102 5 Contact resistance results on uniformly doped poly-si films on glass Specific contact resistance c (-cm 2 ) Bn =0.4eV <111> Bn =0.3eV <100> Bp =0.5eV Bp =0.6eV <100> <100> Bp =0.7eV Bn =0.4eV <100> <100> Resistivity of Si layer (m-cm) Figure 5.11: The Schottky barrier height and silicon resistivity dependence of the specific contact resistance of evaporated SPC poly-si films. The silicon film is heavily oxygen contaminated. Each Schottky barrier height curve is labelled with the barrier height value and the silicon crystal orientation. The doping density axis is not shown as both n-type and p-type contacts are plotted together. (All the data points are taken from Figure 5.4 and Figure 5.8. Therefore, the error information is not repeated here.) 5.5 Conclusions In this Chapter, Al contacts on uniformly doped n + and p + poly-si films on glass were systematically investigated. These films were deposited via e-beam evaporation and crystallised via SPC. The transmission line models set up at UNSW in the course of this thesis were found to be well suited to determine the contact resistance of evaporated

103 5 Contact resistance results on uniformly doped poly-si films on glass 93 poly-si films on glass. All contacts fabricated were found to be ohmic, both before and after baking. Annealing at low temperatures ( C) massively improved the contact resistance for Al/p + poly-si contacts and Al/SiO x /n + poly-si contacts. Higher baking temperatures ( 300 C) had either no effect on the contact resistance (Al/p + poly-si) or degraded the contact resistance (all other investigated contacts). The Al/SiO x /n + poly-si contact structure was found to improve the contact resistance significantly after sufficient baking as compared to Al/n + poly-si contacts. The trend of the dependence of Al/n + poly-si contact resistance on resistivity (doping density) agreed with the trends obtained on sc-si and LPCVD poly-si materials which were reported in the literature. However similar experiments on Al/p + poly-si contacts revealed a much steeper dependence trend, which implies a different Si surface property from heavily doped p-type sc-si and LPCVD poly-si. The Schottky barrier height is a figure-of-merit of MS contacts. A series of curves representing different Schottky barrier heights were reproduced from the literature and used to fit the measured specific contact resistance of Al contacts on evaporated p + poly-si and n + poly-si in order to determine the barrier heights of Al/poly-Si contacts. The Schottky model and the Bardeen model were employed to discuss and explain the results. It was found that the fitted Schottky barrier heights agree well with those reported in the literature and can be explained with the existing MS contact models. A fraction of the measurements on both types of contacts were found to be abnormal. We believe that this is the result of a heavy oxygen contamination of the poly-si films, whereby this contamination has occurred either during the a-si deposition step and/or the subsequent rapid thermal annealing step. The oxygen contamination caused the MS contact band structure to change. This change can be explained with the MS contact models. Experimental evidence for this change was provided by fitting the measurements with a series of curves representing different Schottky barrier heights.

104 6 Contact resistance results on poly-si thin-film diodes on glass 94 6 Contact resistance results on poly-si thin-film diodes on glass 6.1 Motivation The results from the previous Chapters of this thesis form a sound basis for analysing complete poly-si thin-film diodes. In this Chapter, the contact resistance measurement models and systems established in the course of this thesis are employed to characterise and improve the aluminium contacts to finished poly-si thin-film solar cells (diodes) on glass. The aim is to achieve ohmic contacts to the back surface field (BSF) layers and the emitter layers of the solar cell samples, with sufficiently low specific contact resistance. 6.2 Contacts to the back surface field layer of PLASMA cells Sample preparation In this Section, experiments are performed on PLASMA solar cells. Three samples are used BSPC1, BSPC2 and BSPC3. Each sample has a size of around 5 by 5 cm 2. The general design structure and fabrication processes are very similar to EVA solar cell introduced in Chapter 1, expect that the silicon material is deposited by using PECVD rather than e-beam evaporator. The specific fabrication parameters of the solar cells used in this Section are listed in Table 6.1. PLASMA cells were deposited in amorphous form using PECVD and then crystallised via solid-phase crystallisation (SPC). Emitter, base and BSF layers were all intended to be uniformly doped. After crystallisation, the grain size is in the range of 1-2 μm. Rapid thermal annealing (RTA) and hydrogenation (HYD) were then performed on the cells to improve their electrical properties. The RTA

105 6 Contact resistance results on poly-si thin-film diodes on glass 95 system at UNSW uses halogen lamp arrays to heat the sample in a short period of time in order to activate the dopants as well as passivate point defects in the sample. The hydrogenation process was performed in a parallel-plate rf PECVD system which is located in a cluster tool. The main function of this process is defect passivation. Hydrogenation is a key process of crystalline silicon thin-film solar cell fabrication. It improves the open-circuit voltage of UNSW poly-si thin-film solar cells by a factor of about 2 [Terry 2007]. Table 6.1: Structural parameters of the PLASMA solar cells investigated in this Section. Parameter Details Glass 3 mm (planar, borosilicate) AR coating SiN (~70 nm) Emitter (PECVD) n + (~100 nm, ~ cm -3 P, ~500 /) Base (PECVD) p - (~1200 nm, ~ cm -3 B) BSF (PECVD) p + (~70 nm, ~ cm -3 B, ~2000 /) Crystallisation (SPC) C RTA C Hydrogenation C, direct plasma Formation of the contact resistance structures on PLASMA samples started with a piranha clean, followed by a dip in 5% HF to remove the surface oxide. The resulting surfaces were found to be hydrophobic. The samples were then rinsed for 10 min in DI water, followed by drying with a nitrogen gun. Next, the samples were immediately loaded into the evaporator chamber (no loadlock). No oxide layer was intentionally grown. The chamber was pumped down during about 60 minutes to a pressure of about 10-5 Torr. Then nm thick aluminium was evaporated onto the samples, using resistively heated evaporation from a tungsten boat. The evaporation rate was Å/s. The TLM/CTLM structures were then photolithographically patterned. A mesa etch done by plasma etching (PE) was conducted to constrain the current in the silicon to only flow directly between the contact pads (not necessary for CTLM patterns). In this Section, all contact resistance measurements were performed at room temperature (~300 K) on the back surface field (BSF) layer of PLASMA samples, by using the Kelvin sense measurement system described in Section In order to ensure good measurement precision, the current range used for each measurement

106 6 Contact resistance results on poly-si thin-film diodes on glass 96 covered three orders of magnitude, within the range of 5 A to 100 ma Results Figure 6.1 shows the I-V curves measured from a TLM pattern on the BSF layer of the PLASMA sample BSPC1 (no surface or contact treatment), and the corresponding fitted TLM characteristic curve (inset). The measurement was done by using an in-line TLM pattern which consists of several Al contact bars separated by a resistive poly-si sheet with variable length. A linear least square fit was used to fit the measured data points. Evidently, the contacts are not ohmic or homogeneous and the data points do not show a linear trend. Therefore, in this case the contact resistance can not be obtained via the TLM technique. 23 µm spacing 15 µm spacing 43 µm spacing 64 µm spacing 84 µm spacing 104 µm spacing 124 µm spacing 145 µm spacing 6.E-03 3.E-03 amps 0.E volts E-03-6.E voltage (mv) 0.6 y = x R 2 = spacing (μm) Figure 6.1: I-V curves measured from an in-line TLM pattern on PLASMA sample BSPC1 (no surface or contact treatment). The inset is the corresponding fitted TLM characteristic curve (linear fitting). As shown in Table 6.1, the surface layer was intended to be heavily doped. The results obtained in Chapter 5 showed that Al contacts on heavily doped poly-si are ohmic even without baking. The reason why ohmic contacts cannot be achieved on the virgin BSF

107 6 Contact resistance results on poly-si thin-film diodes on glass 97 layers of PLASMA solar cells is believed to be due to the hydrogenation process. As a plasma process, hydrogenation is known to alter the silicon surface properties in two ways. First is surface damage. During the hydrogenation process, particle bombardment occurs which may introduce heavy lattice damage in an up to 30 nm thick surface layer [Jeng 1988, Neamen 2003]. Second is dopant neutralisation due to hydrogenation, which strongly decreases the doping density of the surface layer [Jeng 1988]. Research in our group has shown that boron is much more easily neutralised than phosphorus [Widenborg 2007]. Figure 6.2 shows the measured I-V curves and the corresponding fitted TLM characteristic curve (inset) from an in-line TLM pattern on a non-hydrogenated PLASMA sample (BSPC2). This sample has the same structure and similar fabrication parameters as BSPC1, but no hydrogenation process was conducted. Evidently, this sample exhibits ohmic and homogeneous contacts as well as a linear characteristic curve without any contact or surface treatment. The measured specific contact resistances on different positions of this sample are in the order of 10-4 cm 2, as listed in Table µm spacing 25 µm spacing 45.5 µm spacing 66.5 µm spacing 86.5 µm spacing µm spacing 127 µm spacing 147 µm spacing 6.E-03 3.E-03 amps 0.E volts E voltage(mv) y = x R 2 = E spacing (μm) Figure 6.2: I-V curves measured from an in-line TLM pattern on PLASMA sample BSPC2 (no hydrogenation, no surface or contact treatment). The inset is the corresponding fitted TLM characteristic curve (linear fitting), giving c = cm 2.

108 6 Contact resistance results on poly-si thin-film diodes on glass 98 Table 6.2: Specific contact resistances and sheet resistances measured on different BSF positions of the non-hydrogenated PLASMA sample BSPC2, using TLM and CTLM structures. Pattern R sheet (/) c (cm 2 ) Current range (μa) TLM TLM CTLM CTLM CTLM Two approaches were used to solve hydrogenation-induced surface degradation. One is baking of the contacts. During thermal annealing, aluminium atoms diffuse into silicon and react with Si atoms. This process happens more quickly where there is a high defect density [Neamen 2003]. As a large defect density is introduced to the solar cell surface during the hydrogenation process, it is believed that low temperature baking (< 300 C) can cause the aluminium to penetrate through the heavily damaged surface layer and form ohmic contacts to the lightly damaged Si layer underneath. After completion of the first measurements (Figure 6.1), sample BSPC1 was sequentially baked at 150, 200, 250 and then 300 C in an N 2 purged oven. The duration of each bake was 30 minutes. Figure 6.3(a) (d) are a series of figures showing how the contacts are dramatically improved via baking. After annealing at 250 C for 30 min, the R 2 value of the TLM characteristic curve approaches 0.99, which is close to the R 2 values of Al contacts on Si wafers and poly-si thin-film samples investigated in the previous Chapters. The contacts become ohmic and homogeneous enough to perform a reliable TLM measurement. Annealing at 300 C for 30 min further increases the homogeneity of the contacts and lowers the contact resistance. However, high temperature annealing (> 300 C) degrades the electrical performance of the device due to loss of hydrogen [Terry 2007]. Hence, 250 C is the optimum baking temperature for minimising hydrogenation -induced Si surface damage in PLASMA cells.

109 6 Contact resistance results on poly-si thin-film diodes on glass µm spacing 23 µm spacing 43 µm spacing 64 µm spacing 84 µm spacing 104 µm spacing 124 µm spacing 145 µm spacing 6.E-03 3.E-03 amps E volts 15 µm spacing 23 µm spacing 43 µm spacing 64 µm spacing 84 µm spacing 104 µm spacing 124 µm spacing 145 µm spacing -3.E-03-6.E-03 6.E-03 3.E-03 0.E volts 15 µm spacing 23 µm spacing 43 µm spacing 64 µm spacing 84 µm spacing 104 µm spacing 124 µm spacing 145 µm spacing -3.E-03-6.E-03 6.E-03 3.E-03 0.E+00 amps (a) (b) volts 15 µm spacing 23 µm spacing 43 µm spacing 64 µm spacing 84 µm spacing 104 µm spacing 124 µm spacing 145 µm spacing -3.E-03-6.E-03 6.E-03 3.E-03-3.E-03-6.E-03 amps amps 0.E volts (c) voltage (mv) y = x R 2 = spacing (μm) voltage (mv) y = x R 2 = spacing (μm) voltage (mv) voltage(mv) y = x R 2 = spacing (μm) y = x R 2 = spacing (μm) (d) Figure 6.3: Measured I-V curves from in-line TLM patterns on the BSF layer of sample BSPC1 and the corresponding fitted TLM characteristic curves of the contacts after baking for 30 min at (a) 150 C, c = not measurable; (b) 200 C, c = cm 2 ; (c) 250 C, c = cm 2 ; (d) 300 C, c = cm 2.

110 6 Contact resistance results on poly-si thin-film diodes on glass 100 In the literature it is reported that, during plasma processing, the first several nanometres of silicon are most heavily damaged and dopant-neutralised [Graves 1994]. Therefore, the other approach is to remove a thin surface layer so that ohmic contacts can be formed on less heavily damaged silicon material. PLASMA sample BSPC3 was cut into several small samples. Before performing the routine cleaning and the TLM patterning processes, some of these samples were wet-chemically etched using coloured HF for different durations. The etch rate is around 15 Å/s for our poly-si (without seed layer). Then all samples were cleaned and TLM/CTLM patterned. After the first measurement, the contacts were baked at 250 C for 30 min in a N 2 purged oven. Figure 6.4 illustrates the typical I-V curves measured from one CTLM pattern on the BSF layer of one of these samples (a) with and (b) without surface treatment before contact annealing. As can be seen, the contacts become ohmic and homogeneous after the surface treatment. 5 µm spacing 10 µm spacing 15 µm spacing 20 µm spacing 25 µm spacing 30 µm spacing 6.0E-2 4.0E-2 2.0E-2 amps 0.0E volts -2.0E-2-4.0E-2-6.0E-2 (a) All coloured HF solutions used in this Chapter were made using the same recipe.

111 6 Contact resistance results on poly-si thin-film diodes on glass µm spacing 10 µm spacing 15 µm spacing 20 µm spacing 25 µm spacing 30 µm spacing 6.0E-2 4.0E-2 2.0E-2 amps 0.0E volts -2.0E-2-4.0E-2-6.0E-2 (b) Figure 6.4: The measured I-V curves from the CTLM patterns on the BSF layers of two samples cut from BSPC3, (a) before and (b) after coloured HF etching of the surface for 5 sec. The improvement of the specific contact resistance c arising from baking and coloured HF etching is compared in Figure 6.5. Due to difficulties with precisely measuring the active layer thickness, the sheet resistance is used instead of resistivity to evaluate the doping density. The thickness of the BSF layer is believed to be laterally uniform. Note that the peak doping level occurs near the surface and is constant over a certain thickness but drops abruptly when approaching the p-n junction. Therefore, the etching duration must be optimised to a point that the most heavily damaged layer is removed while high surface doping density is still maintained. As can be seen in Figure 6.5, both baking and coloured HF etching improve c to values in the order of 10-5 cm 2. On average, 10 seconds of etching yields the lowest c of around cm 2. With increasing etching duration, the sheet resistance increases as the thickness of the BSF layer decreases. After etching for 25 sec, c becomes higher as the surface is close to the p-n junction and with a lower doping density. After the etched samples were baked at 250 C for 30 min, the specific contact resistance became too low to be measurable and hence is not shown.

112 6 Contact resistance results on poly-si thin-film diodes on glass 102 Specific contact resistance c (-cm 2 ) C baking for 30m 5s coloured HF etching 10s coloured HF etching 25s coloured HF etching k 1.6k 2.0k 2.4k 8.0k 12.0k 16.0k Sheet resistance (/) Figure 6.5: The specific contact resistances of Al on the BSF layers of PLASMA samples cut from BSPC3. The error bars represent the 95% confidence interval. In conclusion, both approaches (surface etching and contact annealing) can solve the contact problem arising from hydrogenation-induced surface degradation, giving ohmic contacts and sufficiently low contact resistances. This finding is used for guiding contact resistance experiments on other types of UNSW poly-si thin-film solar cells.

113 6 Contact resistance results on poly-si thin-film diodes on glass Contacts to the back surface field layer of EVA cells In this Section, an EVA solar cell sample (EVA1) is investigated. The size was around 5 by 5 cm 2. The general design structure and fabrication processes have been introduced in Chapter 1. The specific fabrication parameters of the solar cell used in this Section are listed in Table 6.3. EVA solar cells are deposited using e-beam evaporation and crystallised via SPC. Emitter, base and BSF layers are all intended to be uniformly doped. After crystallisation, the grain size is in the range of μm [Song 2006]. Similar to PLASMA cells, RTA and HYD were then performed on the cells to improve their electrical properties. Table 6.3: Structural parameters of the EVA solar cells investigated in this Section. Parameter Details Glass 3 mm (planar, borosilicate) AR coating SiN (~70 nm) Emitter (e-beam) n + (~100 nm, ~ cm -3 P) Base (e-beam) p - (~1500 nm, ~ cm -3 B) BSF (e-beam) p + (~100 nm, ~ cm -3 B, ~1500 /) Crystallisation (SPC) ~24 about 600 C RTA C Hydrogenation C, remote plasma Formation of the contact resistance structures on the BSF layers of EVA samples and the contact resistance measurement are exactly the same as PLASMA samples. Again, the I-V measurements on the untreated surface and the unbaked contacts indicate non-ohmic behaviour due to hydrogenation-induced surface degradation, as shown in Figure 6.6(a). However, the homogeneity of these contacts is much better than that of the PLASMA sample shown in Figure 6.1. This is believed to be due to the different plasma conditions used in the hydrogenation process. After baking at 250 C for 30 min in a N 2 purged oven these contacts were ohmic, as can be seen in Figure 6.6(b). It was also found that coloured HF etching can make the contacts ohmic.

114 6 Contact resistance results on poly-si thin-film diodes on glass µm spacing 10 µm spacing 15 µm spacing 20 µm spacing 25 µm spacing 30 µm spacing 6.E-02 4.E-02 2.E-02 amps 0.E volts -2.E-02-4.E-02-6.E-02 (a) 5 µm spacing 10 µm spacing 15 µm spacing 20 µm spacing 25 µm spacing 30 µm spacing 6.E-02 4.E-02 2.E-02 amps 0.E volts -2.E-02-4.E-02-6.E-02 (b) Figure 6.6: Measured I-V curves from a CTLM pattern on the BSF layer of an EVA sample cut from EVA1, (a) before and (b) after baking the contacts at 250 C for 30 min. Figure 6.7 illustrates the specific contact resistance c of Al contacts to the p-type BSF layers of EVA samples. These samples were cut from sample EVA1. The effects of baking and coloured HF etching (5 sec and 10 sec, before and after baking) are

115 6 Contact resistance results on poly-si thin-film diodes on glass 105 compared. All bakes were conducted at 250 C for 30 min in a N 2 purged oven. Generally, c drops with decreasing sheet resistance. Again, it is found that either contact annealing or surface etching can eliminate the contact anomaly arising from hydrogenation-induced surface degradation. A specific contact resistance of below 10-4 cm 2 can be achieved via baking and/or surface treatment. Specific contact resistance c (-cm 2 ) C baking for 30m 5s coloured HF etching 5s coloured HF etching + bake 10s coloured HF etching 10s coloured HF etching + bake Sheet resistance (/) Figure 6.7: Measured specific contact resistances of Al contacts to the BSF layers of EVA samples cut from EVA1, after different surface or contact treatments. The error bars represent the 95% confidence interval.

116 6 Contact resistance results on poly-si thin-film diodes on glass Contacts to the back surface field layer of ALICIA cells In this Section, experiments were performed on ALICIA solar cells. Two samples were used IAD1 and IAD2. Each sample was 5 by 5 cm 2. The general design structure and fabrication processes have been introduced in Chapter 1. The specific fabrication parameters of the solar cells used in this Section are listed in Table 6.4. ALICIA solar cells are deposited using e-beam evaporation. However, in contrast to EVA and PLASMA cells, ALICIA cells are epitaxially grown on a seed layer using the IAD (Ion-Assisted Deposition) technology. The seed layer on the SiN-coated glass is made by AIC (Aluminium-Induced Crystallisation) of a-si. The grain size of ALICIA material is in the range of m [Aberle 2005]. Then, RTA and HYD are performed on the solar cells to improve their electrical properties. Note that a standard ALICIA cell has an n-type BSF, an n-type base, and a p-type emitter. Table 6.4: Structural parameters of the ALICIA solar cells investigated in this Section. Parameter Details Glass 3 mm (planar or textured, borosilicate) AR coating SiN (~80 nm) Seed layer (AIC) p + (~75nm, ~ cm -3 Al) Emitter (IAD) p + (~50 nm, ~ cm -3 Ga) Base (IAD) n - (~1200 nm, ~ cm -3 P) BSF (IAD) n + (~80 nm, up to cm -3 P at the surface, ~ /) RTA C Hydrogenation C, remote plasma Formation of the contact resistance structures on the BSF layers of ALICIA samples and the contact resistance measurements are exactly the same as for the previous two types of solar cells. In contrast to the findings on PLASMA and EVA samples, the I-V measurements from the CTLM patterns on the BSF layers of samples IAD1 and IAD2 (no surface etching or contact baking), shown in Figure 6.8(a) and (b), indicate a nearly ohmic property. The linearity of these curves is substantially better than that of PLASMA and EVA samples. This is believed to be due to two factors. First, a remote plasma was used in the hydrogenation process instead of the more energetic direct

117 6 Contact resistance results on poly-si thin-film diodes on glass 107 plasma used for PLASMA cells. Therefore, the ion bombardment during the hydrogenation process was diminished. Second, as mentioned in Section 6.2.2, the dopant neutralisation effect is much weaker for phosphorus than for boron. As a result of these two factors, the hydrogenation process induces only a slight degradation of the n + doped BSF layer of ALICIA cells. Therefore, ohmic contacts immediately exist after Al deposition and there is no need for resorting to any surface or contact treatment. 10 µm spacing 20 µm spacing 30 µm spacing 40 µm spacing 50 µm spacing 60 µm spacing 6.E-03 4.E-03 2.E-03 amps 0.E volts -2.E-03-4.E-03-6.E-03 (a) 10 µm spacing 20 µm spacing 30 µm spacing 40 µm spacing 50 µm spacing 60 µm spacing 6.E-03 4.E-03 2.E-03 amps 0.E volts -2.E-03-4.E-03-6.E-03 (b) Figure 6.8: Measured I-V curves from a CTLM pattern on the BSF layer of ALICIA sample (a) IAD1 and (b) IAD2 (no contact baking or surface etching).

118 6 Contact resistance results on poly-si thin-film diodes on glass 108 After the first contact resistance measurement, sample IAD2 was baked for 30 min at about 240 C in a N 2 purged oven and sample IAD1 was Al-stripped to receive the surface treatment. After surface cleaning and a 5% HF dip, sample IAD1 was then etched in coloured HF solution for 30 sec. Then, it was metallised and CTLM patterned again. Due to the larger grains (smaller grain boundary density), the Si etch rate in coloured HF was found to be much lower for ALICIA cells than for PLASMA and EVA cells. After 30 sec of etching, the average sheet resistance only increased by around 20%, from 560 / to 670 /, which implies that the BSF layer was only slightly thinned. Figure 6.9(a) and (b) illustrate the I-V measurements from a CTLM pattern on each ALICIA sample. Evidently, the I-V curves become non-ohmic as compared to Figure 6.8. In contrast to the results on PLASMA and EVA samples, baking and surface etching were found to be detrimental to the contacts on ALICIA BSF layers (which have an Al/n + poly-si contact structure). The reason why baking deteriorates the BSF contacts of ALICIA samples is believed to be due to the reaction between the Al layer and the n-type BSF layer. As discussed in Chapter 5, annealing of Al/n-Si contacts may cause Al to introduce ionised acceptor atoms at the n-si surface and lead to an Al/p-Si/n-Si contact structure which increases the contact resistance. The higher the annealing temperature, the more severely the contact is degraded. And according to SIMS measurements on ALICIA solar cells, the BSF surface doping density is very low, of the order of cm -3 [Terry 2007]. Therefore, 240 C baking for 30 min may introduce sufficient thermal budget to change the contacts qualitatively, i.e., lose the ohmic property. Again, according to SIMS measurements, the doping density below the surface of ALICIA cells is not uniform but decreases steeply in the first 100 nm. This is the believed reason why removing a thin layer from the surface leads to non-ohmic and inhomogeneous contacts as the surface doping concentration becomes lower. Comparing Figure 6.9(a) and (b), it can be found that surface etching degrades the contacts more severely than baking. Note that the resistance from every I-V measurement consists of the contact resistance R c and the resistance of BSF layer sheet R semi. The I-V curves in (a) twist with each other, which implies that the R c becomes so high that it dominates the total measured resistance instead of the R semi. After the measurement in Figure 6.9(a), sample IAD1 was also The used oven failed to reach the intended baking temperature (250 C) during the baking process for unknown reason.

119 6 Contact resistance results on poly-si thin-film diodes on glass 109 baked at 240 C for 30 min. The contact was not improved as expected and hence the results are not shown here. 10 µm spacing 20 µm spacing 30 µm spacing 40 µm spacing 50 µm spacing 60 µm spacing 6.E-03 4.E-03 2.E-03 amps 0.E volts -2.E-03-4.E-03-6.E-03 (a) 10 µm spacing 20 µm spacing 30 µm spacing 40 µm spacing 50 µm spacing 60 µm spacing 6.E-03 4.E-03 2.E-03 amps 0.E volts -2.E-03-4.E-03-6.E-03 (b) Figure 6.9: Measured I-V curves from a CTLM pattern on the BSF layer of ALICIA sample (a) IAD1, after 30 sec coloured HF etching of the surface; and (b) IAD2, after baking the contacts at 240 C for 30 min.

120 6 Contact resistance results on poly-si thin-film diodes on glass 110 The measured specific contact resistances c of samples IAD1 and IAD2, before and after baking, are presented in Figure Evidently, c drops with the decreasing sheet resistance. It can be seen that baking not only increases the c values but also causes larger error bars due to the fact that the TLM technique is unreliable for non-ohmic contacts. Generally, owing to the different surface doping levels, the specific contact resistance of as-metallised ALICIA BSF layers is of the order of 10-3 cm 2. Due to the severely degraded I-V characteristics of sample IAD1 after surface etching, the contact resistance could not be measured and hence is not shown. Specific contact resistance c (-cm 2 ) 10-1 IAD1 as metallised IAD2 as metallised IAD2 after baking Sheet resistance (/) Figure 6.10: Measured specific contact resistances of Al contacts on the BSF layers of ALICIA solar cell samples IAD1 and IAD2. The error bars represent the 95% confidence interval.

121 6 Contact resistance results on poly-si thin-film diodes on glass Contacts to the emitter layer of PLASMA cells In this Section, PLASMA solar cell sample BSPC3 is investigated. Its structure is shown in Table 6.1 (see Section 6.2). All samples used in this Section were cut from this 5 by 5 cm 2 sample (done in Section 6.2). The sample preparation steps are as follows: The BSF and base layer of the sample were etched off by using plasma etching (PE). A hot-probe station was used to detect the polarity of the remaining layer. The reason of using PE is to i) mimic the standard solar cell metallisation processes which was introduced in Chapter 1; ii) investigate the impact of PE on the contact resistance of the emitter layer. The formation of the CTLM patterns on the emitter layer is exactly the same as on the BSF layer. In order to find out if hydrogenation and/or plasma etching damages the surface, some samples were etched in coloured HF solution for 20 seconds prior to the metallisation step. A top view of a finished sample is shown in Figure The dark areas are the aluminium patterns (CTLM and the others). Al thickness is around 300 nm. The yellowish area is n-type poly-si (emitter layer), with a thickness in the centre of the glass piece of around 100 nm. Due to inhomogeneity issues with our plasma etching process, the silicon was etched more quickly in the periphery than in the centre of the substrate. As a result, there is a Si thickness slope towards the edges of the glass after PE. A cross-sectional sketch of the samples is shown in Figure 6.12.

122 6 Contact resistance results on poly-si thin-film diodes on glass 112 c b a Figure 6.11: Photograph (top view) of the CTLM and other Al patterns (dark) on a plasma etched PLASMA sample. The glass is slightly wrinkled. The yellowish layer is the emitter. The three CTLM patterns indicated by the arrows correspond to the three patterns depicted in Figure CTLM pattern a c b poly-si SiN Glass Figure 6.12: Cross-sectional sketch of the sample shown in Figure 6.11 (not to scale). The three labelled CTLM patterns correspond to the three patterns indicated in Figure 6.11 and the three graphs in Figure Depending on exactly where the CTLM patterns sit on the emitter layer, the resulting I-V characteristics are different, as shown in Figure 6.13(a), (b) and (c). Each CTLM pattern (a, b and c as shown in the two figures above) yields four valid I-V curves: (a) for the pattern sitting entirely on the slope between poly-si and glass, the contacts are all ohmic; (b) for the pattern sitting partly on the slope, some contacts become non-ohmic; (c) for the pattern sitting beyond the slope but near the centre, the contacts are all non-ohmic. This phenomenon is believed to be due to the varied doping density