Field effect transistor sensors for liquid media

Transcription

1 Field effect transistor sensors for liquid media Water micropollutants: from detection to removal November 26-28, 2018 Orléans 1

2 OUTLINE Some liquid sensors Dual Gate FET Examples Process of Dual Gate TFT Theory Characterization Tests for PH measurement Prospects 2

3 Water sensors Some measure parameter Temperature ph conductivity dissolved oxygen turbidity.. Sensor principle Thermistor Redox sensor Metallic electrodes Electrochemical or optical Optical measurement of diffuse light 3

4 PH sensors Equation : Ox1 + Réd2 <-> Réd1 + Ox2 (Nernst equation) PdO + 2H + +2e Pd + H 2 O. Y. Qin et al. / Sensors and Actuators B 255 (2018)

5 Sensors objective Developing high sensitive sensors from: Electronic device Compatible technologies Easy to functionalize Field effect transistors: Detection of charges linked to the surface Easy measurement Numerous possibilities for the technology Low cost and high number of devices Specialized in silicon based technologies: Thin film devices Low temperature process Good electrical properties TFT as chemical sensors: Different technologies Compatibility with chemical and biological functionalization Possibility to integrate microfluidic Usable in liquid media Highly sensitive devices 5

6 Main principle silicon based sensors ISFET : Ions Sensitive Field Effect Transistors ph sensor ph pzc : isoelectric ph ph variation : shift of the transfer characteristic and of the threshold voltage Sensitivity: S= dψ dphs = -2,3 kt q α S= 59 mv/ph (Nernst equation) Well-know device with main advantages Limitation of the sensitivity 6

7 Id (µa) DVgs (V) Main principle silicon based sensors SGFET : Suspended Gate Field effect Transistor MOS or TFT structure With suspended gate Sub-Micron Gap ( nm) Compatible with measurements in liquid media ph sensor (Si 3 N 4 layer) ph = 11.4 / 10.1 / 7.6 / 4.6 / 3 ph Sensitivity : DV gs /ph = 255 mv / ph Vgs (V) ph Biosensors Chemical and biological functionalization Antigens/Antibodies 7

8 Microfluidics integration With PDMS microchannels Control of the volume Continuous flow Same sensitivity With integrated microchannels (front or rear face) Gate Inlet/Outlet Si-Poly Gate Source/Drain Contacts (source and drain) Microchannel Sensitivity 290mV/pH Sensitivity to ph 5 10 ph 8

9 OUTLINE Some liquid sensors Dual Gate FET Examples Process of Dual Gate TFT Theory Characterization Tests for PH measurement Prospects 9

10 DGFET : Example 1 Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography Lim et al, Science and Technology of Advanced Materials, 2017 VOL. 18, NO. 1, nanoimprinted SiNW for the active layer Silicon dioxide Extended gate High sensitivity 10

11 DGFET : Example 2 Dual-Gate Organic Field-Effect Transistors as Potentiometric Sensors in Aqueous Solution By Mark-Jan Spijkman, et al, Adv. Funct. Mater. 2010,20, PTAA stands for the organic semiconductor polytriaryalamine. The top dielectric consists of a stack of poly-isobutylmethacrylate (PIBMA) and the Teflon derivative AF Sensitivity to ph versus coupling capacitance 11

12 OUTLINE Some liquid sensors Dual Gate FET Examples Process of Dual Gate TFT Theory Characterization Tests for PH measurement Prospects 12

13 Dual Gate TFT with polysilicon SiO 2 deposition Wafer insulation (silicon oxide) Process: APCVD Gas: Silane/Oxygene Temperature: 420 C Deposition rate: 29 nm/min Thickness: 800 nm Silicon Wafer 13

14 Dual Gate TFT with polysilicon SF 6 SF 6 SF 6 Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Doped polysilicon deposition Process: LPCVD Gas: Silane, phosphore pressure: 90 Pa Deposition rate: 5 nm/min thickness: 300 nm Dry etching Process : Plasma power: 30w Flow rate: 30sccm pressure: 4 Pa Etching rate: ~150nm/min 14

15 Dual Gate TFT with polysilicon Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Doped polysilicon deposition Process : LPCVD Gas: Silane, phosphore Pressure: 90 Pa Deposition rate : 5 nm/min thickness : 300 nm Dry etching Process : Plasma power : 30w Flow rate: 30sccm Pressure: 4 Pa Etching rate: environ 150nm/min 15

16 Dual Gate TFT with polysilicon Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Si 3 N 4 Deposition Process : LPCVD Gaz: Silane/Ammoniac Pressure: 60 Pa Temperature: 725 C Deposition rate : 4 nm/min thickness : Variable 16

17 Dual Gate TFT with polysilicon Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Deposition of Si 3 N 4 Process : LPCVD Gas: Silane/NH 3 Pressure: 60 Pa Temperature: 725 C Deposition rate : 4 nm/min thickness : Variable Deposition of SiO 2 Process : APCVD Gas: Silane/Oxygène Temperature: 420 C Deposition rate : 29 nm/min thickness : Variable 17

18 Dual Gate TFT with polysilicon Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Wet etching of SiO 2 Process : Solution de BHF Dry etching Process : Plasma Power : 30 W Flow rate: 10 sccm Pressure: 1 Pa Etching rate : environ 15nm/min 18

19 Dual Gate TFT with polysilicon D 19 S Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer G

20 Dual Gate TFT with polysilicon D 20 S Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer G Doped silicon deposition Process: LPCVD Gas: Silane, phosphore Pressure: 90 Pa Deposition rate : 5 nm/min thickness : 300 nm

21 Dual Gate TFT with polysilicon D S Poly-silicon Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer G Poly-silicon deposition Process: LPCVD Gas: Silane Pressure: 90 Pa Deposition rate : 5 nm/min thickness : 100 nm 21

22 I D (A) First electrical measurement 20,0µ 15,0µ Before encapsulation After encapsulation After Forming Gas 10,0µ 5,0µ V GS (V) 22

23 Dual Gate TFT with polysilicon Poly-silicon Insulator layer (SiO 2 ) Insulator layer (Si 3 N 4 ) Highly doped polysilicon Wafer insulation (silicon oxide) Silicon Wafer Si 3 N 4 deposition Process: LPCVD Gas: Silane/Amonia Pressure: 60 Pa Temperature: 725 C Deposition rate : 4 nm/min thickness : Variable SiO 2 deposition Process: APCVD Gas: Silane/Oxygène Temperature: 420 C Deposition rate : 29 nm/min thickness : Variable 23

24 Dual Gate TFT with polysilicon Wet etching of SiO 2 (Nitrure de silicium) Process : Solution de BHF Dry etching Process : Plasma Power : 30 W Flow rate: 10 sccm Pressure: 1 Pa Etching rate : environ 15nm/min 24 11

25 Optimization of the bottom dielectric 1 rst Goal : decrease of the threshold voltage for bottom gate structure Test with several bottom gate insulators Thicknesses 40 V TH (V) Best result Low threshold voltage Low dispersion in data point nm/90 nm 80 nm/50 nm 80 nm/20 nm 50 nm/50 nm Thickness SiO 2 /Si 3 N 4 25

26 I D (A) Final transfer characteristic 20,0µ 15,0µ Before encapsulation After encapsulation After Forming Gas 10,0µ 5,0µ V GS (V) 26

27 OUTLINE Some liquid sensors Dual Gate FET Examples Process of Dual Gate TFT Theory Characterization Tests for PH measurement Prospects 27

28 I D (A) Modeling V DS = 1V n e 10,0µ ID (A) Model 5,0µ V G,Bottom =10 V V G,top = 0V V GS -V th (V) V G,Bottom = 0V - V G,top = 0V 28

29 Amplification values Theoretical amplification calculated from capacitance amplification : Real amplification (for TFT): C Top C Bottom Larger grains Smaller grains µ Bottom µ Top I D = W L V DS µ Bottom C Bottom V G,Bottom V th,bottom + µ Top C Top V G,Top V th,top I D = W L V DS µ Bottom C Bottom V G,Bottom V th,total V th,total = V th,bottom µ Top C Top µ Bottom C Bottom V G,Top V th,top V th,total = µ Top C Top µ Bottom C Bottom V th,top Sensitivity 29

30 ID (A) Modeling V DS = 1V n e 8,0x10-6 6,0x10-6 V G,top = 2V 4,0x10-6 V G,Bottom =10 V, V G,top = 2V 2,0x10-6 n e 0, Vg bottom (V) V G,top = 0V V G,Bottom = 0V, V G,top = 0V 30

31 Dual gate operation Material e r Thickness (nm) SiO Si3N SiO ,5 Active layer : undoped polysilicon 100 nm Gate layers : highly doped polysilicon C Bottom = 4,4 x 10-8 F/cm 2 Theoretical amplification: Top gate insulator Si 3 N 4, 25 nm SiO 2, 25 nm C Top = 8,8 x 10-8 F/cm 2 C Top C Bottom = 2 SiO 2, 5,5 nm (native oxide) C Top = 6,2 x 10-7 F/cm 2 C Top C Bottom = 14 31

32 Drain Current (A) Drain Current (A) Water measurement Droplet Polarization 1,6x10-6 1,4x10-6 1,2x10-6 1,0x10-6 Vtop=0V Vtop=0,1V Vtop=0,2V Vtop=0,3V Vtop=0,4V 8,5x10-7 8,0x10-7 Vtop=0V Vtop=0,1V Vtop=0,2V Vtop=0,3V Vtop=0,4V 8,0x10-7 6,0x10-7 7,5x10-7 4,0x10-7 2,0x10-7 7,0x Bottom gate voltage (V) 16,0 16,5 17,0 Bottom gate voltage (V) 32

33 I D (A) PH measurement (C top ->5,5nm) V Gbottom (V) 3,0x10-6 2,5x10-6 2,0x10-6 PH µA 1µA 1098 mv/ph 1,5x ,0x10-6 5,0x10-7 0, V GS (V) ph 853 mv/ph Amplification factor > 14 33

34 Top gate threshold voltage Possibilities to decrease the top gate threshold voltage Decrease the top insulator thickness Limitations due to electrical insulation Increase of the quality of the interface between silicon dioxide and polysilicon Optimization already done Increase of the quality of polysilicon layer Optimization already done (low temperature process) Many traps at grain boundaries and between interfaces High threshold voltage Increase the doping level of polysilicon Modification of the transfer characteristic Increase the conductance 34

35 I D (µa) I D (µa) TFT with low doped polysilicon Active layer : Polysilicon deposited from silane by LPCVD In-situ doping with phosphine (control of the ratio of gases) Characterization versus Bottom gate Field effet Channel conductance Low On/off ratio Not important for sensing 0,30 0,28 0,55 0,50 0,45 0,40 0,35 0,30 0,25 0,20 0,15 0, V GBottom (V) Comparison Top gate versus Bottom gate transfer characteristics 0,26 0,24 0,22 0,20 V GTop V GTop compatible with tests in liquid 0,18 V GBottom 0,16 0,14 0,0 0,5 1,0 1,5 2,0 V G (V) 35

36 DV (V) I D (µa) Dual Gate TFT with low doped polysilicon Transfer characteristics versus V GBottom With different values of V GTop 0,50 0,45 0,40 0,35 0,30 V GTop from 0 to 2V Large increase of the current due to the top channel 0,25 0,20 0, , V GBottom (V) 6 I D = 225 na Voltage shift with fixed I DS 4 The slope gives the amplification ratio 2 I D = 325 na 0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 V Gtop (V) 36

37 I D (µa) Measurements in liquids Top Gate with polarized droplet Metallic electrode (Ti/Au) for Top gate Comparison of transfer characteristics With metallic Gate (Al) With liquid Gate 0,24 0,22 0,20 with drop at ph 7 with aluminum top gate 0,18 Good correlation showing the good functioning in liquid media 0,16-0,2 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 V Drop (V) 37

38 DV (V) Amplification (DV/DV GTop ) Amplification versus polarization I D = 225 na I D = 225 na I D = 325 na 0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 V Gtop (V) 2 0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 V GTop (V) I D = 325 na The amplification value increases with V GTop Top channel formation The amplification value is higher at low V GBottom Top channel more influent than Bottom channel Measured amplification >> Calculated amplification (C Top /C Bottom ) 38

39 Amplification Amplification (DV/DV GTop ) Comparison of Amplification values Theoretical values Measured values V GBottom around 0V V GBottom around 10V V GBottom around 6V 0 0,0 0,5 1,0 1,5 2,0 V GTop (V) ,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 V GTop (V) I D = 225 na I D = 325 na Amplification range consistent with theory Increase of the amplification with polysilicon layers 39

40 Conclusion : Measurements in liquids Several tests with solutions with various ph values Sensitivity above the Nernst value > 59 mv/ph Highly dependent on polarization Examples : The sensitivity is higher for low bottom gate voltage (under 4V) and increases with the top gate voltage. consistent with previous calculated and measured amplification values in dual gate configuration Amplification factor with : V GBottom around 3 V GTop = 0.75V 3.5 ph sensitivity around 200 mv/ph Amplification with : V GBottom around 3 V GTop = 0.5 V 2.6 around 150 mv/ph 40

41 Prospects :Applications to biodetection Very promising results with ph Application to bio elements Integration of nanomaterials on the top surface Nanowires, nanotubes, nanocarbons (porous) Create a structure based on Extended gate TFT Increase the surface And interactions with biomolecules 41

42 Acknowledgment : ANR PlasBioSens Sensor for biodetection Easy measurement Integrated Highly sensitive High selectivity Electronic detection Sensor sensitivity Surface Nanomaterials Functionalization: Chemical Biological 42

43 43 Thank you for your attention

44 DGFET : Example 1 A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen Lee et al, Nanoscale 7(40):16789, 2015 SOI (Silicon on Insulator) for the active layer Silicon dioxide a s insulator Extended gate Application to biosensing Antigen / Antibody links 44

45 Dual Gate TFT with polysilicon Final structure External top gate contact Deposition of a top gate contact (aluminum) Capacitive amplification Top gate Bottom gate Dual gate Characterization Characterization with liquid (ph sensor) : with deported electrode (Au/Ti) 45

46 I DS (µa) I D (µa) Characterization : Bottom gate Transfer characteristic Dual Gate Characteristics 5,0 4,5 4,0 V DS = 1V 5 4 3,5 V Gtop = 0 to 2 V 3,0 3 2,5 2,0 1,5 1, V 0V 0,5 0, V GS (V) V GS (V) Mobility µ FE (cm2/v.s) Threshold voltage V th (V) 12,5 10 I DS with V GTop 46

47 DV (V) Dual Gate Characterization I DS fixed to 2 µa or 3 µa V For each V GTop : V 1 = V GBottom (I DS =2 µa) V 2 = V GBottom (I DS =3 µa) V 1 13 Slope = 1 Effect for V GTop > 1V ,0 0,5 1,0 1,5 2,0 V GTop (V) Slope = 1 DV = DV GTop No capacitance amplification Potential shift Top Gate threshold voltage to high 47