SUSPENDED THERMAL OXIDE ISOLATION FOR ACTUATION AND SMALL CURRENT MEASUREMENT IN MEMS

Transcription

1 SUSPENDED THERMAL OXIDE ISOLATION FOR ACTUATION AND SMALL CURRENT MEASUREMENT IN MEMS A Dissertation Presented to the Faculty of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Russell Y. Webb January 2000

2 2000 Russell Y. Webb

3 SUSPENDED THERMAL OXIDE ISOLATION FOR ACTUATION AND SMALL CURRENT MEASUREMENT IN MEMS Russell Y. Webb, Ph.D. Cornell University 2000 A technique for fabricating high-aspect-ratio, single-crystal silicon (SCS) microelectromechanical systems (MEMS) with integrated, suspended thermal oxide electrical isolation segments was developed and characterized. Maintaining a planar wafer and using low temperature processing after the trench oxidation allows this MEMS isolation process to be integrated with other technologies including IC fabrication. Creating isolation, metallization, and contacts on the same scale as the micron wide SCS beams that they isolate provides a flexible solution to the long standing problem of isolation in MEMS. The unique capabilities of this process were demonstrated by fabricating and characterizing integrated electrometer devices and distributed actuators. The charge integrating and potential sensing of the electrometer demonstrate high resistance isolation (10 PΩ) and high input resistance sensing, while the distributed actuator demonstrates large motion and multiple potentials on a single structure. The process is derived from SCREAM [Shaw, 1994]. Released isolation segments and Al-Si contacts allow electronics to be embedded within single crystal silicon (SCS) MEMS and silicon beams to be used for springs and actuators. Capacitance, leakage current, and breakdown voltage are measured and discussed. After discussing

4 fabrication, the mechanical, thermal, and electrical characteristics are described and example devices explored. The isolation technology presented here enables more complex designs through lower parasitics, integration of electronics, multiple potentials within one SCS structure, and decoupling mechanical and electrical energy. Devices using suspended thermal oxide isolation feature improved reliability and robustness, lower stress, less signal cross-talk, and higher Q than MEMS techniques with more layers of conformal thin films on the beams.

5 BIOGRAPHICAL SKETCH Born (1971) in rural south Georgia, many miles from anything high-tech, I was convinced by many days of farm labor to pursue science as the one area of study sure to take me far from my childhood labors. After completing studies in mathematics and physics at the University of Georgia as an undergraduate, micromechanics, far removed from the cattle worming and insecticide spraying of my youth, brought me to Cornell University (by happy coincidence also far from the oppression of 100% humidity). From my youth I have enjoyed designing and building in the form of building houses and furniture, painting, theater, and fiction. My truest interest have always been in the creation of things and ideas. The field of micromechanics attracted me for the same reasons. iii

6 In memory of my Mother. iv

7 ACKNOWLEDGMENTS Many graduate students in the MEMS group at Cornell University have worked toward suspended trench isolation and have improved my experience at Cornell through their friendship and help. Their efforts and camaraderie have helped to achieve the result reported here. Specifically, thanks go to Scott G. Adams, Fred M. Bertsch, John M. Chong, Peter G. Hartwell, C. Seung-Bok Lee, and Bryan W. Reed. I am grateful to Professor Noel C. MacDonald for assembling such a unique and capable group, providing insight, and allowing for the expression of our interest and creativity. This work was done at the Cornell Nanofabrication Facility whose staff makes our research possible. Funding for this project was provided by DARPA. v

8 TABLE OF CONTENTS INTRODUCTION 1 MEMS Anchor Isolation 3 Previous Suspended Isolation 4 Details of SCREAM Isolation 5 Suspended Thermal Oxide Isolation 7 Organization 8 FABRICATION 9 Trench Formation 11 Planar Electronics 15 MEMS Definition 16 MEMS Release 20 Beam Recessing 22 Fabrication Pitfalls and Solutions 23 Trench sealing cusp 23 DRIE silicon etch starvation 24 Oxide roll-over at top of trench 24 Implantation arcing 24 vi

9 LAYOUT AND DESIGN 26 CAD Layout 26 Isolation Segments 28 Anchors 29 Signal Routing and Crossing 29 Springs and Actuators 32 STRUCTURES AND COMPONENTS 34 Low Leakage Anchors 34 Oxide Isolation 35 Resistor 41 Threshold Actuator 41 Heated Diode Contact Sensor 50 Oxide Beams 54 INTEGRATED ELECTOMETER 60 Structure 61 Operation 62 Guarded Anchor Leakage 65 vii

10 Isolation Leakage 67 Air-Gap Leakage 71 DISTRIBUTED ACTUATOR 74 CONCLUSION 81 APPENDIX 84 Parallel-Plate Instability Derivation 84 Fabrication Notes 85 BIBLIOGRAPHY 89 viii

11 LIST OF FIGURES Figure 1: IBM six level copper interconnects...1 Figure 2: Side, bottom, and cross-section of suspended isolation...3 Figure 3: SCREAM cross-section....6 Figure 4: Single suspended isolation segment...7 Figure 5: Cross-section of suspended thermal oxide isolation....9 Figure 6: Major process cross-sections...10 Figure 7: Fabrication cross-section CAD layout...11 Figure 8: Trench formation...11 Figure 9: Isolation trench after etch...12 Figure 10: Trench etch with less than 1% exposed Si Figure 11: Cusp planarization...14 Figure 12: Contact implants, metallization, and metal patterning...15 Figure 13: Anisotropic patterning of MEMS structure...16 Figure 14: Starting deposition vs. etch steps...17 Figure 15: Isolation shorting due to oxide roll-over...18 Figure 16: Isolation shorting by etch ripples...19 Figure 17: Sidewall passivation, floor clear, and release...20 Figure 18: Bottom of released isolation segment...21 Figure 19: Top oxide clear and beam recessing...22 Figure 20: Recessed beam in a spring Figure 21: Example CAD layout...26 Figure 22: Final device from CAD layout...27 Figure 23: Illustration of layout shorthand...28 Figure 24: Basic signal exchanges Figure 25: Shorthand diagrams of the basic signal exchanges ix

12 Figure 26: Basic signal exchange networks...31 Figure 27: CAD layout for smaller exchanges...32 Figure 28: Anchor bounded by oxide trench at border Figure 29: Anchor with oxide trench inset from border or at edge Figure 30: Expanding truss...37 Figure 31: Fractured Isolation Segments Figure 32: In-line expansion of isolation...40 Figure 33: Parallel-plate stability...43 Figure 34: Closing of threshold actuator (0, 32, 32.5 V)...44 Figure 35: Drift in open and closing voltages over 1.5 hours Figure 36: Oxide charging at high bias...46 Figure 37: Effective potential difference ratio...47 Figure 38: Closing and opening response of actuator...49 Figure 39: Threshold actuator with milled mirror for vibrometry...50 Figure 40: Released diode IV...51 Figure 41: Schematic of heated diode contact sensor...52 Figure 42: Forward diode current as heater is brought into contact...52 Figure 43: V/ T of diode at constant forward current...53 Figure 44: Change in forward diode voltage with heating current Figure 45: Torsional displacement with latching...55 Figure 46: Schematic of z-buckling elevator...56 Figure 47: Out-of-plane displacement via buckling...57 Figure 48: Bent silicon and oxide composite beams...58 Figure 49: Current integrating electrometer...61 Figure 50: Electrometer with bump stop Figure 51: Discharge data for guarded anchor capacitor...66 x

13 Figure 52: Guarded anchor measured resistance...67 Figure 53: Charging data with fit using constant R int Figure 54: Fit residuals...69 Figure 55: Incremental isolation resistance with error Figure 56: Charging through an air-gap...72 Figure 57: Typical MEMS actuator Figure 58: Distributed actuator with 40 isolation segments Figure 59: Distributed DC motion to each side...77 Figure 60: Static motion capture...77 Figure 61: Resonant (2.36 khz) amplitude versus voltage...78 Figure 62: Frequency response of distributed actuator Figure 63: Still and moving distributed actuator...79 Figure 64: Frequency response at 20 and 40 VPP...80 Figure 65: Isolation in use by Kionix, Inc Figure 66: Embedded microfluidic tunnel with isolation xi

14 INTRODUCTION In integrated circuit technology, the most complex and constraining aspect of the technology is often isolation and interconnects. This fact is witnessed by the complexities of modern signal routing in many of the current industry CMOS processes including IBM's six level copper metallization (Figure 1). As transistor dimensions have shrunk over the years, the technology for providing adequate metallization and interconnects on the same scale has become increasingly complex. Figure 1: IBM six level copper interconnects. The situation in MEMS is not one of struggling to adapt an existing signal routing and isolation technology as device design and technology change, but one of entirely lacking a versatile method for providing isolation and metallization. MEMS needs a suspended, robust, capable, and adaptable isolation and interconnect scheme providing isolation at the 1

15 2 same scale of the most primitive MEMS component, the released beam. In addition, this scheme should not constrain MEMS design or prevent future innovation. For these goals to be met, an isolation scheme for micronscale SCS MEMS needs to meet the following requirements: micron-scale isolation, metallization, and contacts planar and low temperature processing structural properties similar to SCS (GPa fracture stress) high breakdown voltage (>200 V) low leakage and capacitance (> TΩ isolation resistance) released isolation segments scalability This work presents the first SCS MEMS isolation process to achieve all these goals. The basic structure of this method for integrating suspended oxide isolation segments with SCS MEMS beams is shown from several views in the figure below. The first image shows a side view of the oxide isolation segment; ripples in the sidewall of the SCS beam result from the cyclic nature of the DRIE Bosch silicon etch [Bosch, patents and ] while the smoothness of the short oxide segment running through the beam belies the slight reentrance of the isolation trench etch (if this trench were not reentrant the DRIE etch of the MEMS structure would not remove all the silicon from the oxide surface). The second image shows the bottom of the oxide isolation after the MEMS release etch has cleared it of silicon. The final image, a focused ion beam (FIB) cross-section, reveals the internal cross-section of the isolation.

16 3 Figure 2: Side, bottom, and cross-section of suspended isolation. Before discussing the new isolation technology, attention will be given to other MEMS isolation techniques. MEMS Anchor Isolation All MEMS which are capable of electrostatic actuation incorporate some form of electrical isolation to separate potentials. The most basic isolation scheme is anchor isolation in which isolation structures are anchored to the substrate. Anchor isolation is commonly used in both surfaced and bulk micromachining. Polysilicon and metal-film MEMS commonly use anchor isolation formed by dielectric films under the

17 4 deposited conducting MEMS structure [Tang, 1989]. Anchor isolation has been formed in bulk micromachining by a variety of methods: isolation of sputtered metal by overhanging oxide in the SCREAM process [Shaw, 1994] (discussed in more detail in a following section). silicon-on-insulator fabrication which leaves the anchors attached to the insulator [Yao, 1998]. depositing dielectric films in DRIE trenches at anchors [Brosnihan, 1997]. bonding silicon MEMS to insulating substrates [Juan, 1997, 1996]. All of these methods are fundamentally limited in their ability to create complex structures by their lack of mechanical connection between structures with different potentials, since all connected beams are at the same potential. The SOI technique improves over sidewall metallization by reducing film stresses and providing low minimum capacitance, but the use of SOI substrates does not solve the general isolation problem because it is limited by the present cost of substrates, can not easily provide released isolation segments, and lacks routing and multiple potentials. Previous Suspended Isolation More advanced isolation schemes which decouple the mechanical and electrical routing and structure of devices have been developed in both surface and bulk micromachining. In surface micromachining, the ability to build relatively planar composite structures can be used to adequately solve the general MEMS isolation problem [Chen, 1993]. The incorporation

18 5 of suspended isolation in bulk micromachining is difficult because of the need to etch into the substrate which results in a non-planar wafer and invalidates many of the standard IC fabrication techniques which surface micromachining can use. Previous methods of fabrication have overcome this challenge but offer only qualified success in suspended isolation of SCS MEMS. Isolation by oxidiation of SCS beams [Arney, 1988; Yao, 1992; Reed, 1999; Zhang, patent ] is limited by stress effects, complex metallization with large features, difficulty integrating other technologies, large isolation segment size, and non-planar processing. The oxidation of defined structures complicates metallization and integration with other technologies such as on-chip electronics. This oxidation approach can provide excellent mechanical and electrical properties and has been used to form isolation and interconnects of multi-level SCS MEMS [Hofmann, 1997]. Deposited dielectric films [Yao, 1996] have been used to circumvent the high temperature requirements of oxidation but introduce the issue of the mechanical strength of deposited films and interfaces without alleviating the other problems of oxidizing beams for isolation. Details of SCREAM Isolation The SCS MEMS isolation process presented here derives its lineage from the SCREAM process. In the SCREAM process, sidewall metallization is formed by depositing an insulator and then metal on all sidewalls of the MEMS structure. The oxide used for releasing the structure is the intermediate insulator and forms a overhang which prevents the metallization on one structure from connecting to adjacent structures or the silicon core of the beams.

19 6 Figure 3: SCREAM cross-section. Using this technique, large actuator plates capable of carrying high voltages (60V)with GΩ resistance to ground can be achieved. The other isolation and interconnect requirements remain difficult to obtain. Using thermal oxide as a sidewall film in SCREAM allows one to apply higher voltages (120V) and reduces leakage current. The primary problems with sidewall metallization are the high minimum signal capacitance due to the thin insulator separating the metallization from the silicon core of the device and the lack of multiple potentials on one connected, released structure. Patterning the metal using thick resist on released devices can provide multiple potentials but is difficult, has large isolation pitch (~20 µm), becomes increasing difficult with deeper MEMS, and does not provide any signal crossovers.

20 7 Suspended Thermal Oxide Isolation The integration of suspended oxidized trenches with SCS highaspect-ratio beams can achieve the desired goals of MEMS isolation. In these systems, planar metallization routes signals to isolated, suspended segments of the device allowing a multitude of signals and high area actuation without high area parasitics. Using small (2 by 8 µm) segments of thermal oxide formed by trench oxidation gives the capability of carrying high voltages with low stress, low leakage, low minimum signal capacitance [Webb, 1998]. Multiple levels of metal or the use of silicon as a conductive line provides signal crossovers for general routing. The process can be integrated with other technologies because a planar wafer is maintained for all photolithography and the only high temperature step (the trench oxidation) is the first process step and leaves the wafer planarized; recently, this isolation process has been integrated (Figure 66) with microfluidic channel fabrication [Chong, 1998]. Figure 4: Single suspended isolation segment. This type of isolation (shown in Figure 4) provides many benefits for MEMS design including reduced parasitic currents and capacitances. The

21 8 sidewall metallization typically used in MEMS with sidewall metal and sidewall oxide thickness, t sw (typically 200 nm), forms a capacitor to the grounded silicon core of the structure proportional to the length and height of the MEMS structure. Using suspended trench isolation the area of parasitic leakage and capacitance is proportional to the cross sectional area of the SCS beam at the isolation point where the insulating oxide thickness, t iso, is typically 2 µm. If the total beam length of the device is L, the parasitic capacitance of the MEMS with sidewall metal is a factor of 2L( t / t ) higher than that of the trench isolated structure. For a small 400 iso sw µm by 400 µm actuator with 400 comb fingers, this factor is greater than 10 5 resulting in higher parasitic capacitance and leakage current. For both types of devices the capacitance to the floor from the released structure can be minimized by recessing the floor with an isotropic silicon etch. Organization The next chapter details the fabrication process while mentioning pitfalls that have been encountered and means to avoid them. The third chapter covers layout and design of basic structures. Chapter four discusses the unique components of structures created with the process and details their characteristics and design. Example devices are discussed in the remaining chapters. The appendices cover derivations and list facility specific fabrication notes.

22 FABRICATION Thermal oxide isolation segments are suspended in SCS MEMS beams as shown in the focused ion beam cross-section of Figure 5. These segments mechanically connect and electrically isolate released beams. By oxidizing a deep RIE (DRIE) etched trench in the first processing step a planar surface is maintained for subsequent photolithography. The MEMS structure is defined and released with a SF 6 dry etch [Bosch, patents and ] leaving contacts, diodes, and other electronics embedded in released, isolated, high aspect ratio SCS beams. The silicon core of the beams is used to form electrostatic actuators. Figure 5: Cross-section of suspended thermal oxide isolation. Building an isolated MEMS structure which exceeds the capabilities of a SCREAM structure requires three masks, one for each of the following structures: isolation trench, contact via, and MEMS. Frequently it is useful to add a metal patterning mask to this list, but simple metal patterning can be achieved using wide trenches that do not seal at the top during 9

23 10 oxidation. Isolated structures have several features not found in SCREAM structures: Fewer sidewall films result in reduced damping, less thin-film stress, and more precise control of the force, spring stiffness, and mass of the structure. Reduced area and increased thickness of the dielectric between devices and ground reduce the parasitic capacitance and leakage current by more than five orders of magnitude. Multiple isolation segments allow several different potentials to be applied to connected structures. Electrical contact to the silicon eliminates the problem of metallizing high aspect ratio structures and allows for integrated resistors and signal shielding. The fabrication process is composed of four main stages: trench formation, planar electronics, MEMS definition, and MEMS release. The following figure shows a cross-section of a simple structure after each stage. The final structure on the left shows a cross-section down the length of an isolated beam, while the structure on the right shows a transverse crosssection of a beam. A section discussing each stage follows. Figure 6: Major process cross-sections.

24 11 The four layer CAD layout and location of the cross-section is shown below: Cross-Section Isolation Trench MEMS beam Beam Contact Metal Removal Figure 7: Fabrication cross-section CAD layout. Trench Formation Figure 8: Trench formation.

25 12 A Bosch DRIE etch (using a PlasmaTherm SLR-770), with variation in parameters between steps, is used to create reentrant trenches using photoresist as a mask. The trenches are required to be reentrant so the vertical etch used to define the MEMS structure will remove all silicon from the sides of the oxidized trenches. Reentrance angles of have been used successfully. Trench lengths (perpendicular to the Si beam) are typically 8-10 µm to simplify photolithography alignment. Trench depths of µm have been used to isolate 8-33 µm deep structures. Figure 9: Isolation trench after etch. The Bosch DRIE requires a minimum area of exposed Si per wafer (5% is adequate). If there is less exposed Si, the passivation layer fails at the top of the trench during the etch giving the profile shown in Figure 10 below. The required area cannot be provided by large trench openings on each die since the resulting holes will not seal (leaving the wafer unplanarized). One solution is to place enough trenches in the pattern to give the required area. The other solution is to expose silicon on the edge of the wafer. For the later technique the edge of the wafer can be exposed or the resist on the edge can be dissolved using a solvent (acetone on a cotton

26 13 swab has worked well). A more viable solution for dedicated trench etching is to place or mount sacrificial silicon within the etch chamber. Figure 10: Trench etch with less than 1% exposed Si. Thermal oxide is grown to seal the trenches; adequate sealing of a 0.8 µm wide trench is provided by growing 1.3 µm of oxide. Due to the reentrant profile a small keyhole void is formed inside the sealed trench. The walls of the oxidized trench are thick enough and the top of the trench is well enough fused that this keyhole does not present any mechanical problems (see Figure 31 and the accompanying discussion for details). The planar oxide is etched back to 400 nm using a dry anisotropic etch. After etch back, the sealed trenches have a nm notch at the seam because pinch-off occurs near the plane of the unoxidized wafer while oxide growth leaves the final oxide surface above this plane. A more planar substrate, which facilitates uniform metallization, can be achieved by coating the wafer with a thin resist layer (~600 nm) and etching the resist

27 14 and oxide with a dry etch having 1:1 selectivity between resist and oxide. The resist is first thinned to around 200nm using a brief O 2 etch (1-2 minutes). Adding a small percentage of O 2 to a CHF 3 dry etch has been found to give the desired 1:1 selectivity for the oxide thinning etch. The figure below shows the result of planarization on three trenches, and the inset shows the final result without planarization. Figure 11: Cusp planarization. Slightly wider trenches have been used to form discontinuities in the subsequent metal deposition. A 1.5 µm trench leaves a 200 nm gap after oxidation which the metallization does not cross and which does not interfere with later photolithography. The resistance across these small metal discontinuities has been measured to range from 100 GΩ to 1 TΩ at V. Using this technique the metal can be patterned where the

28 15 silicon is isolated without significantly adding to the space required for the design. Planar Electronics Figure 12: Contact implants, metallization, and metal patterning. Sloped vias are etched to form contacts from the planar metal to the silicon. A vertical via etch increases the metal etch time because the effective thickness of the metal layer is increased by the thickness of the planar oxide at the edge of the via. Either a BHF wet etch or a sloped resist patterning and a dry etch with 1:1 selectivity between resist and oxide is used to etch these vias. Doses of and energies of 20 and 55 kev have been used to form ohmic contacts and diodes using P + and BF + 2 respectively on a n-type substrate. Schottky diodes have been formed on n-type substrates by depositing Al on unimplanted vias. On a highly doped (> ) p-type substrate ohmic contacts can be formed without an implant using Al as the metal. A nm layer of aluminum is sputtered to contact the vias. The metal is removed in areas where the completed structure should not have metal using either a Cl 2 RIE etch or a wet Al etch. The dry etch is preferred because of its verticality.

29 16 The vias and metal removal patterns are usually thin rectangles (typically 3 x 10 µm) oriented perpendicular to where the 1 µm wide MEMS beam will be patterned. This placement and sizing means most of the wafer remains uniformly covered with oxide and Al which simplifies alignment of the MEMS structure to the vias and metal patterns. If the via and metal patterns are overlapped in a region where a beam is formed, the silicon beam will not have any capping material during the release phase of the process resulting in the removal of silicon from the top of the beam during release. This effect or later removal of the oxide from the top of the beams using the already patterned metal as a mask can be used to hollow out the tops of beams for spring constant reduction or out-of-plane actuators (recessing beams is discussed in a later section). MEMS Definition Figure 13: Anisotropic patterning of MEMS structure. The MEMS pattern is transferred through the Al and oxide layers using dry Cl 2 and CHF 3 etches from 1.5 µm photoresist. Care must be taken to remove all the Al from via edges where its thickness is greatest. The oxide is over etched by nm to remove the oxidation roll-over

30 17 which prevents the oxide filled trench from being reentrant at the top. This over etch can etch into the silicon enough ( nm) to create a wider silicon section at the tops of beams (Figure 14). This section can lead to failure of the sidewall oxide which protects the beam during release as discussed in the MEMS release section of this chapter. This potential failure results from the floor clearing oxide etch attacking the oxide at the upper corner of the beam where it protrudes from under the capping oxide. If the first cycle of the Bosch MEMS definition etch is an etch step, then the wider section is undercut, and the problem it can cause is avoided. An oxide etch that does not significantly etch silicon or that creates a vertical silicon profile also avoids this problem. A cross-section of the initial profile is shown below to the left; while, the results of starting with a deposition step and a etch step are shown on the right from top to bottom. Figure 14: Starting deposition vs. etch steps. The remaining photoresist is used as a mask for an anisotropic Bosch SF 6 DRIE silicon etch which defines the MEMS structure and bonding pads. The selectivity to resist of the Al and oxide etches is typically

31 18 2:1, while the selectivity of the silicon etch is greater than 50:1. To achieve isolation, the depth of the silicon etch should be less than the isolation trench depth (a reliable goal is to make the MEMS structure 1µm + 5% of the beam height shorter than the trench depth) and the profile must be more vertical than the outer walls of the oxidized reentrant trench. The beams can actually be of slightly greater depth than the trenches since the silicon undercut of the beams during release will clear the bottom of the trench, but the more conservative depth goal described above is a more reliable target. Two failure modes for the isolation have been observed during fabrication. Both are due to the silicon not being completely removed from the sides of the oxidized segments and can be avoided by proper selection of etch recipes. Figure 15: Isolation shorting due to oxide roll-over. The first failure mode (shown above) is caused by not removing the oxide roll-over at the top of the trench during the transfer of the MEMS

32 19 pattern into the planar oxide layer. This slight overhang masks silicon around the perimeter of the trenches. The result is a sheet of silicon on the side of the oxide segments which electrically shorts the isolation. In Figure 15 above, the dark material around the lighter oxidized trench is this sheet of silicon masked by the oxide overhang at the top of the trench. The rippled silicon surface resulting from the cyclic nature of the Bosch process causes the other failure mode. A slight non-reentrance remaining at the top of the trenches makes this failure mode more likely to occur for a given etch. If the cycles are too course in time, making larger and deeper ripples, then the point of each ripple can form silicon wires which encircle the isolation segment and connect to silicon on each side as seen in the image below. Figure 16: Isolation shorting by etch ripples.

33 20 MEMS Release Figure 17: Sidewall passivation, floor clear, and release. A 300 nm conformal PECVD oxide layer is deposited to protect the SCS sidewalls from the release etch. The electrical characteristics of the PECVD oxide are relatively unimportant since no conductors are separated solely by this oxide. Another deposition technique which is compatible with the planar metal can be used or the oxide can be removed after release to improve mechanical characteristics. During deposition the wafer is at 300 C for 20 minutes which provides sufficient annealing of the Al-Si contacts. The passivation oxide is removed from planar surfaces using a CHF 3 anisotropic dry etch which has high selectivity versus silicon and aluminum. A vertical Bosch etch is used to etch past the bottom of the isolation trenches and to increase the final distance from the MEMS structure to the floor. This etch also reduces the etch time needed for release and reduces release time variation resulting from aspect ratio or loading effects. An isotropic SF 6 etch is used to release structures having a minimum dimension of less than twice the isotropic etch depth. Some structures in the upper end of this category may not release due to local loading or aspect ratio effects, while some larger structures in open areas

34 21 may be released. The isotropic etch depth is usually 3 8 µm, but a minimum dimension of 30 µm is used for structures that are not intended to be released. The bottom of the silicon beams are undercut by 2 4 µm, 10% of the beam height, during release. The most acute angle on bottom of the structure is the corner near the sidewall passivation and not a dramatic cusp in the center of the beam as sometimes shown. An oxide layer can be deposited to cover the underside of the beam if a passivated surface is preferred. The bottom of the oxide trenches are cleared by the release as well. The next figure shows the bottom of an isolation segment after release. Figure 18: Bottom of released isolation segment.

35 22 Beam Recessing Figure 19: Top oxide clear and beam recessing. An optional removal of the silicon from the tops of structures in areas without metal can be done at this point. No extra photolithography is done for this patterning; all areas not covered with metal are etched including the floor below the suspended structures. First an anisotropic oxide etch (CHF 3 ) is used to remove the top oxide using the previously patterned Al as a mask. A dry silicon etch is then used to remove silicon from the tops of the beams. If an isotropic etch is used, then the bottom of the beams may need to be passivated to prevent undercutting. In the figure below, an anisotropic SF 6 DRIE Bosch etch similar to the beam forming etch was used to recess the silicon. In the figure below, half of a spring has been etched away using an anisotropic silicon etch; the original spring height, h, is shown, and the remaining silicon is marked with a bracket. Only those parts of the structure without planar aluminum have been recessed.

36 23 h silicon Figure 20: Recessed beam in a spring. Fabrication Pitfalls and Solutions In addition to the obvious profile and depth control requirements of the process, several potential problem areas have been identified and methods for dealing with them found. This section will detail these pitfalls and outline solutions while referring to the above chapter sections for details. Trench sealing cusp The cusp at the top of the sealed oxide isolation segment coupled with the expansion of the segment upon release can make the metal discontinuous across the trench. As discussed in the trench formation section above, this problem is avoided by planarizing the oxide during etch back using a resist layer and a CHF 3 /O 2 etch with 1:1 selectivity between oxide and resist.

37 24 DRIE silicon etch starvation The DRIE Bosch process requires a minimum area of exposed silicon in the etch chamber for proper operation. When etching narrow trenches that do not occupy much wafer area, this exposed silicon needs to be supplied by removing the resist near the edge of the wafer or by placing enough narrow trenches within the pattern that enough area is exposed. The trench formation section above provides further discussion and details. Oxide roll-over at top of trench As can be seen in the cross-sections of the previous chapters, the trench sealing oxidation creates a ~0.5 µm deep roll-over at the top of the trench rendering the trench non-reentrant at the top. It is crucial to etch through this non-reentrant trench oxide during the transfer of the MEMS pattern into the oxide at the MEMS definition step. By over-etching the oxide, the roll-over is removed in trench areas that are not covered by MEMS structures (such as where the trenches protrude from the side of the silicon beams), and the roll-over does not mask a sliver of silicon along the trench sidewall as shown in Figure 16. The effect of this oxide over etch can lead to a profile requiring the first process step in the MEMS-defining Bosch etch is an etch rather than deposition step (see Figure 14 and the discussion above it for more details). Implantation arcing In the Cornell Nanofabrication Facility, implantation is done with an unneutralized ion beam. This causes charging of the sample surface and when coupled with resist outgassing as the ions strike the resist mask

38 25 can cause arcing at the vias which destroys the via and can prevent the device from releasing. It has been found that this arcing occurs during the first pass of the ion beam when outgassing is greatest. Reducing the dose by a factor of 10 for the first 10% (the first pass) of implantation has been found to eliminate arcing when a moderate 300 µa implantation current is used. Hard baking of the resist for 3-12 hours may also eliminate the problem.

39 LAYOUT AND DESIGN This chapter covers CAD layout requirements and the layout and structure of basic MEMS elements along with basic design rules and suggestions for reliable layout. CAD layout is compared with micrographs of completed devices in order to illustrate how to layout devices. CAD Layout MEMS Beam (mesa) Isolation Trench (trench) Metal Removal (metal) Beam Contact (via) Figure 21: Example CAD layout. A simple example of a CAD layout is shown above and the resulting MEMS structure is shown in Figure 22. Transverse rectangles, as shown here, are generally drawn in the via, trench, and metal patterning layers to ease alignment. These rectangles are generally 0.8 µm (in the case of the isolation trenches) or 3-6 µm (for the other layers) in width and overlap the mesa (MEMS) layer by 4-10 µm. It is important to realize that overlapping the metal removal, via pattern, and mesa layers will define a MEMS beam that has no metal or oxide capping once the sidewall 26

40 27 passivating oxide is removed from planar surfaces (leaving the silicon exposed on the tops of these beams during extension and release etches). The resulting device rotated counter-clockwise and tilted by about 45 is shown below. The contact via in the center of the intersection is not visible in this image, but the isolation segments and metal patterning on top of the segments is clearly visible. Figure 22: Final device from CAD layout.

41 28 As will be seen later in this chapter, it is often useful to present device layout in a shorthand notation. The shorthand illustrated in the figure below has been designed for simple and clear representation of common structures and is made up of the following elements: long straight lines represent beams. filled circles represent basic isolation segments. outlined rectangles show ohmic contact regions. short line perpendicular to beams indicate metal removal. Comparing the shorthand to the CAD layout presented above should make its features and use clear: Figure 23: Illustration of layout shorthand. Isolation Segments As stated previously, isolation segments are usually drawn as µm by 8-12 µm rectangles overlapping the MEMS beams as shown in Figure 23. Larger trench widths (and hence longer oxidation times for trench sealing) could be used to fabricate deeper trenches for taller, >40 µm, MEMS structures. Generally, around 5 µm of open space is left around

42 29 each isolation segment since they approach 3 µm wide at the base making release in confined spaces more difficult. Using this spacing rule, no difficulties have been encountered during release. Fixed-fixed oxide segments, as would be formed if the isolation segments in the CAD above were extended until they joined, are avoided since expansion of the oxide segments would unnecessarily stress the confining silicon structure. However, the four isolation segments above could probably be joined into a 'U' shaped trench with no ill effects. Anchors Mesa structures defined by the MEMS definition remain anchored to the substrate if their smallest cross-sectional dimension is greater than twice the undercut created by the isotropic silicon release etch. The nonmoving combs in the micrograph (Figure 22) above are attached to such an anchor. Generally, the more open area around a structure the more it is undercut during release and the wider it must be to remain attached to the substrate. A 30 µm feature is usually not released regardless of location during the release of 1 µm beams and intersections surrounded by 2 µm gaps. Signal Routing and Crossing In order for an interconnect scheme to flexibly route signals within a design, structures which can exchange the position of any two signals are needed. Within this isolated MEMS process, signals are carried by the planar metallization and by the silicon core of the beams. The next figure shows the basic signal exchange operations needed to form an arbitrary wiring topology of this system:

43 30 A B Al Oxide Silicon C Figure 24: Basic signal exchanges. Using the shorthand developed above, implementations of each of these exchanges are diagramed below: A B C Figure 25: Shorthand diagrams of the basic signal exchanges.

44 31 Finally, fabricated implementations of each exchange are shown below. Exchange A is shown on top, while type B and C are shown below on the left and right respectively: Figure 26: Basic signal exchange networks. The exchange networks shown above are µm on a side. Smaller networks can be made using finer photolithography on 3-7 µm wide beam sections as shown in the CAD layout below.

45 32 Isolation Trench MEMS beam Beam Contact Metal Removal A B C Figure 27: CAD layout for smaller exchanges. Springs and Actuators Spring and actuator design is much the same as in the SCREAM process. For a given geometry a spring fabricated using this isolation process will have a lower spring constant than in SCREAM since there is no sidewall metal to stiffen the structure ( k width 3 ). Folded spring designs are usually used but 400 µm fixed-fixed springs with two isolation segments have also been used with no difficulty (see Figure 22 for an example). The important differences, resulting from using the silicon core of the beam as the conductor, are contact must be made from the metal to the isolated core and for a given CAD geometry the actuation surfaces will

46 33 be up to 800 nm farther apart (the outer surface of a SCREAM metal layer is about 400 nm from the surface of the silicon core). Also, since the sidewall oxide layer separates the two potentials in this suspended oxide isolation MEMS process, actuator plates can be non-destructively brought into contact.

47 34 STRUCTURES AND COMPONENTS Many unique structures can be formed in addition to the structures found in simple SCS MEMS such as anchors, beams, and springs. The most successful and important of these structures and simple electronics are detailed in the following sections. Low Leakage Anchors A traditional SCS MEMS anchor is simply a large beam which is not released from the substrate. Its sidewalls are clad with the same layers of oxide and (possibly) metal as released beams. In addition to having large capacitance, these anchors also allow leakage to the substrate through the sidewall passivation at the edge and sidewalls of the anchor. In SCREAM type structures, a leakage path also exists along beams since the beams are not isolated. Once high quality isolation is added to MEMS the leakage to the substrate from the beams can be largely eliminated so the leakage of anchors is more significant. Placing an isolation trench and insetting the metal around the edges of anchors creates effective low leakage anchors. This guarding oxide trench can be inset from the anchors edge to ease alignment or can coincide with the edge if 1µm alignment can be achieved. Simple anchors with a perimeter of 1.6 mm and without oxide guarding have been found to have resistances of 1 10 GΩ at 20 V while guarded anchors provide 1-6 PΩ isolation at 20 V. The measurement and analysis of guarded anchor leakage is discussed in the next chapter after introducing the integrated electrometer.

48 35 Figure 28: Anchor bounded by oxide trench at border. Figure 29: Anchor with oxide trench inset from border or at edge. Oxide Isolation Isolation segments become functional when the isotropic release etch removes silicon from under oxidized trenches. These segments can be placed within an anchors edge, as demonstrated in the guarded anchors, or

49 36 crossing a released silicon beam. Oxidized trenches a can also be used to form beams by fabricating long oxidized trenches attached to a silicon beam or anchor. The primary characteristics of isolation segments will be described below and can be divided into mechanical, thermal, and electrical characteristics. The mechanical strength and fatigue properties of thermal oxide provide the high strength and reliability needed for integration with SCS without degrading device reliability and robustness. The force required to fracture the isolation segments has been experimentally shown to be greater than the force required to fracture the SCS beams which the segments isolate. An expanding truss of oxide, Figure 30, was used to fracture the isolated beam shown in Figure 31. During release the thinner 13 µm long isolated silicon beam was released before a larger and thicker 160 µm truss of oxidized trenches connected to it was released. In the picture below, one can see the expanding oxide trusses in the upper and lower portions of the image and the stressed silicon structure in the center. The silicon has failed in this case in the vertical beam near base of the triangular support (just to the right of the upper portion of the isolation segment).

50 37 fracture Figure 30: Expanding truss. As the formerly restrained truss expanded, the silicon beam and isolation segment were put in tension and failed before the maximum stress of 2.5 GPa was applied. The expansion of a fixed free oxide truss, L ox, was measured to be 630 nm and the displacement of the end of a silicon beam, from solving for the equilibrium state of the elastic oxide and silicon beams, pulled by a similar truss is X Si = 1 + Lox E A L E A L Ox Ox Si Si Si Ox where,l Si, L Ox, A Si, and A Ox are the fractional expansion of oxide to silicon, lengths, and cross-sectional areas respectively. Experimentally, a 160 µm long truss was observed to fracture the isolated silicon beam (Figure 31) while a 100 µm long truss did not fracture the beam. From these

51 38 observations, the yield stress of an isolated beam is determined to be between 2.0 GPa and 2.5 GPa (40-50 mn applied force) using ESiXSi σ Si =. L Based on the difference in cross-sectional area, the stress in the isolation segments is roughly an order of magnitude lower than the stress in the SCS beams. Since oxide fibers have been found to have slightly higher yield strength than crystalline silicon [Petersen, 1982] and the stress is lower in the oxide, the oxide segment does not weaken the beam. The important conclusion is that SCS beams isolated with released thermal oxide segments are not measurably weaker than unisolated beams which confirms thermal oxide as a robust MEMS material [Ogo, 1994]. Figure 31 shows examples of this result. Si

52 39 Figure 31: Fractured Isolation Segments. By measuring 241 nm of expansion in a fixed-free beam containing 25 isolation segments (Figure 32), the 2 µm width of each segment was found to expand 9 nm. One expects 4-5 nm of expansion based on the oxidation temperature of 1150C and the thermal expansion coefficients of silicon and oxide. Measuring a 171 µm long trench, the length expansion of these oxidized trenches was found to be 371 ± 16 nm / 100 µm compared with a theoretical expansion of 196 nm / 100 µm. The other source of expansion is stress caused by the volume expansion of oxide in the

53 40 trenches during oxidation. These measurements give an effective thermal expansion factor of 0.37 ± 0.02% for oxide isolation segments oxidized at 1150 C. Out-of-plane bending, due to the slightly reentrant profile of the isolation segments, has not been observed even in fix-free systems with many isolation segments. Figure 32: In-line expansion of isolation. As studied by Hartwell [Hartwell, 1999; Turner, 1999], the Q of these structures with two fixed-fixed springs, each containing two isolation segments, attached to a 400 comb actuator is ~9000 in vacuum and ~20 in air. As expected the electrical properties of 2 µm thick thermal silicon dioxide segments with a contact area of 20 µm 2 satisfy the isolation criteria discussed in the introduction. The breakdown voltage of the segments has been shown to be greater than the 400 V at which the 20 µm air-gap around

54 41 the structure breaks down (2x10 5 V/cm). The expected breakdown should be over 1 kv but maybe reduced by the sharp silicon edges where the bottom of the silicon beam connects to the isolation segment and is limited by the maximum voltage that can be applied to the thinner oxide under the planar metal. The coupling capacitance, 345x10-18 F, of the isolation is negligible in most cases, while the coupling between planar metal lines and the silicon core, assuming a 400 nm top oxide layer, is near 7x10-15 F per 100 µm of beam length if the silicon core is not electrically connected to the metal line. As discussed in the next chapter, the resistance of single isolation segment has been measured to be at least 10 PΩ (P ) at 100 V. Resistor Suspended resistors are formed by contacting an isolated silicon beam on each end. The resulting resistance is L R = ρ, hw where ρ is resistivity, w is beam width, h is beam height, and L is beam length. The current capacity of these resistors is limited by eletromigration in the connecting Al line. A 1 µm by 350 nm Al line has been found to reliably carry 2 ma and to fail within 1 second at just over 3 ma. This maximum current can be raised by increasing the metallization crosssection either by thickness or layout. The current density in these wires at failure is 6-9 GA/m 2 which is similar to reported [Muller, 1977] electomigration in aluminum, 2 GA/m 2. Threshold Actuator A parallel-plate actuator coupled with a displacement or contact sensor can be used to accurately sense potentials with little disruption of

55 42 the system being tested using the simple and well defined instability characteristics of the parallel-plate actuator. Parallel-plate pull-in time rather than voltage has been used for pressure sensing [Gupta, 1997, 1996], and one time use of pull-in coupled with stiction has been used for in situ potential measurement in plasmas [Pangal, 1996]. The basic method of using a spring-mass-actuator system to measure potential in MEMS has its roots in the resonant gate transistor [Nathanson, 1967]. For a non-zero voltage across the parallel-plate, there exists a plate separation at which the actuator will close. This fact is readily observed by noting that the actuator force goes to infinity as the separation of the plates goes to zero (F act g -2, where g is the gap between the plates). For any finite spring force (the spring force has a maximum amplitude, -kg 0, when the plate separation is zero), there exists a plate gap at which the actuator force is equal in magnitude. The parallel-plate's natural instability occurs when this point of collapse and the actuated position coincide. These two fixed points can be seen to approach one another in Figure 33. In an actuator described by a linear spring and a parallel-plate force, the point of collapse occurs at 2g 0 /3 (see the first Appendix section for a derivation).

56 Force V.4 V 2 V 4 V 6 V 8 V 11 V Separation Figure 33: Parallel-plate stability. The threshold actuator is basically a parallel-plate, variable capacitor with a restoring spring. The input voltage located on the non-moving plate, needed to close the actuator is determined by the reference voltage applied to the moving plate. The closing action of a typical threshold actuator design is shown in Figure 34 below. The spring and moving plate are formed by a simple cantilever beam in this case.

57 44 Figure 34: Closing of threshold actuator (0, 32, 32.5 V). To use parallel-plate instability in a sensor application, it is important to have a well defined closing voltage and to be able to tune the closing voltage. Fringing fields and spring non-linearities will cause the instability point to differ from two thirds the starting plate separation but will not impact it's usefulness as a sensor. Typical drift of 15 mv per hour in the closing potential of a threshold actuator with a closing voltage of 39 V is shown below. Some of this drift is likely caused by slight variations in point contact resistance while probing the sample.

58 Closing Voltage Drift [mv] Time [sec] Figure 35: Drift in open and closing voltages over 1.5 hours. An unexpected result from testing the consistency of the closing voltage is that the PECVD oxide sidewalls of the device trap charge if a high enough bias is applied across touching beams. This effect can be seen in the following figure where opening voltage is measured as a function of closing voltage. The shift in opening voltage starts when 50 V is applied across the contact. The shift observed in opening voltage coincides with a similar shift in closing voltage, so this is not a surface effect. The sweep spans about 20 minutes and the time between points is ~10 seconds. This hysteresis results from the onset of conduction through the PECVD oxide layer. The sidewall PECVD used in these devices is known to be less than ideal, and this effect could be avoided by using sidewall oxide with better electrical properties. The other tests presented here are not effected by this oxide charging because lower voltages are used.

59 Opening Voltage [V] Closing Voltage [V] Figure 36: Oxide charging at high bias. One side of the parallel-plate is electrically attached to the potential to be measured; while, the closing voltage is tuned by applying a variable potential to the other side of the actuator. The reference voltage on the tuning plate is then adjusted to make the actuator close at a lower input voltage, biasing it so the potential difference needed to close the plate is achieved at a lower input voltage. To avoid stiction when the actuator closes it is often necessary to include asymmetries (discussed below) which can not be neglected. Asymmetries in the device will cause the plates to have different effective contributions to the potential across the plate; the closing voltage of the actuator depends on which side of the parallel-plate the voltage is applied because of the difference in fringing fields caused by asymmetries. Defining the normal closing voltage, V nc, to be the input voltage needed to close the actuator with the reference voltage on the moving plate being the same potential as the wafer, the following formula relates the input voltage, V i, and reference voltage, V ref, to the normal closing voltage:

60 47 Vnc = Vi Γ Vref, where Γ represents the effectiveness of V ref with respect to V i. Ideally Γ=1, but it is most important to determine its value for a particular design by stepping V i and measuring its effect on the closing voltage by sweeping V ref. Such a sweep is shown below for an extremely asymmetric design in which Γ = (this asymmetric design is shown in Figure 39) Closing Voltage [V] y = x R 2 = RefCap Voltage [V] Figure 37: Effective potential difference ratio. Once the parallel-plate actuator is closed the potential across the actuator must be reduced to release the plate. A large contact area can result in surface forces capable of holding the actuator closed with no applied voltage. To avoid this stiction, small protrusions (sometimes called bump stops or simply stops) are used which contact before the full plate area. These stops serve to increase the minimum releasing voltage by reducing surface interactions and increasing the minimum plate separation which reduces the force between the plates for a given voltage and minimizes the current spike caused by the capacitor's collapse

61 48 [Castaner, 1999]. The simplest design is to locate the stops on one side of the parallel-plate. This location however removes the air-gap which normally isolates the two plates. A better arrangement is to design a separate stop, either grounded or electrically connected to the moving plate it contacts. Because the moving plate will contact this stop, the moving plate carries the reference potential leaving the input voltage isolated by the more effective air-gap. By having the stop at the same or nearly the same potential as the moving structure it contacts, one can also eliminate the high voltage, PECVD oxide charging problem mentioned above. This sensor system needs to approach instability quasistatically, so its maximum operating frequency must be significantly below its natural frequency. The cantilever based systems studied have a resonant frequency of ~50 khz and are capable of measuring 0-30 V potentials with 5 mv precision at a sampling rate of >30 Hz. The dynamics of the closing and opening of a threshold actuator are shown in Figure 38. The data was collected using a commercial vibrometer after cutting a 45 degree mirror (Figure 39) using a focused ion beam. The recorded instability point is greater than one half the total movement because the motion is limited by a bump-stop (the drawn gap between actuator plates is 4 µm in this design).

62 Distance [µm] Time [sec] Figure 38: Closing and opening response of actuator. The next figure shows the tested system including the milled mirror (labeled 'M') which allows optical in-plane probing. The actuator shown here is a simple cantilever with an opposing fixed plate and grounded bump-stops.

63 50 Figure 39: Threshold actuator with milled mirror for vibrometry. Heated Diode Contact Sensor A general problem facing MEMS is the need for displacement sensing. Contact sensing is also important and when integrated with a tunable potential sensor can be used to monitor on chip capacitive changes. Relays [Kruglick, 1999] have successfully been used for contact sensing and have the advantage of high signal output. Fabrication complexity, high voltage damage, and reliability problems are among the disadvantage of relays. In the interest of simplicity (with additional processing relays could be fabricated in this isolation process), contact heating of diodes was explored as a contact sensing method. Using the same layout as the resistor but replacing one of the substrate contact vias with a diode via, gives an isolated diode with the ohmic contact to the isolated beam segment contacting the diode base. The

64 51 I-V characteristics of a 4 µm by 1 µm suspended and isolated diode are shown in Figure 40. The breakdown voltage, ~6.6 V, matches the expected value for a shallow, highly doped diode on doped silicon substrate; the forward bias current density is comparable to that of a planar, unetched diode fabricated on the same wafer. 1.0E E-04 Current [I] 0.0E E E E-03 Voltage [V] Figure 40: Released diode IV. Contact heating of integrated diodes provides another contact sensing method. As discussed in the section on resistors, isolated resistors can be used as heaters. Bringing a heater into contact with a beam containing a diode biased at constant forward current produces a change in biasing voltage roughly proportional to the temperature change of the diode. This sensing method is viable between -50 C and 200 C. Above 200 C forward current can damage the junction due to increased dopant mobility [Gardner, 1994]. A schematic of the contact heated diode is shown in the next figure. In addition to the notation described in Figure 23, a square with an 'X'

65 52 inside represents a diode via, and a line with diagonal hatching on one side shows an anchored beam. diode heater current actuation Figure 41: Schematic of heated diode contact sensor. Biasing an integrated diode to -1 V forward bias and bringing a silicon heater into contact with it using a parallel-plate actuator gives the response shown in Figure 42. The use of a parallel-plate actuator insures that the transition to contact is abrupt id(-1v) [µa] Vact [V] Figure 42: Forward diode current as heater is brought into contact.

66 53 Solving for the forward voltage at a given forward current, I f, gives kηt If Vf = ln 1 + q I0 where I 0 = 2 Ani q N a ktµ n. qt n Plotting the derivative with respect to temperature of this forward voltage equation one can see that the change is forward voltage at constant current while not constant, as often claimed, varies by ±1% in 100 K around 300 K dv/dt [mv/k] Temperature [K] Figure 43: V/ T of diode at constant forward current. With the heater in contact with the diode beam, the heating current was ramped and the change in forward diode voltage measured for a range of forward currents. As shown in the chart below, the change in forward

67 54 voltage is independent of forward current and indicates a temperature change of 14 C Diode Voltage Change [V] µa -26 µa -51 µa -76 µa E E E E E E-03 Heating Current [A] Figure 44: Change in forward diode voltage with heating current. Oxide Beams As mentioned earlier, oxide trenches can be used as structural beams rather than simply as embedded dielectric segments of silicon beams. When attached directly to the silicon substrate without supporting springs, thermal mismatch can easily distort released structures, cause buckling, or otherwise apply large forces. The forces generated are not always convenient but can be used to provide static displacements and forces which are otherwise impossible within the same area. The out-of-plane stiffness inherent in high-aspect-ratio MEMS makes it difficult for these systems to operate out of the plane of the wafer. One way to circumvent this limitation is to permanently deflect a device

68 55 out of plane. Torsional beams are capable of large angles which can deflect devices out of plane but require large displacement forces and large motion out-of-plane actuators. Using a latching mechanism to hold the deflected device, allows a device to be deflected out of plane once by an external probe and fixes its position where it may operate far from the wafer plane. The thermal mismatch between coupled silicon and oxide beams can be used as a latching mechanism that is as stable and strong as the device is elevates. Both buckling and continuous stress induced displacements have been used for latching to achieve angular displacements. In the buckling example below, a fixed-fixed oxide beam buckles toward a torsional paddle. When the paddle is depressed the oxide beam pushes a silicon beam over the edge of the paddle locking in place. Figure 45: Torsional displacement with latching. Large static displacements can be obtained with buckling beams [Huang, 1996]. The magnitude of these displacements must be predicted using careful calibration since small deviations in stress or geometry can radical alter buckling results [Saif, 1998]. In plane buckling occurs in µm long fixed-fixed oxide beams. Out of plane buckling can be

69 56 achieved by building a fixed-fixed oxide truss structure with width greater than the oxide beam height. A schematic of this type of z-elevation device is shown below: elevated MEMS signal line signal line anchor buckled oxide truss anchor Figure 46: Schematic of z-buckling elevator. The following figure shows a 3 mm long 500 µm wide oxide truss built from 30 µm tall oxide beams that is buckled 180 µm out of plane. At its center a functional distributed actuator is attached. Contact is made to each side of the actuator by torsionally hinged trusses running from the anchors alongside the buckled oxide. The structure buckles upward because the top of the truss, being less constrained than the bottom, is able to flex before release.

70 57 Figure 47: Out-of-plane displacement via buckling. Another way to exploit the thermal expansion mismatch between silicon and silicon dioxide is to fabricate connected, parallel oxide and silicon beams (as shown in the bimorph cantilevers of Figure 48) so that at room temperature the silicon is shorter than the oxide causing the composite beam to bend toward the silicon side. This type of lateral motion instead of buckling can be used for clamping avoiding the tendency of overly constrained buckled structures to seek other stable modes. The following figure shows four composite oxide and silicon beams at room temperature; from left to right, the spacing between the oxide and silicon sub-beams is decreased leading to a larger stress gradient and more bending. These beams are composed of an oxide cantilever, the right side of each composite beam, overlapping a comb-shaped silicon cantilever.

71 58 oxide silicon decreasing spacing between beams Figure 48: Bent silicon and oxide composite beams. The final angle and separation between silicon and oxide beams are 3.9, 4.5, 6.1, 9.4 degrees and 8, 6, 4, 2 µm from left to right. Using a simple arc length model, where s is the separation between beams, L is the length of the composite beam, and is the measured (.37 ±.02%) fractional expansion of the oxidized trenches when cooled from 1150 C to room temperature, the final angle, φ, is given by φ = L s. This model gives 3.4, 4.5, 6.8, and 13.6 degrees for the final angles. The model becomes less accurate as the separation between the oxide and silicon beams goes to zero because it assumes the oxide is able to expand fully neglecting the increasing effectiveness of the silicon beam in constraining the oxide as the separation is decreased.

72 59 Composite silicon and oxide beams can also be used for thermal actuation by passing current through the silicon half of a composite silicon and oxide beam. Thermal actuation, though slow and often requiring high power, can create large forces [Zhang, 1999; Que, 1999]. Passing a heating current through the silicon half of the right-most bimorph pictured above, results in 2-3 µm of motion at the tip for a 3 ma current (~2 V bias). A more resistive substrate would allow more heat generation at 3 ma at the expense of a larger applied voltage; while, increasing the cross-sectional area of the metallization would allow for higher current capacity.

73 INTEGRATED ELECTOMETER Combining the threshold actuator, a contact sensor, and a high resistance input capacitor of known value allows small currents to be measured by accumulating charge on the capacitor and measuring its potential with a threshold actuator of much smaller capacitance. This system is distinguished by its simplicity, PΩ (10 15 Ω) input resistance up to 20 V, and a large voltage-sensing range. Sensing fa currents with PΩ input resistances is typical of relatively modern electrometers [Clover, 1989]. Since an air-gap is maintained between the sensing actuator and integrating capacitor, the potential on the capacitor is independent of sensing frequency. The goals and special features of this system are as follows: measure 10 fa currents on-chip with a measurement period as low as 10 seconds. measure on-chip potentials with an accuracy of.01 V over a dynamically tunable range of -30 to 30 V. measure on-chip resistances up to 10 PΩ with 10-20% error. radiation tolerance greater than electronics based sensing µm 2 sensor area. 3 PΩ input resistance at 20 V. on-chip measurement of integrated current sources. room temperature operation. fabricated with the basic isolation process described here. In the literature, low temperature MEMS electrometers using resonance tuning caused by moving the input charge through a known external magnetic field have recently been demonstrated and studied [Cleland, 60

74 ]. General discussion of electrometer design including that of mechanical, spring-balanced electrometers can be found in older literature [Hansen, 1936; Palevsky, 1946]. Structure The basic sensing circuit is shown below. By monolithically integrating the components on chip, parasitics are reduced. The internal resistance of the reference capacitor, R int, remains a factor. Care has been taken to increase R int by using the guarded anchor structure discussed in the previous chapter for the integrating capacitor. C pp sensor I in C int R int V ref sensor bias Figure 49: Current integrating electrometer. Figure 50 shows a MEMS-based implementation of the circuit above. The sensing threshold actuator is at the bottom of the picture. The ladder shaped half of the threshold actuator is connected to the integrating capacitor. In the upper half of the picture, a bump stop can be seen which maintains the air-gap between the moving threshold actuator plate and the integrating capacitor. A heated diode contact sensor, discussed the previous chapter, is integrated into the bump stop, and the moving beam at the top of the image contains a heating element for the sensor. The data reported here was collected using the reflectance monitoring of a commercial vibrometer.

75 62 Figure 50: Electrometer with bump stop. Operation Prior to measuring integrated currents with this device, one must determine a few characteristics of the design. The first critical characteristic is the closing voltage with respect to the capacitor voltage. As discussed in the previous chapter this relationship can be described by a linear function; further accuracy can be obtained by adding a cubic term, but the correction provided by this term is less than 1% over the target voltage range. The capacitance of the integrating capacitor is also needed and is measured using a commercial LCR meter, HP-4274A. Alternatively, the capacitance could also be obtained using a current source and monitoring the charge accumulation with the device itself. Other characteristics that can effect

76 63 measurement are resonant frequency and Q of the threshold actuator and the temperature dependence of the system. The resonant frequency of the sensor is around 50 khz in the tested devices and does not impact the tests performed. Because the device is tested in air, its Q is fairly low (around 20); coupled with its high resonant frequency this means that the system will effectively reach equilibrium in less than 2 msec at which point its energy will have damped to.67% (1/e 5 ) of the initial energy. The experiments reported here are done by using LabView to control a laser reflectance monitor with ~1 µm spot size (part of a Polytec OFV3001 vibrometer system) and two Keithley 487 voltage sources. One voltage source is attached to the threshold actuator and is used to tune the closing voltage of the actuator until the potential difference between it and the integrating capacitor voltage is great enough to destabilize the parallel-plate actuator used for sensing. The other voltage source is used to bias the device supplying the input current or, in the case of characterizing the integrating capacitor, to directly charge the capacitor. The laser is aligned such that when the beam rests against its bump stop the laser reflects off the top surface of the beam. Since the laser spot size is 1 µm and the mechanical structure's instability point is more than 500 nm from the bump stop, the laser can be aligned so that it only detects the MEMS beam when resting against the stop or in transition to the stop. The mass of the actuator does not effect the location of its instability point, but will determine the time the actuator takes to close and contribute to error in determining when the instability point is reached. For this reason a cantilever design with low mass is used.

77 64 The basic measurement technique is to apply a voltage to the threshold actuator which insures the actuator is open and then sweep the sensor bias until the actuator closes. By comparing the closing voltage to the known relationship between capacitor voltage and closing voltage the corresponding capacitor voltage is determined. Comparing this voltage with a pervious measurement is used to determine the average current between the measurements: I average = CV ( 2 V1) ( t t ) 2 1 When monitoring a current comparable in magnitude to the internal leakage of the capacitor, it is necessary to insure that the integrating capacitor is fully discharged before starting the measurement. When the input circuit is simply a large resistor, this is done by comparing the closing voltage to the known closing voltage of the system when the capacitor is discharged and applying an input bias which will discharge the capacitor while monitoring the closing voltage until the closing voltage corresponding to zero voltage on the capacitor is achieved. In other cases the capacitor must be directly discharged by making contact to it; an integrated relay would be ideal in this case but another actuator that touches the capacitor can provide effective discharging since the isolation provided by PECVD sidewalls is on the order of GΩ, meaning 10 V can be discharged in less than 30 msec when one applies a small voltage of opposite polarity to the beam touching the capacitor. In measurements where the input current is known to be significantly larger than the capacitor's internal leakage at the voltages in question, measurements can be conducted by comparing a series of closing voltages without concern for the capacitor's starting charge.

78 65 The smallest charge measurable by this system is determined by voltage noise on the capacitor as given by the equation below [Hansen, 1936]: 2 CVrms kt = 2 2 which implies the smallest measurable number of electrons is ktc n = e q. For a capacitance of 2.98 pf as used in the tested devices smallest detectable charge is 700 electrons. Since the minimum voltage increment used in testing was 1 mv with a 1 pf capacitor, the smallest charge that has been measured with these systems during testing at room temperature was 6.2k electrons (9 times the minimum charge). With decreasing capacitance, the thermal noise of the spring system will eventually become the limiting factor in small charge measurement but is not a significant factor in the systems tested. Guarded Anchor Leakage The parasitic resistance to ground of the guarded anchors used as integrating capacitors was measured by charging an anchor with a capacitance of 2.98 ±.02 pf to 20 volts and monitoring its discharge using the threshold actuator and laser reflectance monitor. Using a device with an integrating capacitor with no integrated input source, the guarded anchor capacitor was directly charged to 20 V and then the charging probe was lifted to allow the capacitance to discharge. By sweeping the sensor bias, V sensor, and recording the closing voltage over time, the internal discharging rate of the capacitor was monitored directly. In the literature, similar characterization of internal discharging has been used for a MOS

79 66 electronic electrometer giving an input resistance of Ω for a prototype device [Cover, 1989]. The data collected and five point box smoothing of the data are presented below: Voltage [V] Time [sec] Figure 51: Discharge data for guarded anchor capacitor. The resistance at each point of discharge is calculated by comparing the change in capacitive charge to the average applied voltage. R V Vavg( t2 t1) Vavgtdif = = I CV ( V) CV 2 1 dif The total error is where E = Cƒ+ tƒ + Vƒ + Vƒ, total diff avg dif f ƒx X X ( 2, f is the function for which the error is being calculated, and ( X is the error in measuring X. In this case the error is

80 67 Vavg CV t ( t CV V ( V t ( dif avg dif Vavgtdif V CV CV C ( dif avg dif dif 2 2 dif Using the above equations and the following errors gives the results presented in Figure 52: time error =.01 sec (LabView uncertainty), voltage error =.007 V (1/ 5 of the voltage error before smoothing), capacitance error =.03 pf (using HP-4274A LCR meter). 6.00E+15 dif 2 dif E E+15 Resistance [Ohms] 4.50E E E E E E E Voltage [V] Figure 52: Guarded anchor measured resistance. Isolation Leakage An interesting and challenging small current measurement to perform with the system is measuring the leakage through a single released thermal oxide isolation segment. The resistance of an isolation segment is high enough to be difficult to reliably measure without expensive commercial electrometers and careful attention to parasitics. The input resistance of the electrometer device is expected to be comparable

81 68 if not less than the resistance of a single isolation segment. The isolation characteristics of an air-gap will also be explored for comparison since an air-gap of approximately one micron separates the threshold potential sensor from the integrating capacitor and leakage through such an air-gap must be understood in order to draw conclusions about oxide isolation effectiveness. The data presented below represents the charging of the integrating capacitor by leakage through an isolation segment with 100 V applied across it. Assuming constant values for both R iso and R int gives the following charging equation: V R t iso int Cint Rint R V e iso int = 1, Riso + R int where V iso is the voltage on the isolation segment which generates the input current. A curve fit in Mathematica puts both R iso and R int within 2% of 10 PΩ (10 15 ). The curve fit also shows that assuming the resistances to be constant is the main limitation of the model. In the chart below showing 1700 data points over six hours of measurement, one can see the fit indicates a slower charging rate at the beginning of charge accumulation and a slightly higher rate at the end. This error can be explained by considering the voltages of both the isolation segment and the integrating capacitor as the charging takes place. Since the voltage on the capacitor is rising from zero while the voltage on the isolation is decreasing in magnitude, the ratio of the two resistances R iso /R int is likely to go up as the charging progresses (the resistance of each is higher at lower voltages).

82 Capacitor Voltage [V] data fit Time [sec] Figure 53: Charging data with fit using constant R int Fit - Measured [V] Time [sec] Figure 54: Fit residuals. The fit indicates a internal resistance of 10 PΩ for the capacitor which is comparable to the value measured by monitoring the capacitor discharge directly as discussed in a previous section. Taking this value as a

83 70 reasonable approximation and presumably an accurate value for some voltage between 0 and 50 V, the resistance of the isolation segment can be evaluated, using the same incremental method used above to determine the guarded anchor resistance, R avg Vavg =, I avg by adding the current drained away by the internal leakage of the capacitor to the measured current since the isolation leakage is also supplying current to make up for the self-discharge of the capacitor. The results of this analysis are shown below in Figure 55 and indicate that a resistance of 10 PΩ is reasonable. 1.3E E+16 Isolation Resistance [Ohms] 1.1E E E E E E Voltage on Isolation [V] Figure 55: Incremental isolation resistance with error. In addition to the results above it is interesting to estimate the number of charge carriers in the oxide. From Muller and Kamins, the mobility of electrons, 20 cm 2 /Vs, is much higher than that of holes in silicon dioxide and can be assumed to be the main carrier species.

84 71 J n = = qµ ε A V q 100 µ cm ( 3 4) 10 3 cm 4 As described in Sze [1967], the conduction, in steady-state, through oxide at low fields is ohmic, essentially independent of oxide thickness for a given field strength, and results from thermally excited electrons hopping between isolated states. For this 2 µm thick oxide isolation with an area of 20 µm 2 to have a 10 PΩ resistance, the oxide resistivity is Ωcm which falls in the range of measured for bulk oxide in the literature [Johansen, 1965]. The literature contains many recent discussions of thinner oxide layers (<20 nm) at much higher fields (>4 MV/cm) than applied here (0.5 MV/cm). Fowler-Nordheim tunneling into the oxide conduction band is the most relevant conduction mechanism at these high fields (6.5 MV/cm for a silicon electrode) [Lenzlinger, 1969; Suyama, 1987]. Consideration of conduction through thin oxide layers can be found in Kassmi [1990] and interface stress effects for thin oxides (<10 nm) are covered by Kimura [1996]. Breakdown of ultra-thin oxide films is also thoroughly covered [Chen, 1985; He, 1999]. Air-Gap Leakage The leakage through an air-gap is important for two reasons. The first is to compare leakage through air to the isolation leakage measured in the previous section in order to determine if leakage of the isolation segment was the primary leakage source. The second need to study leakage across an air-gap is to determine if the air-gap of the sensing threshold actuator is significantly altering the potential on the integrating capacitor.

85 72 The need to validate the isolation segment as the major leakage source suggests using the same system with the isolation segment replaced by an air-gap. This structure was fabricated by removing the isolation segment from a device using a focused ion beam leaving a ~2µm air-gap where the previously tested oxide segment was located. Repeating the experiment of the previous section after removing the oxide isolation segment using a focused ion beam gives the charging curve shown in below: Voltage [mv] Time [sec] Figure 56: Charging through an air-gap. The average resistance for the first 1000 seconds of applied voltage is 880 PΩ. One may suspect the source of this leakage is not necessarily through the 2µm air-gap were the isolation was located. Other options include leakage through the air across larger gaps or surface leakage along the grounded silicon floor separating the leakage supply voltage from the integrating capacitor. Among all these options leakage across the smallest air-gap seems most likely.

86 73 Having determined the basic electrical, mechanical, and thermal characteristics of the isolation segments, the next chapter will present a device which requires a suspended isolation scheme and exceeds the capabilities of a unisolated design. An isolation technique producing isolation on the same scale as the MEMS structures of the design is particularly important in this example.

87 74 DISTRIBUTED ACTUATOR A common MEMS actuator is the linear comb-drive actuator. A comb-drive actuator fabricated using suspended oxide isolation is shown in Figure 57. Using the silicon as the actuator conductor, one can ground the fixed combs which allows the signal carrying comb arms to be tied together around the actuator perimeter. This design avoids a common failure mode resulting from the bending of cantilevered comb arms. This device resonates around 4 khz with an amplitude of ±8 µm at 20 VPP. Figure 57: Typical MEMS actuator. Two common figures of merit for MEMS devices are range of motion and displacement per volt. While these are interesting qualities, the distance moved by a given actuator needs to be compared to the size of the actuator since obtaining larger motion by building proportionally large device does not yield more motion per chip area. Fractional motion, Γ, is

88 75 defined below and accurately measures the motion of a device relative to its size, the square root of the chip area used by the moving device. Γ distance area The maximum fractional motion is 1 since the area covered by the moving device is included in its effective chip area. For a large motion, typical comb drive actuator, Γ=001.. Using a dual height extension of the SCREAM process actuators designed to optimize stability and obtain large motions have achieved fractional motions of [Lee, 2000]. For a given application, this metric needs to be balanced against the optimization of other valid metrics such as frequency response, stability, Q, force application, and input voltage. Larger motions can be generated at comparable voltages by a distributed actuator, one composed of a series of smaller actuators where the motions add constructively. Distributed actuators are a good example of a device which is not feasible in a MEMS process using sidewall metallization [Chen, 1993]. The ability to place small isolation and metal patterning within a confined design is the primary reason for this expanded capability. A distributed MEMS actuator shown in Figure 58 which has 20 isolated silicon segments was fabricated and tested. The compact size of the isolation segments allows the device's 20 actuators within a 350 x 200 µm area. The silicon core is grounded outside of the isolated segments and is used for one side of the actuator. This device is effectively a self actuating cantilever and over comes the typical limitation of cantilevers, which require either curved fixed combs or high starting voltages, by integrating

89 76 actuators along the length of the cantilever. Fractional motions of 0.61 have been obtained with distributed actuators of this type. Figure 58: Distributed actuator with 40 isolation segments. During testing, the minimum voltage needed to collapse the distributed parallel-plate actuators was measured to be 48 V, and a stable DC sweep of ±15 µm at 47 V is demonstrated by the data in Figure 59. The devices can be operated for full open and close cycles in both directions with no signs of damage.

90 Distance [µm] Voltage [V] Figure 59: Distributed DC motion to each side. The data above was taken from capturing the DC motion of the device under an optical microscope and comparing the actuated and unactuated images as seen below in Figure 60. Figure 60: Static motion capture. A similar motion is observed for both directions of actuation as demonstrated in the resonance response, Figure 61, which plots the amplitude at the structures resonant frequency, 2.36 khz, versus applied

91 78 peak-to-peak amplitude of the input sine wave when the signal is applied to first one and then the other side of the balanced actuator (each side drives the system with a separate set of 10 actuators). The amplitude begins to level off in the figure because the actuators near the end of the distributed cantilever of actuators are fully closed Amplitude [µm] Peak to Peak Voltage [V] Figure 61: Resonant (2.36 khz) amplitude versus voltage. These self actuated cantilever designs do not show the frequency hysteresis often observed in systems where spring stretching occurs. The next figure, Figure 62, shows the results from sweeping frequency and recording amplitude of motion for a 40 VPP sine input. One curve is increasing frequency while the other is decreasing frequency.

92 Amplitude [µm] Frequency [Hz] Figure 62: Frequency response of distributed actuator. Constancy of the resonant frequency for different input voltages was explored using a different design shown still and in motion below: Figure 63: Still and moving distributed actuator. The response of this device sweeping forward and back in frequency for 20 VPP and 40 VPP signals is shown below in Figure 63.

93 Amplitude [µm] Frequency [Hz] Figure 64: Frequency response at 20 and 40 VPP. In conclusion, distributed actuators offer a means of achieving large motion per chip area. These actuators are one example of micron-scale, suspended isolation opening new avenues of design and innovation in MEMS.

94 CONCLUSION The isolation technology presented here enables more complex designs through lower parasitics, integration of electronics, multiple potentials within on SCS structure, and decoupling mechanical and electrical energy. New devices using suspended thermal oxide isolation feature improved reliability and robustness, less signal cross-talk, and higher Q. Maintaining a planar wafer and using low temperature processing after the trench oxidation allows this isolated MEMS process to be integrated with other technologies including IC fabrication. Kionix, a high tech startup in Ithaca, NY, has adopted the process as their primary fabrication technology. Thanks to their efforts of refinement, attention to process variation effects, and innovation in packaging technology there will soon be an ISO 9000 qualification for the fabrication process. Having more than six dedicated engineers refining the process and making commercial products with this technology proves its fundamental stability and capability. An example of Kionix fabrication using the isolation technology is shown below: 81

95 82 Figure 65: Isolation in use by Kionix, Inc. The adaptability of the process has been proven by John Chong's adaptation of the process to additionally produce suspended, movable, microfluidic channels with integrated heaters and fluid injection ports [Chong, 1998]. An example of these fluidic structures is shown below after being cut away with a focused ion beam.

96 83 Figure 66: Embedded microfluidic tunnel with isolation. Additionally, this suspended oxide trench isolation for SCS MEMS is increasingly being used to solve unique problems. The use or planned use of the process for out of plane actuation (Chris Lee, Cornell University), experimental study of dynamics (Kimberly Turner, Univ. of Santa Barbara), and RF MEMS (Noel Elman, Cornell University) is a testament to the processes maturity.