Vertical high voltage devices on thick SOI with back-end trench formation

Transcription

1 Vertical high voltage devices on thick SOI with back-end trench formation U. Heinle, K. Pinardi *, and J. Olsson, Uppsala University, Sweden * Chalmers Technical University, Gothenburg, Sweden

2 Outline Introduction & goals Realization of the VDMOS transistors on thick SOI Comparison of front-end and back-end trench formation Electrical results Summary

3 Introduction Integration of high voltage devices and logic circuitry reduces cost and inceases reliability LDMOS transistors and LIGBT possible options Junction isolation of lateral devices consumes big area SOI with deep trench isolation makes it possible to use vertical DMOS transistors

4 Goals Integration of vertical high voltage devices and logic circuitry Automotive application requires Low R on Breakdown voltage >400V Simple scalability Vertical DMOS transistor on thick silicon-on-insulator

5 Realization Thick SOI with 50µm thick device layer Doping 4e14 cm 2 Deep trench isolation Buried dopings to minimize R on RESURF to avoid lateral punch-through

6 Top view of a transistor structure

7 Process flow with front-end trench formation 1. As + implantation into the backside of the device layer and bonding 2. Trench etching, phosphor diffusion into the trench sidewalls, TEOS deposition, poly-si deposition, CMP 3. RESURF implantation and high temperature anneal 4. Growth of the gate oxide (500Å) 5. Poly-Si deposition and gate etch 6. P-base implantation and diffusion 7. Contact implantations 8. CVD oxide deposition and contact hole etch 9. Metallization

8 Slip lines after high temperature anneal

9 Defects after Secco etch

10 Defects at the surface

11 Breakdown voltage of a RESURF-n - -diode Breakdown voltage > 600V

12 Stress simulations Front-end Back-end Stress reduction due to back-end trench formation

13 Process flow with back-end trench formation 1. As + implantation into the backside of the device layer and bonding 2. RESURF implantation and high temperature anneal 3. Growth of the gate oxide (500Å) 4. Poly-Si deposition and gate etch 5. P-base implantation and diffusion 6. Contact implantations 7. Trench etching, phosphor diffusion into the trench sidewalls, TEOS deposition, poly-si deposition, CMP 8. CVD oxide deposition and contact hole etch 9. Metallization

14 No visible slip lines at the end of the process

15 Defects after Secco etch Best case Worst case Reduced number of defects

16 Reduced number of defects at the surface

17 Electrical results Breakdown voltage of a RESURF n - -diode Breakdown voltage of a vertical DMOS transistor

18 Electrical results (2) IV-characteristics of a 30mm transistor Comparison of devices with different gate lengths DC characterization does not show a difference between front-end and back-end trench formation!

19 Summary High voltage VDMOS transistors on thick SOI with back-end trench formation have been demonstrated Front-end trench formation creates a large number of defects Back-end trench formation reduces the number of defects No difference in DC characteristics between front-end and back-end trench formation

20 Acknowledgement This work is financially supported by a grant from the Swedish Foundation for Strategic Research (SSF) within the Auto-IC project. The authors are grateful to Magnus Granström, Volvo Technical Development Corporation, and Stefan Bengtsson, Chalmers Technical University, for many useful discussions.