IMPACT Seminar. Title: Past, present, and future of CMP Faculty: David Dornfeld Department: Mechanical Engineering University: Berkeley IMPACT

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1 1 Seminar Title: Past, present, and future of Faculty: David Dornfeld Department: Mechanical Engineering University: Berkeley

2 2 Overview Outline History and Future Development (courtesy of Ken Cadien, formerly of Intel (Fellow Emeritus) and now Professor and Canada Research Chair in Nanofabrication, University of Alberta, Department of Chemical & Materials Engineering) - slurries and pads Towards design for manufacturing (DFM) for in

3 3 Components of Chemical Mechanical Planarization Mechanical Phenomena Chemical Phenomena Interfacial and Colloid Phenomena

4 4 Scale Issues in Material Removal Mechanical particle forces Particle enhanced chemistry Active Abrasives Pores, Walls Grooves Pad Chemical Reactions Tool mechanics, Load, Speed Mechanism critical features dies wafer Layout nm!m mm Scale/size From E. Hwang, 2004

5 5 GoogleEarth view of process We are here

6 6 phenomena at different scales slurry supply Pad/Wafer rotation of wafer head downforce Head Plate n Pad Wafe r 4-12 Die 100nm-10!m Featur e Feature/Asperity ~1!m 1-10!m pad asperity Copper abrasive particles Pad asperity Abrasive Abrasive Contact

7 7 Cadien Outline History Challenges and solutions: slurries and pads Next 10 years Very long Term Conclusions Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

8 8 History circa 1984 The semiconductor industry thought that scaling was done at the 1.0 mm dimension due to topography Topography 3 µm Topography > DOF! Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

9 9 History 1984 Karey Holland remembers her reaction one day in 1984 when a colleague, Bill Cote, at IBM recommended that she use what seemed for all the world like a scrub pad and a scouring liquid for one of the critical steps in processing the silicon wafers that contained the next-generation memory chips. The idea of exposing the wafer surface to billions of abrasive particles did not sit well with her. You re not going to put that dirt on my wafer, she protested. Source: Scientific American Magazine, February 1998

10 Interconnect Scaling Enabled by 1000 nm Two Al Metal layers, BPSG nm ILD planarization, W plugs w etch back 130 nm Six Cu Layer 180 nm Six Al Metal layers 250 nm Five Al metal layers, SiOF 350 nm Four Al metal layers, W polish, PSG 90 nm Seven Cu Layer 65 nm Eight Cu Layer Many milestones Oxide Polish STI Polish Poly Polish Tungsten Polish Copper Polish Barrier Polish Wet Station Clean DSS clean Dry in/dry out Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

11 11 Transistors have also been enabled by Don Scansen, Under the hood of Intel s 45nm technology, Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

12 12 s Attributes improved yield Removes defects reduced electromigration enabled optical lithography enabled novel integration schemes Cu damascene technology Enabled upstream modules CVD EP Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

13 The Future (next 10 years) Applied to Many Non-IC Applications (Courtesy Cabot Microelectronics) 13 5-inch FSM Ref: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

14 14 Challenges for the IC Industry The next 10 years Integrating porous ILDs Improving copper dishing, erosion, defects; many more metal layers More tune ability for STI, W, barrier Polishing novel materials 450 mm wafers? 1.5 mm edge exclusion? Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

15 15 ITRS 2007 PLANARIZATION POTENTIAL SOLUTIONS, pg 24 Slurries and Pads

16 A Variety of Materials Make Up Chip Surfaces Oxide SiON Poly Nitride Doped Ox Doped Si 16 Semiconductors Have Changed 15 Elements Smaller Traces; New Materials, Processes and Designs W Ti(N) Al(Cu) Cu Low K High K Ni Silicide Ru +Ta(N) 250 nm chip 32 nm chip 60 Elements (Potential) ULK Source: Spiro et al, Proceedings 2007 ICST Conference, Shanghai. Source: K. Cadien, 2008.

17 17 Fully Tunable Oxide, Nitride, and Poly Polish ( Courtesy Cabot Microelectronics) 1000 Nitride Rate Å/min 2500 Oxide Rate Poly Rate 2500 Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

18 18 Designers Are Demanding More Choice: Example Tungsten Tunability W Ti/TiN PETEOS Selective AP-USG SIN Pad Ox Non-Selective PETEOS PETEOS AP-USG AP-USG SIN Pad Ox i.e.w2000 Courtesy Cabot Microelectronics SIN Pad Ox i.e. W7300

19 19 CMC s s Epic D100 Pad - New Pad Process: Continuous Extrusion, Supercritical CO2, High Density Courtesy Cabot Microelectronics Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

20 20 Pads Optimized for Application Performance Material Selection and Control Interspersed Long/Short Chain Polymers Optimize Number and Regularity of Hard/Soft Domains Control Phase and Void Composition Material Processing: Liquid Casting Custom Tuned Texture Across the Pad Unique Elastic, Viscoelastic and Thermal Properties Both material and processing knobs allow tunability and extensibility of pad properties Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

21 21 Materials/Process Design: Rationale Numerous small hard and soft domains control tribological and thermal properties stable and extended boundary lubrication regime Specific curatives control elastic and viscoelastic properties Grading improve across the wafer uniformity w/o compromising planarization efficiency Solid lubricant reduce motor torque during polish lower friction and lower shear w/o compromising RR Extended & lower COF lower dishing/erosion and stacking faults lower stress on low k dielectrics during Neopad, Ra ~ 2.35um Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

22 22 Innovative Pad Design Enhanced Performance Solo pad technology w/ soft & hard segments in the polymer matrix: Improved planarity within die and within wafer Improved non-uniformity and low edge exclusion Reduce microscratches and lower defects Competitive material polish rates Pad technology designed w/ tunability feature for each application: Provides a novel key process parameter to improve process performance for current and advanced technologies Differentiated Pad Manufacturing Concept: Compression molded In-situ pad grooves ensure uniform, high integrity profiles and provide better slurry distribution and efficiency Enables significant batch-to-batch process control Lower CoO: Material cross-linking: lower wear rates and >2X extended pad life Reduced slurry usage (20-30% reduction) Less defect adders Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

23 23 Very long term - circa 2030 There is definitely an inflection point occurring in the next 20 years Both transistors and interconnects face fundamental change Running out of elements for both transistors and interconnects Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

24 24 ITRS 2007 Emerging Research Devices Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

25 25 Cu interconnect scaling is an issue long term Resistivity increases with reduced film thickness Source: S. M. Rossnagel and T. S. Kuan, Alteration of Cu conductivity in the size effect regime, J. Vac. Sci. Technol. B 22.1., Jan-Feb 2004 Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

26 26 Could Al replace Cu? Timing depends on barrier thickness, resistivity Source: P. Kapur, J. P. McVittie, and K. C. Saraswat, Technology and Reliability Constrained Future Copper Interconnects Part I: Resistance Modeling, IEEE Trans. On Electron Devices, 49, (2002)

27 1000 nm Two Al Metal layers, BPSG 27 Interconnect Scaling & Future Options 500 nm ILD planarization, W plugs w etch back 350 nm Four Al metal layers, W polish, PSG? 250 nm Five Al metal layers, SiOF CNT 180 nm Six Al Metal layers? 3D Options Laser Optical Coupler After several generations of scaling µp Transmitte r circuit Optical modulator Optical WG Receiver circuit Optical Photodetector 65 nm Eight Cu Layer Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, nm Six Cu Layer 90 nm Seven Cu Layer

28 28 What does all of this mean for? Hard to predict Depends on integration scheme s attributes will be relevant does improve yield so whatever the scheme this may be useful Scattering in interconnects is due partially to the roughness of the interconnect... does smooth...cu and optical There is some hope that will be around in 2030 Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

29 29 Summary 3D then optical Continuous improvement Pad & slurry tunability New materials Next 10+ years Transition/paradigm shift in years Depends on design, architecture, etc and beyond Source: K. Cadien, The Future of : Slurries and pads, Keynote presentation, -MIC, Fremont, March 4, 2008.

30 30 Cadien s Summary For the next decade or more - will need to do continuous improvement Improved defects, dishing and erosion Increased tunability for slurries New slurries for new materials Novel pads with more tunability to enable the above How is addressing these? - process understanding embedded in process model - stress-induced failures and reduced force polishing - slurry behavior and slurry design based on mechanics - revive SMART pad?

31 31 Let s zoom in Abrasive Contact Pad asperity Abrasive Tribo-chemical removal Slurry agglomeration Charging issues in lapping induced stress

32 32 Modeling Challenges - Present methods treat process as a black box; are blind to process & consumable parameters Need detailed process understanding For modeling pattern evolution accurately Present methods do not predict small feature well For process design (not based on just trail and error) Multiscale analysis needed to capture different phenomena: At sufficient resolution & speed process less rigid than other processes: possibility of optimizing consumable & process parameters based on chip design MfD & DfM Source of pattern dependence is twofold: Asperity contact area (not addressed yet) Pad hard layer flexion due to soft layer compression (addressed by previous models)

33 33 Adding the electro-chemical effects Develop a transient tribo-electro-chemical model for material removal during copper Experimentally investigate different components of the model Using above model develop a framework for pattern dependency effects. Slurry chemistry (ph, conc. of oxidizer, inhibitor & complexing agent) Pad properties layers hardness, structure Abrasive Type, size & conc. Polishing conditions (pressure P, velocity V) Polished material Incoming topography Model 1. Passivation Kinetics 2. Mechanical Properties of Passive Film 3. Abrasive-copper Interaction Frequency & Force Removal Rate (RR) Planarization, Uniformity, Defects

34 34 Conclusion Continuing evolution of devices and materials offers interesting challenges at many different scales Defect reduction Predictability for slurry/pad development Modeling provides driver for DfM (and MfD) Accommodate new applications of Strategy must allow appropriate detail at any level Data structure should allow inheritance to link higher views to lower views, rapidly Must be well validated/calibrated Needs to be user friendly Requires close interaction with industry drivers

35 35 Thank you for your attention!