Obtaining a Higher V oc in HIT Cells

Transcription

1 PROGRESS IN PHOTOVOLTAICS: RESEARCH AND APPLICATIONS Prog. Photovolt: Res. Appl. 2005; 13: Published online in Wiley InterScience ( DOI: /pip.646 Special Issue Obtaining a Higher V oc in HIT Cells Mikio Taguchi*,y, Akira Terakawa, Eiji Maruyama and Makoto Tanaka Materials and Devices Development Center Business Unit, Sanyo Electric Co., Ltd, 7-3-2, Ibukidai-higashimachi, Nishi-ku, Kobe City, Hyogo , Japan We have achieved a very high conversion efficiency of 215% in HIT cells with a size of 1003cm 2. One of the most striking features of the HIT cell is its high opencircuit voltage V oc, in excess of 710 mv. This is due to the excellent surface passivation at the a-si/c-si heterointerface realized by Sanyo s successful technologies for fabricating high-quality a-si films and solar cells with low plasma damage processes. We have studied ways to treat the surface to produce a good interface throughout our fabrication processes. We have also investigated the deposition conditions of a-si layers for optimizing the barrier height for the minority carriers in the heterojunction. Our approach for obtaining HIT cells with a high V oc is reviewed here. Copyright # 2005 John Wiley & Sons, Ltd. key words: solar cell; a-si; c-si; heterojunction INTRODUCTION Global attention to the solar cell as a promising means of satisfying part of the growing need for an environmentally benign energy supply keeps increasing year by year. The number of solar power generation systems has increased continuously, although the total power generated by these systems is still small compared with world energy needs. To enable solar cells to significantly contribute to preserving the world s energy resources, further cost reduction is necessary. For low-cost solar cells, several approaches have been investigated. Reducing the amount of materials for fabricating solar cells is one solution. A thin (less than 200 mm) wafer slicing technology including kerf loss reduction, and the manufacturing technology for thin wafers are under investigation. 1 This technology is important to prepare for the predicted shortage of silicon material. Thinner active layers (less than 100 mm) are proceeding in the same direction to achieve both high-efficiency and low-cost devices, 2 although they need further efforts to reduce the process cost before proceeding to mass production. High-efficiency solar cells offer an alternative method of cost reduction. The more power a solar cell can generate, the fewer cells are necessary to obtain the same amount of power. It will be important from now on for customers to obtain power from as limited an area as possible. High-efficiency solar cells can also reduce the total system cost as well as the amount of materials needed to fabricate them. * Correspondence to: Mikio Taguchi, Materials and Devices Development Center Business Unit, Sanyo Electric Co., Ltd, 7-3-2, Ibukidaihigashimachi, Nishi-ku, Kobe City, Hyogo , Japan. y m_taguchi@rd.sanyo.co.jp Received 30 November 2004 Copyright # 2005 John Wiley & Sons, Ltd. Revised 10 February 2005

2 482 M. TAGUCHI ET AL. Recently, it seems to be clearer than ever that the direction of achieving both high-efficiency and low-cost device production is the key factor in enhancing solar energy. Polycrystalline silicon (poly-si) is believed to be a good candidate as a low-cost material, compared with mono-crystalline silicon (c-si). However, to obtain high efficiency ( 20%) with a practical size, many problems, such as crystal growth technology to control the grain quality uniformly, light-trapping technology, passivation technology for surface, grain boundary and crystal grains itself, and so on, must be solved. These technologies have been systematically and actively investigated at the laboratory level, 3 but have not been completely adapted to mass production because of the expected cost increase. We believe that a certain level of high-quality materials, accompanied by a low-cost production technology can be a realistic solution for obtaining high-efficiency, low-cost solar cells. In 1974, Sanyo started to investigate amorphous silicon (a-si)-based solar cell technology, and developed various technologies for high conversion efficiency (stable 10% with a size of more than cm). 4 On the basis of a-si solar cell technology using PECVD, we developed a new a-si/c-si heterojunction structure called HIT (heterojunction with intrinsic thin layer). 5 9 This structure features a very thin intrinsic a-si layer inserted between a doped a-si layer and a c-si substrate. This simple yet novel structure has been attracting a growing amount of attention. This is because: (1) it simultaneously enables an excellent surface passivation and p n junction, resulting in high efficiency; (2) its low-temperature processes (<200 C) can prevent any degradation of bulk quality that happen with high-temperature cycling processes in low-quality silicon materials such as solar grade Czochralski Si; and (3) compared with conventional diffused cells, a much better temperature coefficient can be obtained with high-v oc cells. In this paper, the features of the HIT cell and ideas to improve V oc are reviewed. THE HIT CELL Device structure Figure 1 shows the structure of the HIT cell, which is now being mass-produced. The p n junction is realized by the deposition of non-doped a-si and p-type a-si layers on an n-type c-si substrate with the PECVD method. On the bottom side, the back-surface field (BSF) structure is used with non-doped a-si and n-type a-si layers. On both doped layers, transparent conductive oxide (TCO) layers and metal electrodes are formed with the sputtering and screen-printing methods, respectively. All processes are done at temperatures below 200 C. The TCO layer on the top also works as an anti-reflection (AR) coating. The finger electrode on the AR layer is fabricated with 2 mm spacing, which is narrower than that of conventional p n diffused solar cells, to compensate for the high sheet resistance of the TCO layer, whose thickness is optimized for AR coating. For the electrode on the back surface, we also use a finger electrode to make the HIT cell symmetrical so that we can reduce the thermal and mechanical stresses in the device, and thus make this solar cell suitable for various applications, such as Figure 1. The structure of the HIT cell

3 HIGHER V OC IN HIT CELLS 483 Figure 2. Output characteristics of HIT solar cell confirmed by AIST (National Institute of Advanced Industrial Science and Technology) bifacial modules. 9 This symmetrical structure and the low-temperature processes offer the advantage of decreasing the thickness of the cell. High efficiency The most striking feature of the HIT cell is the very high efficiency (>20%) realized with a simple fabrication process. We think that this high efficiency is contributed by the effective carrier trapping within the generation region (c-si) utilizing the double heterostructure. During our basic research in the first half of the 1990s, we achieved efficiency exceeding 20% with a size of 1 cm 2 and found it possible for this structure to achieve both high efficiency and mass production. 7 Then, we shifted our target to develop the technology for the mass production of HIT cells. The first mass production lot of HIT cells with a high conversion efficiency of 173% was shipped in We have continued to make every effort to achieve higher efficiency both in the laboratory and in the factory. Many new technologies for mass production have been developed and adopted. We succeeded in increasing the module efficiency and commercialized 200 W HIT modules in April In this module, the average cell efficiency is 195%. 8 This is quite a high value for a solar cell in mass production. Further, in our laboratory, we have recently achieved an even higher conversion efficiency of 215% (V oc ¼ 0712 V, I sc ¼ 3837 A, fill factor ¼ 787%) with a size of 1003cm 2 as shown in Figure 2. This value was confirmed by AIST (National Institute of Advanced Industrial Science and Technology), Japan. A very high V oc, exceeding 712 mv, is a remarkable value. Improved high-temperature performance The temperature dependence of the solar cell performance has been recognized as one of the most important characteristics for determining output power in practical use. Well-surface passivated solar cells, in other words, high-v oc cells tend to exhibit better temperature dependence compared with traditional c-si solar cells. 10,11 We reported 9 that the HIT cell shows a much better temperature coefficient of 033%/ C than that of a conventional p/n diffused solar cell whose temperature coefficient is 045%/ C. Since our recent progress in efficiency enabled us to obtain quite high V oc, in excess of 710 mv, the temperature coefficient of these cells were measured. Figure 3 shows the cell efficiency normalized at 25 C versus temperature. With our new process

4 484 M. TAGUCHI ET AL. Figure 3. Temperature dependence of conversion efficiency for crystalline silicon solar cells Figure 4. The relationship between V oc and temperature coefficient of power conditions the temperature coefficient has been reduced to 025%/ C. Figure 4 shows the temperature coefficient of the power of various HIT cells plotted as a function of V oc. It is found that there is a good correlation between the temperature coefficients and V oc. It is therefore confirmed that a higher-v oc solar cell is favorable to obtain more power in practical use. As for this correlation between temperature coefficient and V oc of solar cells, more fundamental studies with additional data of various kind of solar cells are under investigation to understand what determines this tendency. THE KEY TECHNOLOGY OF HIGH V OC Importance of the heterointerface In the beginning of our research on the a-si/c-si heterojunction, we started our investigation from a p-type a-si/ n-type c-si heterojunction and faced the poor performance problem of this structure. Inserting a non-doped

5 HIGHER V OC IN HIT CELLS 485 layer into the p-type a-si/n-type c-si heterojunction, we found that the junction properties could be improved drastically. 5 If we try a p/n heterojunction structure now, we still obtain a value for V oc (less than 06 V) that is similar to the data of 15 years ago; meanwhile we can obtain a much-improved V oc in the HIT structure. In the p/n heterojunction, the interface state density caused by the doping materials, which attach to the c-si surface during the deposition process, seemed to deteriorate the junction properties significantly. With the non-doped a-si layer the heterointerface is separated from the doped layer so that these defects caused by the doping materials can be avoided. This implies that the essence of the HIT structure consists in creating a good interface to avoid recombination there. With respect to the influence of the interface state density on the solar cell performance, a numerical analysis of a-si/c-si heterostructure pointed out that the optimum band offset to obtain the high output performance depended on the interface defect density. 12 Si, depending on the interface quality, we have to change our fabrication condition to maximize the output performance. On the other hand, we know that strong electrical field does help reduce the recombination at the heterointerface. Rösch et al. reported in their simulation study that the illuminated I V curve of p-type a-si/n-type c-si cell was nearly unaffected by a defect layer which surface density of states of cm 2. The recombination rate at the heterointerface was suppressed down to much lower level compared with that of crystalline silicon region. 13 Experimentally, however, we often encounter the detrimental effects on the solar cell performance caused by defects at the heterointerface. Although the electrical field can reduce the recombination near the heterointerface, the junction property of this structure is still governed by the interface state density. Therefore, it is important for obtaining high-efficiency solar cells to reduce interface state density and to re-optimize the fabrication condition depending on our interface quality. Reduction of interface state density In order to create a good interface: (1) the c-si wafer should be cleaned as much as possible before being loaded to the CVD system; and (2) high-quality a-si films should be deposited by a low-damage plasma processes. Since we cannot use ultra-high-vacuum process in our production, wafer cleaning before loading the CVD reactor is critical. We set up our original, necessary minimum cleaning process in our laboratory, and have been modifying it to reduce process costs. The wet process has been improved in terms of lifetime measurement by changing the cleaning conditions with an iodine ethanol passivation technique. 14 Controlling the interface properties during a-si deposition is also important. Even if we used the same quality a-si layers, we would have obtained different cell properties due to plasma damage during the deposition. We have reported that the lifetime measurement with the a-si/c-si structure has been useful for optimizing the a-si deposition conditions, including reducing the plasma damage to the c-si surface. 8 Optimizing the deposition condition, including our surface treatment, we have already reported 7 that the surface recombination velocity at the interface between a-si and c-si on the back surface was estimated to be less than 100 cm/s. An even lower surface recombination velocity has been realized in recent HIT cells that show higher V oc. This excellent surface passivation ability of non-doped a-si film on c-si has been intensively investigated by other research institutes and confirmed by various methods. 15 Design of the a-si/c-si heterojunction From our data of V oc and surface recombination velocity, we believe that the HIT cell has a sufficiently low interface state density so as not to have to consider the optimum band offset affected by the interface state density 12 discussed earlier in this paper. We simply need to consider the way to reduce the band offset to block the minority carriers. According to Yablonovitch et al. 16 the ideal solar cell should be built in the form of a double heterostructure. In this configuration a narrower bandgap active layer is sandwiched between two wider bandgap layers of opposite doping. It was also pointed out that the wider bandgap layers may be disordered as long as they still have sufficient electronic quality to support the quasi-fermi level separation in the high-quality narrow-gap active layer. Figure 5(a) shows the ideal double heterostructure where the n-type c-si active layer is between (p/i)- and (i/n)-type a-si layers. In order to collect generated carriers efficiently, the (p/i)-layer should

6 486 M. TAGUCHI ET AL. Figure 5. Band diagram of the HIT cell: (a) ideal double heterojunction; (b) estimated have low barrier for minority carriers and (i/n)-layer should have a large one in the valence band. However, applying the experimentally determined optical bandgap of the a-si layers (16 ev for p-type, 17 ev for i- and n-type) and the electron affinity 17,18 from the literature to the Anderson model, 19 it is found that there is a rather large band discontinuity in the valence band at the (p/i)-a-si/n-type c-si heterojunction (Figure 5b). The numerical analysis of HIT cells pointed out that it is important to control the band offset in the valence band at the heterointerface in order to achieve high performance. 20 On the other hand, from the comparison between our results for the cell parameters as functions of non-doped a-si layer thickness 7 and the simulated data, 20 the carrier blocking effect at the band offset is not so clear as the simulation. It is necessary to measure the band offset of our actual cell to discuss the carrier transport at the interface. Further experiments on the band discontinuity in the HIT cell are under investigation and will be discussed elsewhere. Experimentally, the barrier height can be controlled with the deposition condition of the a-si layers. In the dark I V curves shown in Figure 6, the diffusion current region shifts to a higher voltage and, at the same time, the reverse leakage current decreases with increase in V oc. These samples are fabricated by changing the deposition conditions of non-doped a-si layer. Here, we plotted the curve of the cell whose V oc was 718 mv, but we have obtained even higher V oc exceeding 720 mv in our laboratory, regardless of other parameters. We will continue to investigate new a-si films to achieve further improvements in the heterojunction. CONCLUSION In this paper, we have discussed progress in the efficiency of HIT cells, focusing on our approach to improved V oc. Reduction of the interface state density, control of the heterointerface to give a desirable band offset and the low-damage plasma process are important technologies to obtain higher efficiency in HIT cells. Moreover, from

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