Reducing Contact Resistance Between Ni-InGaAs and n-in 0.53 Ga 0.47 As using Sn Interlayer in n-in 0.53 Ga 0.47 As MOSFETs

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.3, JUNE, 2018 ISSN(Print) ISSN(Online) Reducing Contact Resistance Between and n-in 0.53 Ga 0.47 As using Sn Interlayer in n-in 0.53 Ga 0.47 As MOSFETs Meng Li 1, Geonho Shin 1, Jeongchan Lee 1, Seung Min Lee 2, Jungwoo Oh 2, and Hi-Deok Lee 1 Abstract Self-aligned is a promising source/drain (S/D) contact for high-performance n- InGaAs metal-oxide semiconductor field-effect transistors. An Sn/Ni/TiN (5/15/10 nm) structure deposited by radio frequency sputtering is proposed to provide lower contact resistance at the S/D than the Ni/TiN structure. In the present study, after the formation of by rapid thermal annealing, followed by the selective etching of the TiN capping layer and unreacted Ni, the extracted specific contact resistance was one order of magnitude lower than that of the Ni/TiN (15/10 nm) structure without the Sn interlayer. Furthermore, the /n-in 0.53 Ga 0.47 As junction was well formed without penetration of Ni- InGaAs into the In 0.53 Ga 0.47 As substrate. Sn was found doped throughout the layer to lead to a reduction of contact resistance. Index Terms Contact resistance, metal-oxide semiconductor field-effect transistor (MOSFET), Ni- InGaAs, n-in 0.53 Ga 0.47 As, Sn interlayer I. INTRODUCTION In 0.53 Ga 0.47 As is widely recognized as a suitable candidate for high-performance n-metal-oxide semiconductor field-effect transistors (n-mosfets) on Manuscript received Aug. 25, 2017; accepted Nov. 20, Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea. 2 School of Integrated Technology, Yonsei Institute of Convergence Technology, Yonsei University, Incheon 21983, Korea hdlee@cnu.ac.kr account of its high electron mobility and relatively low band-to-band tunneling leakage [1]. However, the parasitic resistance in source/drain (S/D) of n- In 0.53 Ga 0.47 As MOSFETs could face challenges in satisfying the need of high-performance MOSFETs with the downscaling of devices like silicon. In case of Si MOSFET, while channel resistance and other parasitic resistances decrease or remain the same with the downscaling of channel length, the ratio of contact resistance to other parasitic resistances increases rapidly. Contact resistance dominates the parasitic resistance of devices under the 40 nm node technology [2]. The small sizes of the contacts on the fins of fin field effect transistors (FinFETs), in particular, make it increasingly important to develop solutions to reduce contact resistance for future devices. Self-aligned S/D with metal-alloy-like silicide for Si MOSFETs is a key technology for future highperformance n-in 0.53 Ga 0.47 As MOSFETs [3]. Formation of metal alloy by reaction of Pd, Co, and Ni with In 0.53 Ga 0.47 As has been reported to date [4-8]. has many advantages over Pd-InGaAs and Co-InGaAs and has shown nearly perfect characteristics as a selfaligned material [9, 10]. However, even the contact resistance of /n-in 0.53 Ga 0.47 As is not adequately low for high-performance MOSFETs [11]. More solutions to reduce the contact resistance between Ni- InGaAs and n-in 0.53 Ga 0.47 As are needed to enhance the performance of n-in 0.53 Ga 0.47 As MOSFETs. An Sn/Ni/TiN structure is herein proposed for the formation of. In this study, it was determined that the specific contact resistivity (ρ c ) was reduced by

2 302 MENG LI et al : REDUCING CONTACT RESISTANCE BETWEEN AND n-in 0.53Ga 0.47As USING Sn INTERLAYER IN Native oxide removal Patterning (lift-off lithography) Deposition (RF sputter) Sn/Ni/TiN (5/15/10 nm) Ni/TiN (15/10 nm) Removal of photoresist alloy (Ni/TiN) In 0.53 Ga 0.47 As Semi-insulating InP r r s s RTA 300 C 30 s Selective etching (concentrated HCl) alloy(sn/ni/tin) In 0.53 Ga 0.47 As Semi-insulating InP Fig. 1. Process flow for fabrication of CTLM pattern and planar resistor pattern. more than one order compared to the reference structure of Ni/TiN. The possible mechanism was additionally investigated and is discussed in this paper. II. EXPERIMENTS Si-doped In 0.53 Ga 0.47 As (150 nm) with a doping concentration of cm 3 was grown on semiinsulating InP wafer by molecular beam epitaxy (MBE). A circular transfer line method (CTLM) was used to evaluate the contact resistance and extract the ρ c [12]. The process flow for the fabrication of CTLM and planar resistor patterns is summarized in Fig. 1. After cleaning by an NH 4 OH solution, the surface was passivated using (NH 4 ) 2 S for 10 min. The CTLM and planar resistor patterns were fabricated by a lift-off process. Sn, Ni, and TiN layers were sequentially deposited by radio frequency (RF) sputtering for Sn/Ni/TiN (5/15/10 nm) films. With the same Ar gas flow of 1.8 SCCM at a working pressure of Torr, the RF power for deposition of Sn, Ni, and TiN were 50 W, 100 W, and 80 W, respectively. A sample with a Ni/TiN (15/10 nm) structure was also fabricated as a reference. was formed by rapid thermal process (RTP) at 300 C for 30 s after the photoresist was stripped [13]. Then, selective wet etching by concentrated HCl solution was carried out to remove unreacted Ni and the capping layer TiN [14]. Current voltage (I-V) characteristics were measured by a four-point probe method for the CTLM pattern [15]. The formed alloy was investigated by X-ray diffraction (XRD) analysis. Field emission transmission electron microscopy (FE-TEM) was used to observe the cross-section of the formed films Fig. 2. Schematic diagram of fabricated CTLM pattern. and interfaces. Depth profiles of ingredients were studied by secondary ion mass spectrometry (SIMS). Fig. 2 presents a schematic diagram of fabricated samples with CTLM patterns. The radius of the inner ring (r) of the CTLM pattern is 80 μm, and the gap (s) is split at 12, 16, 20, 24, 32, 40, and 48 μm. III. RESULTS AND DISCUSSION The total resistance (R T ) was measured by a fourterminal method, and ρ c was extracted using the following equations: Rsh RT = ( s + 2 LT ) C, 2p r (1) r s C = ln(1 + ), s r (2) r c = R 2 shlt. (3) where R sh is the sheet resistance, C denotes the correction factor, and L T is the effective transfer length. Measured R T is shown in Fig. 3. It was found that R T was reduced in the structure of Sn/Ni/TiN, which indicated an improvement of contact at the and n-ingaas interface. The extracted ρ c of Sn/Ni/TiN case by Eqs. (1-3) shows great reduction from (Ni/TiN) to Ωcm 2. Although it needs further improvement of contact resistance, it showed potential for reduction of contact resistance by combining other techniques. We conducted 2theta and 2theta omega XRDs to observe the effects of the Sn interlayer in the reaction between Ni and In 0.53 Ga 0.47 As. As shown in Fig. 4(a), the Sn/Ni/TiN structure demonstrates more polycrystalline peaks at different degrees than the Ni/TiN structure. In

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.3, JUNE, R T [W] Ni/TiN (15/10 nm) Sn/Ni/TiN (5/15/10 nm) Gap Space [mm] Fig. 3. Measured total resistance as a function of gap space. Intensity (c/s) Ni In Ga As Depth [nm] (a) n-ingaas Si Concentration [cm -3 ] Intensity (A. U.) (101) (002) (102) (201) (212) Theta (degrees) (a) Sn/Ni/TiN 5/15/10 nm Ni/TiN 15/10 nm Sn/Ni/TiN 5/15/10 nm Ni/TiN 15/10 nm Intensity (c/s) Ni In Ga As Sn Depth [nm] (b) n-ingaas Concentration [cm -3 ] Fig. 5. Depth profile of elements for a sample with (a) Ni/TiN, (b) Sn/Ni/TiN structures after RTA analysis by SIMS. Si Intensity (A. U.) Theta/Omega (degrees) (b) Fig. 4. XRD spectra of the formed alloy (a) 2theta, (b) 2theta omega. addition to the crystalline peak of the substrate at 63.4, the crystalline peak of at 88.8 is observed in Fig. 4(b) [16]. More grains with different grain directions can be expected to form with the Sn interlayer. Depth profiles of elements analyzed by SIMS are depicted in Fig. 5. As shown in Fig. 5(b), Sn is diffused and doped throughout the layer and ends in the substrate of the In 0.53 Ga 0.47 As layer. The intensity of Sn gradually decreases as the depth increase from the surface, indicating that Sn does not react and form alloy with. The Au-Sn system has been proposed as a material of ohmic contact to n-gaas, while Sn is also recognized as an n-type dopant in III-V semiconductors. Sn may dope and introduce additional donors to and n-in 0.53 Ga 0.47 As [17]. Moreover, quick out-diffusion of dopant Si onto surface could be observed in the reference sample. However, that did not happen in the sample with Sn interlayer. It seems that the quick dopant out-diffusion was suppressed by Sn. Besides, increased intensity ratio of In to Ga also can be observed in the formed alloy of the sample with Sn interlayer, which could lead to a reduction of resistivity for In x Ga 1-x As. Thus, reduced resistivity and more free carriers can be provided for the greater current transference between and n-in 0.53 Ga 0.47 As.

4 304 MENG LI et al : REDUCING CONTACT RESISTANCE BETWEEN AND n-in0.53ga0.47as USING Sn INTERLAYER IN Sn/Ni/TiN Ωcm2 with the introduction of the Sn interlayer. The formation of more polycrystalline structures indicated that Sn atoms existed at the grain boundary of the. More current paths through the grain boundary and donors can be expected by the introduction of the Sn interlayer. In addition, a good /ningaas junction without penetration of into the substrate was confirmed by FE-TEM. The Sn/Ni/TiN structure is thus a promising solution for improving the performance of n-ingaas MOSFETs with self-aligned S/D regions. In0.53Ga0.47As ACKNOWLEDGMENTS 20 nm Fig. 6. FE-TEM micrograph of the /n-in0.53ga0.47as junction formed by RTA of the Sn/Ni/TiN structure. Insets show diffraction patterns of the and n-in0.53ga0.47as lattice. Therefore, resistance reduction of and reduced contact resistance between and nin0.53ga0.47as can be expected by the introduction of Sn interlayer. Fig. 6 presents FE-TEM cross-section images of the sample with the Sn interlayer. The /nin0.53ga0.47as junction is well formed without penetration of into the In0.53Ga0.47As substrate. The insets show diffraction patterns of the and In0.53Ga0.47As lattice. The substrate In0.53Ga0.47As has a good crystalline structure, which agrees with the results of XRD. The shows a combination of crystalline and polycrystalline structures, which corresponds to the peaks observed in the sample with the Sn interlayer by XRD. This research was supported by the Ministry of Trade, Industry and Energy (MOTIE; ) and the Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices. The authors thank the Daegu Centers of the Korea Basic Science Institute (KBSI) for the XRD analysis, and the National NanoFab Center (NNFC) in Daejeon for the SIMS analysis. REFERENCES [1] [2] [3] IV. CONCLUSIONS [4] Sn interlayer was introduced into the self-aligned S/D with alloy to reduce the contact resistance between and doped InGaAs region for highperformance n-ingaas MOSFETs. It was found that Sn did not react with ; rather, it was doped throughout the layer after RTA. The specific contact resistivity was reduced from to [5] S. Oktyabrsky and P. D. Ye, Properities and Trade-Offs of Compound Semiconductor MOSFETs, Fundamentals of III-V Semiconductor MOSFETs (Springer Science+Business Media LLC, 2010), Chap. 2. S.-D. Kim, et al, Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime-Part II: Quantitative Analysis, IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp , Mar J. A. del. Alamo, Nanometre-scale Electronics with III-V Compound Semiconductors, Nature, Vol. 479, pp , Nov., E. Y.-J. Kong, et al, Investigation of Pd-InGaAs for the Formation of Self-aligned Source/Drain Contacts in InGaAs Metal-Oxide-Semiconductor Field-Effect Transistors, Solid-State Electronics, Vol. 85, pp , July, S. Kim, et al., In0.53Ga0.47As Metal-OxideSemiconductor Field-Effect Transistors with Selfaligned Metal Source/Drain Using Co-InGaAs

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.3, JUNE, alloys, Applied Physics Letters, Vol. 100, No. 7, pp , Feb., [6] Ivana, et al., CoInGaAs as a Novel Self-aligned Metallic Source/Drain Material for Implant-less In 0.53 Ga 0.47 As n-mosfets, Solid-State Electronics, Vol. 78, pp , Dec., [7] X. Zhang, et al., In 0.7 Ga 0.3 As Channel n-mosfet with Self-aligned Source and Drain, Electrochemical and Solid-State Electronics, Vol. 14, No. 2, pp. H60-H62, [8] X. Zhang, et al, Multiple-Gate In 0.53 Ga 0.47 As Channel n-mosfets with Self-Aligned Ni- InGaAs Contacts, ECS Journal of Solid State Science and Technology, Vol. 1, No. 2, pp , July, [9] P. Shekhter, et al., Epitaxial NiInGaAs Formed by Solid State Reaction on In 0.53 Ga 0.47 As: Structure and Chemical Study, Journal of Vacuum Science & Technology B, Vol. 31, No. 3, pp , Apr., [10] Ivana, et al., Photoelectron Spectroscopy Study of Band Alignment at Interface Between and In 0.53 Ga 0.47 As, Applied Physics Letters, Vol. 99, No. 1, pp , July, [11] J. A. del Alamo, et al., Nanometer-Scale III-V MOSFETs, IEEE Journal of the Electron Devices Society, Vol. 4, No. 5, pp , Sept., [12] D. K. Schroder, Contact Resistance and Schottky Barriers, Semiconductor Material and Device Characterization, John Wiley & Sons, Inc., 2006, pp [13] C. Perrin, et al., Formation of Ni 3 InGaAs Phase in Ni/InGaAs Contact at Low Temperature, Applied Physics Letters, Vol. 109, No. 13, pp , Sept., [14] S. Subramanian, et al., Selective Wet Etching Process for Contact Formation in InGaAs N-MOSFETs with Self-aligned Source and Drain, ECS Journal of The Electrochemical Society, Vol. 159, No. 1, pp. H16-H21, Jan., [15] Dieter K. Schroder, Resistivity, Semiconductor Material and Device Characterization, John Wiley & Sons, Inc., 2006, pp. 2. [16] S. Mehari, et al., Measurement of the Schottky Barrier Height between Alloy and In 0.53 Ga 0.47 As, Applied Physics Letters, Vol. 101, No. 7, pp , Aug., [17] V. L. Rideout, A Review of The Theory and Technology for Ohmic Contacts to Group III-V Compound Semiconductors, Solid-State Electronics, Vol. 18, No. 6, pp , June, Meng Li was born in China in He received a B.S. degree in electronics engineering from Mokwon University, Daejeon, Korea, in He is currently working toward the Doctor s degree in the Department of Electronics Engineering, Chungnam National University, Daejeon, Korea. His research interests include nickel silicide, contact resistance in Ge and InGaAs for self-aligned S/D of MOSFETs, Schottky barrier MOSFETs as well as high efficient silicon solar cells. Geon-Ho Shin received a B.S. degree in electron engineering in 2016, and is currently working toward an M.S. degree in the Department of Electronics Engineering from the Chungnam National University, Daejeon, Korea. His research interests include nickel silicide, nickel germanide and germanium MOSFETs. Jeongchan Lee received a B.S. degree in electronic engineering in 2016, and is currently working toward an M.S. degree in the Department of Electronics Engineering from the Chungnam National University, Daejeon, Korea. His research interests include nickel silicide and treatment of semiconductors.

6 306 MENG LI et al : REDUCING CONTACT RESISTANCE BETWEEN AND n-in 0.53Ga 0.47As USING Sn INTERLAYER IN Seung Min Lee received the B.S. and M.S. degree from the Department of Electronic Engineering, Incheon National University, Incheon, Korea in 2012 and He is currently pursuing the Ph.D. degree in the School of Integrated Technology from Yonsei University, Korea. His interests include crystallography of ALD BeO, AlGaN/GaN MOS- HEMTs, 4H-SiC MOSFETs, reliability of transistors. Jungwoo Oh is an associate professor at Yonsei University in the school of integrated technology (Incheon Korea). He worked as a project engineer with the Front End Processes Division at SEMATECH (Austin, TX USA), investigating nanoscale CMOS devices and assessing potential alternative material properties to replace silicon for nextgeneration CMOS technology. At the SEMATECH consortium, he works with leading semiconductor manufacturers and state government to solve common manufacturing problems by leveraging resources. Dr. Oh holds a doctorate in materials science and engineering from the University of Texas at Austin. His Ph.D. research was in the area of germanium-silicon-based CMOS photonics. He also earned a master s degree in materials science and engineering from POSTECH and a bachelor s degree from Yonsei University. Hi-Deok Lee received B.S., M.S., and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1990, 1992, and 1996, respectively, all in electrical engineering. In 1993, he joined LG Semicon Co., Ltd. (currently SK hynix Semiconductor), Cheongju, Korea, where he was involved in the development of 0.35-, 0.25-, and 0.18-μm CMOS technologies, respectively. He was also responsible for the development of and 0.13-μm CMOS technologies. Since 2001, he has been with Chungnam National University, Daejeon, and now is Professor with the Department of Electronics Engineering. From 2006 to 2008, he was with the University of Texas, Austin, and SEMATECH, Austin, as a Visiting Scholar. His research interests are nanoscale CMOS technology and its reliability physics, silicide technology, and test element group design. His research interests also include sensitivity improvement of sensors, and development of high performance sensors. Dr. Lee is a member of the Institute of Electronics Engineers of Korea. He received the Excellent Professor Award from Chungnam National University in 2001, 2003 and 2014.