EE CMOS TECHNOLOGY- Chapter 2 in the Text

Transcription

1 1 EE 212 FALL CMOS TECHOLOGY- Chapter 2 in the Text In this set of notes we will describe a modern CMOS process flow. In the simplest CMOS technologies, we need to realize simply MOS and MOS transistors for circuits like those illustrated below. Typical CMOS technologies in manufacturing today add additional steps to implement multiple device V TH, TFT devices for loads in SRAMs, capacitors for DRAMs etc. rocess described here will require 16 masks (through metal 2) and > 100 process steps. There are many possible variations on the process flow described here, some of which are described in Chapter 2 in the text. See the STI section in the text especially. + V + V I 1 MOS I 2 OUTUT OUTUT IUT MOS GD GD JD, MDD, BG

2 2 D D G Sub G Sub S S G D S G D S MOS Substrate Well - MOS Substrate Final result of the process flow we will consider. JD, MDD, BG

3 3 hotoresist Si 3 4 SiO 2 Si, (100), Type, 5-50 Ωcm Substrate selection: moderately high resistivity, (100) orientation, type. Wafer cleaning, thermal oxidation ( 400 Å), nitride LCVD deposition ( 800 Å), photoresist spinning and baking ( µm). Mask #1 patterns the active areas. The nitride is dry etched. JD, MDD, BG

4 4 Field oxide is grown using a LOCOS process. Typically C in H 2 O grows 0.5 µm. Boron Implant Mask #2 blocks a B + implant to form the wells for the MOS devices. Typically cm KeV. JD, MDD, BG

5 5 hosphorus Implant Implant Mask #3 blocks a + implant to form the wells for the MOS devices. Typically cm KeV. Well A high temperature drive-in produces the final well depths and repairs implant damage. Typically C C or equivalent Dt. JD, MDD, BG

6 6 Boron Well Mask #4 is used to mask the MOS devices. A V TH adjust implant is done on the MOS devices, typically a 1-5 x cm -2 B KeV. Arsenic Well Mask #5 is used to mask the MOS devices. A V TH adjust implant is done on the MOS devices, typically 1-5 x cm -2 As KeV. JD, MDD, BG

7 7 Well The thin oxide over the active regions is stripped and a new gate oxide grown, typically Å, which could be grown in C in O 2. Well olysilicon is deposited by LCVD ( 0.5 µm). An unmasked + or As + implant dopes the poly (typically 5 x cm -2 ). JD, MDD, BG

8 8 Well Mask #6 is used to protect the MOS gates. The poly is plasma etched using an anisotropic etch. hosphorus - Implant Well Mask #7 protects the MOS devices. A + implant forms the LDD regions in the MOS devices (typically 5 x cm 50 KeV). JD, MDD, BG

9 9 Boron - Implant - Implant Well Mask #8 protects the MOS devices. A B + implant forms the LDD regions in the MOS devices (typically 5 x cm 50 KeV). - Implant - Implant Well A conformal layer of SiO 2 is deposited (typically 0.5 µm). JD, MDD, BG

10 10 - Implant - Implant Well Anisotropic etching leaves sidewall spacers along the edges of the poly gates. Arsenic + Implant Well Mask #9 protects the MOS devices, An As + implant forms the MOS source and drain regions (typically 2-4 x cm 75 KeV). JD, MDD, BG

11 11 Boron + Implant + Implant Well Mask #10 protects the MOS devices, A B + implant forms the MOS source and drain regions (typically 1-3 x cm 50 KeV) Well A final high temperature anneal drives-in the junctions and repairs implant damage (typically C or 1 min 1000 C). JD, MDD, BG

12 Well An unmasked oxide etch allows contacts to Si and poly regions Well Ti is deposited by sputtering (typically 1000 Å). JD, MDD, BG

13 Well The Ti is reacted in an 2 ambient, forming TiSi 2 and Ti (typically C) Well Mask #11 is used to etch the Ti, forming local interconnects. JD, MDD, BG

14 Well A conformal layer of SiO 2 is deposited by LCVD (typically 1 µm) Well CM is used to planarize the wafer surface. JD, MDD, BG

15 Well Mask #12 is used to define the contact holes. The SiO 2 is etched. W Ti Well A thin Ti barrier layer is deposited by sputtering (typically a few hundred Å), followed by W CVD deposition. JD, MDD, BG

16 Well CM is used to planarize the wafer surface, completing the damascene process Well Al is deposited on the wafer by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it. JD, MDD, BG

17 Well Second level metal is deposited and defined in the same way as Al level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si 3 4 is deposited by ECVD and patterned with Mask #16. This completes the CMOS structure. The processing details and some process options are described in Chapter 2 in the text. JD, MDD, BG