ECSE 6300 IC Fabrication Laboratory Lecture 8 Metallization. Die Image

Transcription

1 ECSE 6300 IC Fabrication Laboratory Lecture 8 Metallization Prof. Rensselaer Polytechnic Institute Troy, NY Office: CII-6229 Tel.: (518) s: luj@rpi.edu /index.html 8-1 Die Image = Rectangular FETs = Circular Geometry FETs = Capacitors = Resistance Macros = Alignment and CD Structures Test Structures: C=Capacitors R=Resistors VdP=Van de Pauw structures K=Kelvin TLM=Transmission Line Structures n + -Cap p-cap Cross Section ILD-Cap Al Contact ILD Oxide Field Oxide Source Gate Drain Gate Source Silicon Rectangular MOSFETs: W/L(µm) = 20/2, 40/4,100/10, 400/40, 600/60, 800/80,1000/100 Circular MOSFETs: L = 6, 10, 40, 60, 80, 100 µm 8-2

2 Lecture Outline Metallization in a MOSFET Desired Properties of Metallization Physical Vapor Deposition (PVD) Equipment Plasma and Chemical Etching of Metals Post Metal Processing and Si Precipitates Electromigration Multilevel Metallization Future Trends Note: The lecture slides were prepared based on the original materials written by Profs. T.P. Chow and J.-Q. Lu 8-3 Metallization in a MOSFET Drain Most commonly used Gate Doped poly-si Source and Drain - Aluminum Gate Source 8-4

3 Desired Properties of Metallization Applications: gate, contact (ohmic, schottky), interconnect, solder pad 8-5 Metallization Properties Add Cu! ρ ~ 1.7 µω-cm T m ~ 1084 C α ~ 16.5 ppm/ C Resistivity: ρ (µω-cm) Ag 1.6 Cu 1.7 Au 2.2 Al 2.7 W >5 Ta >13 Ti >40 Si: T m ~ 1414 o C α ~ 2.6 ppm/ C 8-6

4 Metallization Choices 8-7 Process Capabilities of Metallizations Add Cu! 8-8

5 Physical Vapor Deposition Equipment (PVD) Cryo-pump is preferred over diffusion pump for cleanliness (oil back diffusion in the latter) Vacuum Contamination 8-9 Physical Vapor Deposition Thickness control/monitor Uniformity Planetary Cosine Law of Deposition (mass/area): R D =(M e / r 2 )cos cos PVD is line-of-sight PVD includes - Sputtering - Evaporation RPI CVC sputter? Wafers are held upside down to minimize particulates Mean free path: kt cm 2 P 2 P(Pa) (RT, =3Å) 8-10

6 PVD Step Coverage Actual Simulated 8-11 Plasma Etching of Metals Cu?? 8-12

7 Chemical Etches for Metals Acetic : Nitric : Phosphoric : Water 8-13 Post Metal Processing 8-14

8 450 C sintering to ensure good interactions Si precipitates upon cooling at the Al/Si interface -- Al-1% Si alloys are used to prevent excessive silicon consumption 0.5% Cu (discovered accidentally) is also added to prevent electromigration Al/Si Interactions Pits observed after Al etch 5 µm 8-15 Al/Si Interactions Al/Si interaction is a thermally activated, diffusion-limited process 8-16

9 Si Precipitation Si precipitates in and around a contact window in SiO 2 after Al is etched off Solution: diffusion barriers self-aligned silicides (reliable & reproducible clean interface) Resistance change in diffused resistors with Al/Si alloys after 200 C aging 8-17 Specific Contact Resistivity R C = (dv/dj) V=0 R C = f ( B, N D ) B Metal/Si barrier height N D surface doping concentration of semiconductor R C is sensitive to surface native oxide Barrier layer is sometimes added to ensure contact reproducibility and stability Ohmic Contacts Ohmic Contact Schottky Contact n type B 8-18

10 Self Aligned Processes in ULSI CMOS (a) Gate oxide Thermal Oxidation (d) (b) Poly-Si Dep,/Dope, Si3N4, Patterning, S/D Implant (c) (e) Annealing to form silicide, selective wet etch SiO2 Dep., Patterning/RIE, Wet Si3N4 Etch Sidewall Spacer ( Bernie Spacer) 8-19 Electromigration Electromigration occurs due to: - Direct influence of electric field - Electrons facilitating atom diffusion 8-20

11 Electromigration MTF Electromigration mean time to failure (MTF) depends on grain structures and linewidth, thus on deposition method E Beam Evaporated Sputtered MTF J -n exp(-q/kt) J: conduction current density Q: activation energy In Source Al Evaporated 0.5% Cu (discovered accidentally) is added to prevent electromigration 8-21 Al/Si Film Grain Structures (grain boundaries, dislocations and point defects) E-gun Al (0.5%Cu) 2.2 m wide line 1.0 m wide line Bamboo texture preferred 8-22

12 Multilevel Metallization Planarization (CMP) at each level is the key! Cu has replaced Al in upper (global) or almost all levels of metallization because of lower ρ & longer EM MTF SEM view of IBM's first-to-market 6 level copper interconnect technology Si Fin Ox Intel 22-nm PMOS tri-gate transistor (a) & S/D region (b) 8-24

13 IC Technology: Present and Future Present/Future Logic (ITRS 2008) NEC embedded DRAM cell* 3D integration Via Wire Intel 6-core Xeon 7400 Si 45nm 16MB L3 503mm 2 1.9B Ts W A New Paradigm for Future Technologies 8-25 Future Trends Cu has replaced Al in upper (global) or almost all levels of metallization (EM & R) Low k ILD has been explored to replace oxide/nitride ILD to minimize capacitance (C) coupling between interconnects Damascene patterning/planarization (CMP) is the key process step in multilevel metallization Metal deposition techniques: PVD, CVD, ECP, ALD 3D interconnect/packaging has been enabling high performance memory and smart systems 8-26