A New 2.5D TSV Package Assembly Approach

Transcription

1 A New 2.5D TSV Package Assembly Approach Yuan Lu 1,2, Wen Yin 1,2, Bo Zhang 1,2, Daquan Yu 1,2, Lixi Wan 2, Dongkai Shangguan 1,2 Guofeng Xia 3, Fei Qin 3, Mao Ru 4, Fei Xiao 4 1 National Center for Advanced Packaging, Wuxi, Jiangsu, , P.R. China 2 Institute of Microelectronics, Chinese Academy of Sciences, Beijing, , P.R. China 3 College of Mechanical Engineering & Applied Electronics Technology, Beijing University of Technology, Beijing, , P.R. China 4 Department of Material Science, Fudan University, Shanghai, , P. R. China Phone: ; yuanlu@ncap-cn.com Abstract Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, siliconbased device integrations, the TSV s, have become the main stream of 3D packaging technologies. TSV s can be further classified as 2.5D and 3D TSV s. For 2.5D TSV package assembly, since multiple components involved, there are normally two assembly process approaches, i.e., from Topto-Bottom (TOB), or from Bottom-to-Top (). Each approach has its own pros and cons. From stress minimization aspect, TOB is more desirable. But from packaging assembly easiness viewpoint, is more practical and thus has been mainly utilized. To overcome these dilemmas occurred in 2.5D TSV package assembly, a new assembly process approach, called new TOB (n-tob), has been developed. Instead of bonding the onto the, the n-tob starts out with precisely bonding the onto the with using a specially-designed eccentric-axis pickup tip which also effectively protects the flip C4 bumps on the backside during bonding. Finite-element (FE) simulation and reliability tests were employed to assess the effectiveness and impact of this new assembly approach on 2.5D TSV packages. The assessment results show that n-tob is feasible with at least the same performance in both package assembly and reliability. Introduction To enable the miniaturization, better electrical performance and more functionalities, three-dimensional (3D) integration has drawn more and more attention[1,2]. Using high dense vertical interconnects and ultra fine pitch microbumps ( -bumps), the silicon packages, i.e., through-silicon via (TSV), have stood out and become the 3D packaging main stream [3-7]. In structure, silicon packages have been further classified as 2.5D and 3D TSV s. The main difference between these two is whether a common silicon, which is primarily utilized for signal distribution and pitch fanout, is used. Due to its simplicity in handling power density and distribution, and heat removal, 2.5D TSV is more attractive [8,9]. A 2.5D TSV package normally consists of (s), a Si and a substrate (either a BT laminate or a LTCC). There is a micro-bump array with ultra-fine pitch for the. For the, there is a micro UBM pad (or mini bump) array on its frontside and a flip bump array with relatively relaxed pitch on the backside. For the BT (or LTCC) substrate, there is a pattern matching to that of the on its frontside and a SMT compatible pad (or ball) array on the backside. 2.5D TSV package fabrication involves silicon via and redistribution layer (RDL) formation, micro-bumping and package assembly. Large number of TSV publications so far has been dedicated to Si via and RDL formation, and micro-bumping, but very few to TSV package assembly. For 2.5D TSV package assembly, there are two approaches: from top to-bottom (TOB) and from bottomto-top (). TOB starts out with the first being bonded onto the. Then the super ( and ) is bonded onto the. For, the is first bonded onto the. Next, the is attached onto the. Each approach has its own pros and cons. The concept of TOB is straight forward. However due to the fact there are bumps on both the frontside and backside of an, it could be annoyed to protect the flip bumps on its backside from damage during bonding. For, the second bonding ( onto ) normally is poor due to Si warpage, which is attributed to the thermal stress generated during the first bonding because of coefficient-of-thermal-expansion (CTE) mismatch between the and [10]. The dilemmas encountered in these two different assembly approaches were depicted in a cartoon (Figure 1). TOB Figure 1. A cartoon showing the dilemmas occurred in both 2 5D TSV assembly approaches. In this work, a new packaging approach has been developed to assemble the simplest 2.5D TSV package that is composed of a, an and a. This approach is a new version of TOB (n-tob), aiming at solving the issue of protecting the flip bump array on the /13/$ IEEE Electronic Components & Technology Conference

2 backside. Thanks to a specially designed eccentricaxis pickup tip, the new approach uses the as the substrate and it accurately bonds the onto the. Since there is a recess cutout in the tip, the flip array of the is properly protected during bonding. Using as the reference, a comparison study was conducted to assess the effectiveness of n-tob approach and its impact on 2.5D TSV assembly and reliability. The assessment was accomplished through assembly yield analysis, finite-element (FE) simulation and reliability tests. There is no global CTE mismatch between the and as the same substrate material, silicon, is used for both components. CTE mismatch-induced long-term thermal stressing is probably not the main issue for the package reliability [11]. However, since thousands of solder -bumps are used, risks of abrupt reliability failures due to interconnect interfacial intermetallics (IMC) layer coarsening and microcrack initiation during possibly severe thermal and/or mechanical shocks in field services exist. The reliability concerns were addressed by performing multireflows (thermal shock) at lead-free reflow temperature (260 C) and drop test (mechanical shock). Electrical probing was utilized to monitor the reliability testing output. Experiment The 2.5D TSV testing vehicles used in this study consisted of a test ( mm 3 ), a Si ( mm 3 ) and a 6-layer ( mm 3 ). There were bumps at 50 m pitch on the test. The interconnects ( -bumps) of the were constructed using Cu pillar technology. There was a 300 mpitch lead-free flip bump array on the backside. The total number of flip bumps was 1190 with a bump diameter of 100 m. Various daisy chain structures were designed into the test s and for electrical assessments. The builds of testing vehicles were designed as two groups, Group A and Group-B. Group-A was packaged and assembled through n-tob assembling processes; while Group-B through processes. The details of n-tob and process flows are illustrated in Figure 2. To minimize thin Si substrate warpage impact, a Finetech thermalcompression flip bonder was utilized for precise -to bonding with controlled ambient in both n-tob and An eccentric-axis pickup tip was specially designed, and some tool hardware was modified for the Finetech bonder when executing the n-tob. Underfilling was applied to the space both between the and, and between the and. The underfill materials were the same for the samples built by n-tob and assembly approaches. With using ANSYS (ver. 12.1), finite-element analysis was employed to simulate the 2.5D TSV package assembly. Both n-tob and assembly approaches were modeled. Some details of models establishment were given in Figure 3 and Table 1. After assembly, the TSV package samples of Group-A and Group-B were mixed and re-grouped as two reliability testing groups, going through multireflow (thermal shock) and drop test (mechanical shock), respectively. Multireflow experiment was carried out with using a Speedline belt furnace. The reflow peak temperature was 255 C 258 C, with inert gas reflow environment. 16 TSV sample packages (8 from each assembly group) were used for multireflow experiment. After multireflow stressing, the samples were electrically probed to check electrical connections. n-tob Figure 2.2.5D TSV assembly process flows: n-tob vs Figure 3. Brief descriptions of FE model establishment The drop test was performed using a Suchi shock testing system. The test conditions were: half-sine wave, acceleration of 1500 Gs with a pulse duration of 0.5 ms, according to JESD22-B111 standard. The testing PCB boards were made of eight-layer FR4 material with a size of mm 3. Each test board contained 4 or 6 samples which were symmetrically fastened to the PCB by using strong adhesive tapes. The samples from n-tob and were randomly grouped for every board. Total 20 sample packages (10 from each n-tob and group) were subjected to the mechanical shock. Each sample received 30 drops, according to the JEDEC spec. After mechanical shock, the samples were re-probed to check electrical continuity, with failure defined as an open chain. 1966

3 Table 1. Materials Properties Used in the FE Models Figure 6. Comparison of stress/strain distribution in the -bump after reflow for n-tob vs. Results and Discussions The 2.5D TSV packages assembled by using n-tob looked good. The key bonding, i.e., test -to-, was done by the Finetech, with using the eccentric-axis pickup tip and modified optoelectronic hardware. The bonding quality was confirmed by x-ray inspection (Figure 4). Figure 7. Comparison of stress/strain distribution in the solder joints (flip bump) after reflow for n-tob vs. Table D TSV Package Warpage Comparison: n-tob vs. Figure 4. X-ray photographs showing the bonding between the test and (using n-tcb). A: an overview. B: a magnified photo of A. Assembly yields were obtained for the 2.5D TSV units produced via both n-tob and after sample builds and electrical probing. Generally, the assembly yield was higher (about 10% 15%) for the units assembled with n-tob process flow, compared to those built with A completed TSV sample package (using n-tob) can be seen in Figure 5. Figure 5. A completed 2.5D TSV package The key results of FE simulation on the 2.5D TSV packages built by using different assembly approaches were summarized in Figures 6 and 7, and Table 2. With comparing the results of FE modeling on the sample packages built by using n-tob to those made by using, following conclusions can be drawn: - Stress/strain levels of both -bump and flip C4 bump after reflow for n-tob are lower than those for - The final warpages of the and have almost the same values for both assembly approaches. - The warpages of the after first reflow and first underfilling for n-tob were virtually equal to zero, comparing to the large value for - From stress/strain and warpage standpoint, n-tob is a preferred assembly approach. Post multireflow e-probing results were summarized in Table 3. It can be seen that the units built using n-tob performed relatively better. About 87% n-tob units were still good after multireflow, compared to about 62.5% units for the However, it is noted that failures still existed for both 1967

4 approaches. Cross section scanning electron microscopy was performed for the samples from as-received components, asassembled (both n-tob and groups) and postmultireflow units. Microanalysis indicated that the Sn constituent was quite small in the Cu pillar for the as-received components. For the as-assembled units (built through either n-tob or ), there was no elemental Sn left in the solder interconnects between the and, all converted into Cu-based intermetallics (IMC). For the post-multireflow units, the interfacial IMCs were quite coarsened. Some microcracks were observed in the - interconnect. It is thought that conversion of Sn, rapid coarsening of the interfacial IMC s and microcrack initiation and propagation during multireflow were making the interconnects brittle and failed. Table 3. Electrical Test Results After Multireflow Flow ID T=0 Multireflow Delta A A A A n-tob A A bad bad A A Ave Sted B B B bad bad B bad bad B B B B bad bad Ave 17.8 Sted The mechanical shock (drop test) experiment was performed with an impact tolerance < 10%. A sample of the impact curves is provided in Figure 8. Figure 8. A sample of the impact curves used in the drop test. Post-mechanical shock electrical probing results indicated that all the units were OK, passing the failure criteria (Table 4). This suggested that the 2.5D TSV packages built with using either assembly approach were robust. The results of multireflow and drop test suggest that for a 2.5D TSV package, attention needs to be paid to thermalinduced failure even though no global CTE mismatch exist and underfill is applied. This is due to that solder is utilized as the bulk interconnect material and thus interfacial reaction between the solder and metallization of the substrate surface cannot be evaded, This also implies that choosing which assembly process flow (approach) probably has a relatively small impact on the 2.5D TSV package reliability, despite such selection has an effect on the assembly yield. Theoretical studies confirmed the experiment results. Finite-element simulations indicate that the final warpages (strain) of the and of have almost the same values for the TSV packages constructed by both assembly approaches. This hints, once the packages are built, the package interconnects performances and reliability will be mainly governed by soldering mechanics. Table 4. Electrical Test Results After Drop Test Flow ID T=0 Post Drop Delta A A A A n-tob A A A A A Ave Sted B B B B B B B B B Ave Sted Conclusions After assessments, it can be concluded that: - The 2.5D TSV packages built by using newly developed assembly approach, n-tob, have at least the same or better assembly yield and reliability performances as those fabricated by using - Even though the 2.5D TSV package under study is robust in mechanical integrity, there is a room for improvement, mainly in package interconnect designs (structure and surface metal scheme). - The 2.5D TSV package s performances and reliability are mainly dominated by the interconnect soldering mechanics. The influence of choosing which assembly process approach is relatively small. Acknowledgments Authors would like to thank Yanchun Zheng, Fengjin Wang, and Wei Wang for TSV package assembly support. Daquan Yu also acknowledges the support of National Natural Science Foundation of China ( ). References 1. Knickerbocker, J.U. et al, Development of Next- Generation System-on-Package (SOP) Technology Based on Silicon Carriers with Fine Pitch Interconnection, IBM J. Res. & Dev., Vol. 49, No.4/5 (2005), pp Andry, P.S. et al Low-Profile 3D Silicon-on-Silicon Multi-Chip Assembly, Proc. 61 st Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2011, pp Andry, P.S. et al, Fabrication and Characterization of 1968

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