EE 432 CyMOS process PWELL Photolithography and Diffusion Feb. 23th 2017

Transcription

1 1 EE 432 CyMOS process PWELL Photolithography and Diffusion Feb. 23th 2017 Group III Jake Asmus (Leader) John Guss Shengliang Liu Xin Chen Lab instructor Matt Weinstein

2 2 Overview With the field oxide grown on the wafer, it s now time to fabricate the PWELL. The reason why we need to process a xwell is so we can get the two types of transistors for our CMOS s: NMOS and PMOS. The PMOS needs an n-tpye bulk and the NMOS needs an p-type bulk; In our case, they are doped with phosphorus, therefore n-type. With n-type wafers, we have the n-type bulk but lack the p- type bulk and that s where the PWELL process comes in. The PWELL s will act like our p-type bulk for our NMOS s throughout our wafers. For the PWELL process, we will mask our wafers through the photolithography process (see Figure 1a), apply the dosage for the deposition (see Figure 1b), and then the drive to spread the dopant through the substrate (see Figure 1c). Figures 1a 1c have the cross sectional view from the process traveler of the CMOS s after each major step: photolithograph, deposition, and Drive. Figure 1a: Cross section view after photolithograph and etching Figure 1b: Cross section view after Boron deposition Figure 1c: Cross section view after Boron drive Boron Photolithography Photolithography is the process where we pattern our device wafers so we can diffusion dopants into the selective areas masked. Since this was our first time as group applying the photolithography, each one of us applied the process to our own wafers and selected two members to apply the process to our spare wafers. Before starting, we all read the Stand Operation Procedures for photolithography to give ourselves a heads up and reviewed the mask and die layout (Figure 2a for mask and Figure 2b for die layout). The mask layout has 37 dies that contains the following devices: Device Number of Devices 3-terminal PMOS 9 4-terminal PMOS 3 3-terminal NMOS 9

3 3 4-termianl NMOS 3 NPN BJT 3 Transfer Length Method (TLM) pattern 4 Van der Pauw (VDP) pattern 3 NMOS Capacitor 1 PMOS Capacitor 1 NAND 1 NOR 1 NOT (Inverter) 1 Table 1: Device count per die That s a total of 39 devices per die and a grand total of 1443 devices per wafer once the fabrication process is complete. We are using is a six-masked process starting with mask one developing the PWELL s for our NMOS s (see Figure 4 for mask one). The first mask will be the easiest due to no alignment, but every photolithography will have alignment marks that are colored coded (see Figure 4) so we can correctly mask the next photolithography. After reviewing the process and masks, we proceeded to the photolithography room to begin the first photolithography. Figure 3: Mask Color Code Since the Karl Suss Aligner takes some time to start up, we first started the aligner and check mask one if it s clean to use. Figure 4 has the mask we used for the PWELL for our NMOS s. Figure 4: PWELL Mask While the aligner is powering up, Xin Chen set upped the spinner and cleaned it if needed. We start the spinner and set the speed to 3815 rpm for a duration of 25 seconds. John Guss was the first to center his wafer on to the spinning chunk and press down on the pedal to check if the spin run is stable (i.e. no whopping). If satisfied with the test run, we then apply four droplets of hexamethyldisilazane (HMDS) near the center of the wafer to promote adhesion for the photoresist and spun the wafer for 25

4 4 seconds. Once we finished applying hexamethyldisilazane to the device wafers, the device wafers are now primed and ready for the application of the AZ-5214E-IR photoresist (positive photoresist). There are two types of photoresist: positive or negative. The positive photoresist exposed region will become soluble when developed; Negative photoresist is the exact opposite, making the exposed region insoluble when developed. Once we all spun the uniformly layer of one half squeezer of photoresist, we place the device wafers into the oven for a pre-bake at 120 ⁰ C for 25 minutes. While this is taking place, Shengliang Liu cleaned up the spinner. Once the pre-bake is complete, we can begin exposing the device wafers with the Karl Suss. John started us off, setting up his wafer on the platform and centered the wafer with mask one. Once satisfied with his wafer orientation, he then initiated the exposer with ultraviolet light for 90 seconds. Once the time is reached, he replaced his wafer onto the carrier moved onto the development process while letting the next person in line to repeat the exposer steps for their own wafer. While the next Jake was using the Karl suss, John at the wet bench filled a deep glass dish with 1 cm thick of MIF-300 developer. He placed his wafer into the developer for 75 seconds. Once John was finished with the developer, he cascade rinsed, dried his wafer with gaseous nitrogen, and then inspected his wafer with a microscope. Once inspected and satisfied with the exposer and development on the wafer, John placed his wafer onto the carrier ready for post-bake. Everyone else followed these steps with their own wafer, Shengliang Liu developed, inspected spare wafer 1 and Xin Chen developed, inspected spare wafer 2. With the exposure, development, and inspection is complete, we now placed our device wafers onto a carrier and placed them in the oven for post-bake at starting at 107⁰C and ramping up to 128⁰C for a time of 25 minutes. While the post-bake is proceeding, we shut down the Karl Suss Aligner. Once the post bake is complete, we are ready to etch the SiO 2 and strip the photoresist. First we etch the SiO 2 by placing our device and test wafer 1 into the Buffer Oxide Etch (BOE) for 3mins and 40 seconds and added additional 30 seconds for complete removal of SiO 2. Next, we cascade rinse for 2 minutes before the photoresist stripping. Once the 3 minutes are up we all the following procedure for stripping the photoresist: 1. Place the carrier in the acetone #1 tub for 3 minutes. 2. Place the carrier in acetone #2 for 1 minutes. 3. Place the carrier in the methanol tub for 1 minute. 4. Rinse in the cascade rinse tub for 2 minutes. While the wafers are in the cascade rinse, we initiate the rinse sequence for the spin dryer. Once the cascade rinse is finished, we initial the full spin dry sequence (approximately 5 minutes). The photolithography is now complete for the PWELL s and device wafers look like Figure 1c. The next step for the PWELL process is the deposition. Boron Deposition The PWELL deposition is the first step of two for the diffusion process. Deposition is where we dose the wafers with impurities on to the silicon wafer surface. The Drive is the late step that will be performed by none other: Dr. Tuttle. To start this process, Xin Chen applies the standard cleaning procedure since a high temperature deposition will take place and Shengliang Liu preps the furnace for the Boron Diffusion.

5 5 The standard cleaning procedure is used to eliminate any impurities that have contaminated our wafers. During the cleaning, dangerous chemicals will be used and full protected gear is required to proceed. Next, we need to add 2500 ml deionized water and 500 ml ammonium hydroxide (NH 4 OH) into cleaning tub(sc-1) container and 3000 ml of deionized water and 500 ml of hydrochloric acid (HCI) into cleaning tub (SC-2) container. The tubs are then heated to 75⁰C. Once SC-1 reached 75⁰C, hydrogen peroxide (H 2 O 2 ) is poured into the tub. Once the temperature arises to 75⁰C again, the wafers are submerged for 15 minutes. The goal is removing all organic contaminants on the wafer. Once the 15 minutes are up, the wafers are transfer to the cascade rinse for 3 minutes and pour 500 hydrogen peroxide (H 2 O 2 ) into SC-2 tube. The wafers are then submerged into the diluted hydrofluoric acid (HF) for 15 seconds and then transferred into the cascade rinse again for at least one minute. The goal for the HF is to etch the SiO 2 to remove oxide contaminates. Once the SC-2 tub reaches 75⁰C again, the wafers are submerged into the tub for 15 minutes. The goal is to remove all metallic contaminants on the wafer. Once the time s up, it then cascade rinsed again for 3 minutes and then spun dried for 5 minutes. The objective of this diffusion is to have a relative small total dose to have a small surface concentration. For our PWELL s, we want a dose between 7.5E-13 cm -2 and 10E14 cm -2 and we need to find a Dt such that this achieve. This is where Jake Asmus and John Guss applied mathematics taught in lecture come into play. First step is to find a temperature where we want to perform the deposition. We decided to take the same temperature as the Low-Temperature Oxidation, 850⁰C. From there, we can use expression (1) to find D. DD = DD 0 ee^( EE AAAAAAAAAAAAAAAAAAAA ) (1) kk TT D 0 is 1 cm 2 /s, T is our chosen temperature 850⁰C ( K), E Activation = 3.5eV, and k is Boltzmann s constant 8.617E-5 ev/k. With these parameters, we obtain D to have a value of 3.652E-17 cm 2 /s. Next, we need to find the Dt using expression (2). QQ = 2 NN SS DDDD ππ (2) We wanted a dosage between the two boundaries, Q = 9.0E13 cm -2 and N S is the solubility limit of boron. To find N S, we took the N S at 800⁰C and 900⁰C (7E19 cm -3 and 1.2E20 cm -3 respectively) and assume it s a linear approximation (with this assumption, N S = 9.5E19 cm -3 ). With the parameters set, Dt = 7.049E-13 cm 2 /s. From here, we can use expression (3) to find the diffusion time at this temperature with this dosage. DD tt = 7.049E( 13) cm2/s (3) We know D at the temperature 850⁰C and solve for the time which we obtained to be 5.36 hours. However, if we put these values in to the diffusion_spreadsheet.xls file on Dr. Tuttle s website, we get the time to be hours for the chosen temperature and dosage. We talked to our TA, Matt, and he said that pervious groups have been using the same temperature for their deposition. So we went with what the excel sheet said and proceeded with the process. I m still confused why my calculations are not agreeing with the excel spreadsheet; However, I do see that the spreadsheet is using different units, but this should change anything. Looking at the cell B17, the units for N S are cm -3 and the Dt product is

6 6 in µm -2 and there s a constant that s divided to, I assume, change the N S units to µm of 10,000. With our confidence with Matt and the excel file, we proceeded to the deposition once the standard cleaning procedure was complete. With the wafers cleaned, Shengliang Liu loaded the source wafers and device wafers onto the boat and pushed the device wafers and test wafer 2 into the furnace at 850⁰C at a rate of 1 inch every 12 seconds so the wafers can adopt to the heat. The source wafers are BN-975 grade composed of boron nitride and boric oxide. At high temperatures, the boric nitride removes all the B to grow diffusion bonds. Once activated, B 2 O 3 glass forms on the outside of source wafer and it s controllably transferred to the silicon wafers to produre a uniform boron doping. Once the wafers are in the center of the furnace, Matt set upped the recovery, source and soak parameters and soaked for 55 minutes and Jake Asmus started to pull at the 56-minute mark since it takes up to 6 minutes to pull. Once the wafers are cooled and unloaded from the boat, we then deglaze the wafers. This is to etch the oxide that grew on the wafers during the diffusion phase then followed by the cascade rinse and spin dry. Looking at the data sheets, at our temperature and diffusion time, our sheet resistance is around 190 Ω/square. The deposition is now complete and ready for the drive performed by Dr. Tuttle. Boron Drive The boron drive was performed by Dr. Tuttle for a duration of 16 hours. According to Dr. Tuttle, the standard cleaning was performed, applied a LTO for 30 minutes at 800⁰C, deglazed for 30 seconds and then rinsed, grew oxide at 1135⁰C for 13.5 minutes, and then drive at 1135⁰C for 15 hours and 46.5 minutes. Total boron drive is 16 hours. Once the drive was complete, the thickness of the oxide was not what expected, 0.31 µm, and approximately obtained 0.81 µm. The cause of this was due to an oxide source in the tub at the fa end of the furnace. While the drive was proceeding, there was a source of oxygen which unfortunately increased the oxidation time which furthermore increased the thickness. However, this should not be an issue except that it will take more time to etch the oxide. In the end, the objective was to diffuse the boron dopant deeper into the silicon wafer. Results Figures 5-10 have the photolithography results after the developer.

7 Figure 5: John Guss s Wafer Inspection 7

8 Figure 6: Jake Asmus s Wafer Inspection 8

9 Figure 7: Shengliang Liu Wafer Inspection 9

10 Figure 8: Xin Chen s Wafer Inspection 10

11 Figure 9: Spare 1 s Wafer Inspection 11

12 12 Figure 10: Spare 2 s Wafer Inspection The wafers look great and you can see the exposed silicon where the PWELL s will be diffused with boron dopant.

13 13 2-step diffusion 1.0E+18 doping (cm^-3) 1.0E E E+15 profile background 1.0E depth (µm) Figure 11: Boron Profile after the two-step diffusion After the two step boron diffusion, Figure 11 has the predicted boron profile result. Looking at the plot, our junction depth of the PWELL is µm deep with surface concentration 4.047E17 cm -3. This is where the sources and drains of the NMOS s will be diffused into the PWELL at a depth less than µm and more heavily doped. Issues that came about was figuring out the time for the boron deposition. Our calculations and calculations from the excel spreadsheet are very different and still don t know why. More than likely the issue is due to our hand calculations, but needs to be resolved before the next diffusion. Overall, we have now gone through a whole single layer of the fabrication process and we are satisfied with the PWELL process and look forward the text layers.

14 14 Appendix Process Traveler

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