Integration of Power-Supply Capacitors with Ultrahigh Density on Silicon Using Particulate Electrodes POWERSOC 2012

Size: px
Start display at page:

Download "Integration of Power-Supply Capacitors with Ultrahigh Density on Silicon Using Particulate Electrodes POWERSOC 2012"

Transcription

1 Integration of Power-Supply Capacitors with Ultrahigh Density on Silicon Using Particulate Electrodes POWERSOC 2012 P M Raj, Himani Sharma, Kanika Sethi, Prof. Rao Tummala 3D Systems Packaging Research Center Georgia Institute of Technology, Atlanta, GA

2 Outline Component integration using 3D IPAC Concept 3D IPAC goals Applications o VRM and decoupling Thinfilm decoupling capacitors o Power convertor High-density capacitors Slide 1

3 Passives Trend Discretes Array of Discretes Silicon and Glass IPDs 3D IPAC 500 microns (0402) Thick Devices microns 500 microns (0402) microns Thick Devices microns microns 40 microns microns Courtesy: Kemet, Fraunhofer IZM Slide 2

4 What is 3D IPAC Concept and Why? 10 µm Active IC Active IC 40 µm 30 µm Passives Passives 1. Ultra-thin Glass Core ~ 30 µm 2. Low Loss 3. Fine-pitch and coarse-pitch through-package vias 4. Passive components on both sides of glass. RF capacitors, inductors Power supply capacitors and inductors Decoupling Capacitors Precision components 5. Active components for power, digital, RF and Analog 6. Interconnections Slide 3 3D IPAC is a functional module

5 3D IPAC on Interposer 10 µm Active IC Active IC 40 µm 30 µm Passives Passives 3D IC IC 3D IPAC 30 µm 10 µm Si/Glass Core 3D IPAC IC Thin 3D IPAC Capacitor Slide 4

6 3D IPAC in the 3D POP 10 µm Active IC Active IC 40 µm 30 µm Passives Passives Slide 5

7 3D IPAC on PWB 10 µm Active IC Active IC 40 µm 30 µm Passives PWB Slide 6

8 Goals of 3D IPAC Miniaturization: 5X reduction in thickness Cost: 2 5X reduction in cost Performance: Higher bandwidth at lower power compared to today s systems Functionality: Double-side component integration for heterogeneous functions in an ultrathin module Slide 7

9 3D IPAC Applications RF MODULE PDN Module Power Convertor Module Precision Resistors By-pass capacitors High-density Output Capacitors High-density Capacitors 80 µm RF IC Glass POWER IC Glass Active MOSFET Switches Glass 10 µm RF Inductors Precision RF Capacitors High Frequency Decoupling High-density Inductors RF ICs High Q and Precision Components: Capacitors Resistors Inductors Voltage regulator module VRM output capacitors Decoupling capacitors Power switches High-density capacitor High-density inductor Slide 8

10 3D IPAC PDN Module Improved power integrity for 3D ICs and packages with thinner packages POWER IC Glass VRM and decoupling functions in the interposer, close to the package Reduces the number of decoupling capacitors High Frequency Decoupling Logic IC Case 3 Thin power ICs (ex. MOSFET switches) 30 µm Glass core 3D IPAC VRM High-density inductors High-density capacitors FR4 POWER GROUND Slide 9

11 Sputtered BST Thinfilm Capacitors Thinfilms ( nm): Thinner films (Barium Strontium Titanate); Faster crystallization; Higher capacitance density of 14 nf/mm 2 Key Result BST on Si/SiN/Ta/Ni BST sputtering Ar/O 2 (60% O 2 ); 100 W; 2.5 hrs Annealing conditions 750 C, 30 min in N2 Capacitance density 9 11 nf/mm2 Higher yield with large area electrodes 220 nf achieved on 0.28 cm2 Leakage current of the order µa/cm 2 achieved up to 3 V (4 nf/mm 2 ) Yield Slide 10 85% (30/35 devices yielded)

12 Solgel PZT Thinfilm Capacitors 1.0E µf/cm2 (1 V) 1 µf/cm2 (10 V) Leakage Current (A/cm 2 ) 1.0E E E E E E E- 7 PZT/LNO/Si PZT/LNO/ZrO2/Si PZT/LNO/Pt/Ta/Si 1.0E Volts (V) 1.2 x 2.5mm 2 : nf, loss nf, 2.9 x 2.5mm 2 : loss Yield 51% (56/110) yield 14% (8/57) Slide 11

13 3D IPAC-Based PDN Three decoupling capacitor integration scenarios were modeled SMD on board shows highest parasitics and lowest performance; Requires excessive onchip decoupling ThinFilm integration in today s packages can achieve higher frequency stability, but has limited manufacturability IPAC micro-assembled close to IC shows best performance because of thin interposer and short bump parasitics; Impedance)) (Ω)) 1000$ 100$ 10$ 1$ 0.1$ SMD 0.01$ 0.00E+00$ 5.00E+08$ 1.00E+09$ 1.50E+09$ 2.00E+09$ Frequency)(Hz)) Integrated 5X improvement in frequency performance with the proposed 3D IPAC strategy Thin IPAC capacitor Slide 12

14 3D IPAC Power Converter Module Power Module: Switching regulator or charge-pump based Thin power ICs High-density inductors High-density capacitors High-density Capacitors Active MOSFET Switches Glass High-density Inductors Slide 13

15 High-Density Capacitors Slide 14

16 2.2 MLCC 100 µf/cm 2 Planar capacitance µf/cm µf/cm 2 10 µf/cm 2 40 µf/cm 2 PRC Focus Tantalum Area enhancement for 100 µm film Slide 15

17 Process flow for High-Density Capacitors Top Electrode Dielectric Bo7om Electrode Rou3ng Layer Adhesion layer Silicon Carrier Slide 16

18 Porous Electrode with Highest Surface Area Efficiency Silicon Trench vs. Copper Par3culate Electrode Silicon Compatible 100 X enhancement in area Expensive silicon micromachining tools Silicon Compatible Potential for >2000 X enhancement in surface area from BET measurements ( 100 µm) Low-cost paste processing Slide 17

19 Area Enhancement: Nanoelectrodes Vs Trenches PARTICLE SIZE (NANOELECTRODE) AREA ENHANCEMENT (TRENCH) !! AREA ENHANCEMENT (NANOELECTRODE) ASPECT RATIO (TENCH) Slide 18

20 PRC s Background High-Density Capacitor Research High surface area electrodes on silicon trench; US 8,084,841 B2 High surface area electrodes on organic substrate with etched foil Adhe sion layer Adhe sion layer High surface area electrodes on organic substrate with sintered particles US 8,174,017 Slide 19

21 Nanoelectrodes on Si Sintered particles Bottom Cu Silicon Step 1: Copper powder Dispersant (Phosphate ester) Binder: Propylene carbonate Step 2: Printing on Silicon Step 3 Sintering 400 o C 600 o C Copper particle size : 1-2 µm High surface area enhancement due to open pores 30-40X surface area enhancement for 25 µm film Slide 20

22 Porous electrode with Sacrificial Polymers Using a sacrificial polymer (polypropylene carbonate) that would decompose easily at sintering temperatures in reducing atmosphere Vola3le by- product Polypropylene carbonate Polymer granules Porosity in place of polymer HEAT Copper particles Slide 21

23 ALD Conformality Studies Increase diffusion time of the ALD vapor For aspect ratio of torr: 100 seconds 0.2 torr: 500 seconds Larger than ALD pumpdown time; ALD time can start becoming larger; Torr X seconds For aspect ratio of 10: Micro to milli seconds; Very small fraction of ALD pumpdown time; no affect on ALD process time; Aspect Ratio Based on modeling by: Gordon, Haussman and Kim (Harvard); Shephard (IBM) 1000 Slide 22

24 Conformality Studies using EDS EDS Scan at the bo7om of 200 um thick electrode Al O Atomic Weight % Electrode Thickness (depth) (µm) ALD conformality as a function of electrode depth Slide 23

25 Conformal Dielectric on Porous Electrodes 700 cycles of ALD alumina (~ 100 nm) FESEM showed 105 nm thick Alumina film on copper particle necks 105 nm Cross-section of sintered bottom electrode showing ALD alumina layer Slide 24

26 Conformal Top Electrode Key Challenge: To access the high surface area by using a conformal top electrode Approach : Use of a liquid conducting polymer polyethylene dioxythiophene (PEDT) Polymerization: EDT+ oxidizer+ inhibitor 1:25 (in-situ) Conductivity ~ 100 S/cm Fluid nature with low viscosity for easy infiltration of particulate electrode Low temperature processability ( 50 o C) Self-healing characteristics Slide 25

27 Demonstration of Nanoelectrode Capacitors Device Thickness Area Capacitance Enhancement Density Planar (0.6mm x 0.6mm) µF/cm 2 <5 µm 10X 1.1 µf/cm 2 10 µm 25 X 3.9 µf/cm 2 25 µm X 30 µf/cm 2 >75 µm X µf/cm 2 Slide 26

28 Nanoelectrode Capacitors : Leakage Current I- V plot of planar and par9culate electrode capacitor 1.00E E E- 02 Par3culate Capacitor with PEDT Particulate electrodes using PEDT show very high leakage as compared to planar capacitors. Leakage Current (A/uF) 1.00E E E E- 06 Planar Capacitor with PEDT Two possible reasons identified: (I) PEDT/ Al 2 O 3 interaction 1.00E E- 08 Planar Capacitor with Au (II) Inherent Defects in Al 2 O 3 film 1.00E Voltage (V) Slide 27

29 GT PRC: HDCAP Vs State-of-the-Art PRC s Si and Glass IPD Capacitance Volumetric Density µf/cm Thin Film Capacitors 100 1,000 Si Trench Conformal dielectric on a nanoporous electrode 10,000 Permittivity X Electrode Area Enhancement 28 Slide 28

30 Conclusions 3D IPAC shown as a compelling new technology for active and passive component integration in ultrathin functional modules Better miniaturization Lower cost Higher performance Novel silicon or glass-compatible high-density capacitor technologies investigated to meet 3D IPAC goals Slide 29