Fabrication of annular photonic crystals by atomic layer deposition and sacrificial etching

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1 Fabrication of annular photonic crystals by atomic layer deposition and sacrificial etching Junbo Feng School of Optoelectronics Science and Engineering, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan , China Yao Chen Wuhan National Laboratory for Optoelectronics, Wuhan , China and Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, Hubei , China John Blair School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia Hamza Kurt Department of Electrical and Electronics Engineering, TOBB University of Economics and Technology, Ankara 06560, Turkey Ran Hao Wuhan National Laboratory for Optoelectronics, Wuhan , China D. S. Citrin School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia and Unité Mixte Internationale, 2958 Georgia Tech-CNRS, Georgia Tech Lorraine, 2, rue Marconi, Metz, France Christopher J. Summers School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia Zhiping Zhou Wuhan National Laboratory for Optoelectronics, Wuhan , China; School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia ; and State Key Laboratory on Advanced Optical Communication Systems and Networks, Peking University, Beijing, , China Received 29 October 2008; accepted 12 January 2009; published 6 March 2009 In this article, the fabrication process of annular photonic crystals on silicon-on-insulator wafers was addressed for the first time. A self-alignment procedure for nanofabrication using atomic layer deposition and sacrificial etching was established to place accurately nanosized dielectric rods in nanosized circular air holes. Avoiding the challenging electron-beam lithography alignment, this method achieves atomic level precision and shows high stability American Vacuum Society. DOI: / I. INTRODUCTION Photonic crystals PCs are a class of artificial optical materials with periodic dielectric structures, which result in unique optical properties, and show promise to be a key platform for future optical integrated circuits. The ideal PC structure is three dimensional 3D, since light propagation can only be controlled fully with 3D photonic crystals. However, the fabrication of 3D PCs and integrated waveguide channels is very challenging. One of the problems arising due to reducing the dimension to two-dimensional 2D is that the optical properties of the PCs become strongly polarization sensitive. In many cases, we want to implement polarization insensitive devices such that the PC provides a full band gap for all polarizations. To address this problem, we have proposed a novel type of 2D PC called annular PC APC. 1,2 A schematic drawing of the APC is shown in Fig. 1. The APC is composed of dielectric rods and circular air holes in a triangular lattice such that each rod is centered within each hole. Our theoretical results show that rods with different materials provide superior optical performance. Thus, it cannot be simply fabricated by a one step electron-beam lithograph EBL and etching protocol to form ring-shaped holes. 3,4 The most difficult step in fabrication is to place and center accurately each dielectric rod in each hole. Since the air gap is generally less than 50 nm, very precise alignment is required for patterning the dielectric rods. Another scheme is to completely fill dielectric materials in PCs and use precise EBL alignment to form the ring-shaped air gap. However, although it is well known that EBL is the most accurate lithography method at the nanoscale it is very difficult to achieve such high precision across relatively large areas. 568 J. Vac. Sci. Technol. B 27 2, Mar/Apr /2009/27 2 /568/5/$ American Vacuum Society 568

2 569 Feng et al.: Fabrication of annular photonic crystals 569 FIG. 1. Color online Schematic of the annular photonic crystal. The slab thickness is 290 nm. The lattice period of PC is 450 nm. The diameters of PC holes and AlN dielectric rods are 250 and 170 nm, respectively. Additionally, the alignment precision of EBL still depends on the making of alignment marks and system operation. Therefore, an extra precise and stable aligning method is required for the fabrication of APC. In this article, we presented a novel self-alignment procedure for nanoscale fabrication to implement the APC structure. The dielectric rods are placed and centered within each photonic crystal hole by a two-step atomic layer deposition ALD process followed by removal of the first sacrificial layer. 5 Since the alignment precision is now determined by the deposition method, it can be controlled to within 1 2 Å, which is the thickness of one atomic layer of ALD. II. EXPERIMENTAL DETAILS The main process flow sequence is shown schematically in Fig. 2, and consists of EBL, ALD of Al 2 O 3 and AlN, inductively coupled plasma ICP etching of Si and AlN, and buffered oxide etching BOE of Al 2 O 3. Because of the very strong sensitivity of the polarization properties, and band gap alignment for each polarization on the waveguide layer thickness, our process begins with Si slab thickness preparation. The designed Si thickness for APC slab is 290 nm for a wavelength of 1550 nm. However, the availability of wafer thicknesses is limited. For example, the typical vertical layer structure of our SOI wafers is 340 nm of Si on top of a 1 m thick SiO 2 spacer layer grown on a Si substrate from Soitec. To reduce the upper Si layer thickness from 340 to 290 nm, thermal oxidation was used to thin the Si waveguide layer since it consumes Si and the process is highly predictable. 6 The silicon-on-insulator SOI wafer was placed in a furnace for 3hat1000 C by dry oxidation. Then it was immersed in BOE for about 1 min to remove the upper oxide. After confirming the Si waveguide thickness with a Woollam Ellipsometer or Nanospec measurements, we coated e-beam resist ZEP-520A on the top of SOI. ZEP is a widely used positive e-beam resist, which has been demonstrated to have a higher exposure sensitivity than polymethyl methacrylate and an improvement in dry etch resistance. 7 A 300 nm thick layer of ZEP-520A resist was coated on the SOI wafer, baked on a hotplate at 180 C for 2 min, and then exposed with current of 2 na at 100 kv using JBX-9300FS EBL system. Because of the proximity effect in EBL, the optimal dose for any particular pattern is a function of many variables, including the pattern size, the pattern density, the resist thickness, the accelerating voltage, and the substrate atomic mass unit. 8 It is difficult to model all of these variables at the same time because the effect of each parameter is difficult to control. In order to explore the appropriate dose for our structure, we used a series of dose which ranges from 200 to 400 C/cm 2 with interval of 10 C/cm 2. From this study we determined that a dose of 260 C/cm 2 was optimum for patterning a PC with a period of 450 nm and hole diameter of 250 nm. Finally, the wafer was developed in amyl acetate for 2 min and rinsed in isopropyl alcohol for 1 min. Then we used ICP etching to transfer the PC pattern to Si, which was performed using a Plasma-Therm ICP system. The etched samples were located on a He back side cooled chuck biased with MHz of power. The effects of the key process parameters such as the etching gas component, the gas flow, the etching pressure, the source power, and the bias power were studied in details. A Cl 2 and C 4 F 8 based chemistry was used for Si against ZEP-520A etching. The etching pressure was kept at 5 mtorr. The source power and the bias power were 800 and 5 W, respectively. This etching recipe produced an etch rate of 120 nm/min for Si and exhibited a high selectivity of 3:1 for Si compared to ZEP. Following pattern transfer, the wafer was rinsed in Microposit Remover 1165 solvent for several minutes or exposed to an O 2 plasma for about 1 min to remove the resist. After that, a conformal layer of Al 2 O 3 sacrificial layer with the thickness of 40 nm was deposited over the whole surface by ALD. Right following the sacrificial layer deposition, an AlN layer with the thickness of 150 nm was FIG. 2. Color online Fabrication processes of APC on SOI. a Si thickness reduction in SOI wafer. b EBL exposure and development of photonic crystals. c ICP etching of photonic crystals. d Stripping of e-beam resist. e ALD of sacrificial layer Al 2 O 3. f ALD of rod material AlN. g Removal of additional top AlN layer. h Removal of sacrificial layer Al 2 O 3. JVST B-Microelectronics and Nanometer Structures

3 570 Feng et al.: Fabrication of annular photonic crystals 570 FIG. 4. Color online ALD film thickness as a function of reaction cycles for Al 2 O 3 and AlN. realized by wet etching in buffered HF solution. Since the wet etching is an isotropic method, an overetching will cause undercutting below AlN rods, or even release of AlN rods if not well controlled. The control of wet etching will be discussed in detail below. FIG. 3. Cross-sectional SEM images of conformal film depositions of Al 2 O 3 and AlN by ALD a one hole with 40 nm Al 2 O 3 deposition and 90 nm AlN deposition b whole structure after holes were completely filled by the deposition of 40 nm Al 2 O 3 and 150 nm AlN. deposited on the top by another ALD system. ALD is a precisely controlled method for thin films deposition. The principle of ALD is based on sequential pulsing of chemical precursor vapors, both of which form about one atomic layer each pulse. This generates pinhole-free coatings that are extremely uniform in thickness, even deep inside pores, trenches, and cavities. There are also many other attractive properties of ALD for nanofabrications, such as low deposition temperature typically lower than 400 C, almost no selectivity to substrate materials, excellent adhesion, low deposition stress, relatively insensitive to dust, and so on. The disadvantage of ALD is the low deposition rate compared to chemical vapor deposition and sputtering. The Al 2 O 3 layer deposition thickness should be equal to the width of the air gap. Moreover the AlN deposition thickness should be larger than the radius of the dielectric rod in order to completely fill the holes. The scanning electron microscope SEM photographs of the structure after Al 2 O 3 and AlN deposition are shown in the following figures as Fig. 3. A uniform and conformal film deposition was realized. After filling the PC holes sequentially by Al 2 O 3 and AlN, the top additional AlN layer was removed by ICP or reactive ion etching RIE. Finally, the APC structure was accomplished by removing of the sacrificial Al 2 O 3 layer, which was III. RESULTS AND DISCUSSION A. ALD of Al 2 O 3 and AlN ALD was chosen for the conformal deposition of Al 2 O 3 and AlN. We have two ALD systems. One is used for Al 2 O 3 deposition, and the other is for AlN deposition. 9,10 Al 2 O 3 was grown by alternately induced trimethylaluminum TMA and H 2 O into the reaction chamber which was heated at 150 C under a pressure of 500 mtorr. While AlN was grown by TMA and NH 3 pulses at 350 C under 600 mtorr. The growth rate of Al 2 O 3 is 1.8 Å per cycle, and that of AlN is 2.1 Å per cycle. To study the relationship between growth rate and substrate material, we deposited the AlN layer on different substrates, such as Si, SiO 2, and Al 2 O 3. The results showed that ALD deposition rates were almost the same. Figure 4 shows the growing thickness of Al 2 O 3 and AlN layer as a function of reaction cycles. The chemical compositions of Al 2 O 3 and AlN films by ALD were analyzed by energy dispersive x-ray spectroscopy EDS, which are shown in Figs. 5 a and 5 b, respectively. Since the films were deposited only about 60 nm on Si substrate, some of the electrons will permeate the film and hit the Si substrate. That is why a high Si component was observed in the EDS results for both Al 2 O 3 and AlN films. The results also show some extra O component for Al 2 O 3 and AlN films, which may come from the native oxide on Si surface, impurity in nitrogen, or H 2 O vapor in ALD chamber, etc. To precisely analyze the impurity level of the films, x-ray photoelectron spectroscopy can be implemented. The root-mean-square rms roughness of the films was measured by atomic force microscopy AFM. Figures 5 c and 5 d show the oblique J. Vac. Sci. Technol. B, Vol. 27, No. 2, Mar/Apr 2009

4 571 Feng et al.: Fabrication of annular photonic crystals 571 FIG. 5. Color online a EDS result of 60 nm ALD Al 2 O 3 filmonsi substrate. b EDS result of 60 nm ALD AlN film on Si substrate. c Oblique view AFM image of ALD Al 2 O 3 film on Si substrate. d Oblique view AFM image of ALD AlN film on Si substrate. view AFM image of Al 2 O 3 and AlN films on Si substrate, respectively. The rms roughness is 0.19 nm for Al 2 O 3 film and 0.69 nm for AlN film. B. Removing of AlN and Al 2 O 3 Several methods were investigated to remove the top additional AlN and Al 2 O 3 layers: focused ion beam FIB milling, surface polishing, and wet and dry etching. Finally we chose ICP to remove the additional AlN layer since dry etching is easier and faster than FIB and surface polishing. The ICP etch rate of AlN was 15 nm/min using a Cl 2 based gas and the Al 2 O 3 layer acted as the stop layer of AlN etching. The Al 2 O 3 layer can be removed with Cl 2 and BCl 3 chemistry using RIE or ICP. However, the selectivity of Al 2 O 3 to Si in dry etching is very poor, Si layer will be etched synchronously while removing the Al 2 O 3 in the gap. Also, the surface roughness caused by the plasma bombardment of dry etching will be a great source of device losses. We found that BOE can etch Al 2 O 3 and has very high selectivity to Si and AlN. The etch rate of Al 2 O 3 using BOE HF:H 2 O=1:6 is 100 nm/min, and the etch rate of AlN using BOE HF:H 2 O=1:6 is only 1.5 nm/min. Thus, we use BOE to remove Al 2 O 3 on the surface and in the gap. However wet etching is an isotropic etching method, Al 2 O 3 and SiO 2 will be under etched if the process is not well controlled, which will cause the dielectric AlN rods to release and drop off. We found BOE HF:H 2 O=1:6 is too violent for Al 2 O 3 etching and is very hard to control. Figure 6 a shows the APC using BOE HF:H 2 O=1:6 for Al 2 O 3 etching. The undercut effect causes some of the dielectric AlN rods to release and drop off. Diluted BOE has slower etching rate to Al 2 O 3 and the etching is much uniform and easier to control. The etch rate of Al 2 O 3 is 10 nm/min using diluted BOE HF:H 2 O =1:50. After removing the Al 2 O 3 on the surface, diluted BOE was used for removing Al 2 O 3 in the gap. The final APC structure after a well controlled etching with combination of diluted BOE and normal BOE is shown in Fig. 6 b. FIG. 6. a Wafer was put in BOE HF:H 2 O=1:6 for 3 min to remove the Al 2 O 3 layer. The undercut effect causes some of the dielectric AlN rods to release and drop off. b Final APC structure accomplished by a combination of diluted BOE and normal BOE, which optimizes the undercut effect of wet etching. The wafer was put in BOE HF:H 2 O=1:6 for 2 min and then in diluted BOE HF:H 2 O=1:50 for 8 min. IV. CONCLUSIONS In conclusion, we have proposed and demonstrated for the first time the fabrication protocols required to form an annular photonic crystal structure. A novel self-alignment method based on the sacrificial layer ALD and etching technique was established to achieve alignment precision down to the atomic level. It provides a new method for precisely aligning nanostructures and is expected to have general application. Each step of the fabrication process was optimized based on the APC structure. A high selectivity and good etched feature of Si against ZEP-520A etching was obtained by ICP. Very smooth and conformal depositions of Al 2 O 3 and AlN were realized by ALD. A combination of diluted BOE and normal BOE optimizes the undercut effect of wet etching. Such processes are also appropriate to fabricate various other nanostructures. ACKNOWLEDGMENTS This work is partially supported by the National Basic Research Program of China No. 2006CB DSC would like to thank the CNRS for its support. JVST B-Microelectronics and Nanometer Structures

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