Cross-bar architectures

Transcription

1 Cross-bar architectures Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy ielmini@elet.polimi.it Flash scaling overview 1. Flash scaling: 2. Evolutionary scenario: T. Kamaigaichi, et al., IEDM Tech. Dig H. Tanaka et al., VLSI Symp Paradigm shift M. Lee, et al., IEDM Tech. Dig Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 2 1

2 Crossbar architectures Introduction SiO 2 -based 3D-OTP (Matrix, 2004) NiO RRAM crossbar (Samsung, 2005) NiO RRAM BEOL crossbar (Samsung, 2007) Perovskite-based RRAM crossbar (Unity, 2008) PCM crossbar (Hitachi, 2009) PCMS crossbar (Intel-Numonyx, 2009) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 3 Crossbar Mutually crossing perpendicular wordlines and bitlines Memory element at each WL/BL crossing Highest cell density 4F 2 + 3D stacking = 4F 2 /n density Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 4 2

3 Why rectifier? Diode rectifier needed to avoid read current sneakthrough Diode must: 1. Isolate unselected cells low leakage current 2. Sustain reset current high forward current Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 5 SiO 2 -based 3D-OTP First reported in 2004 by Matrix (later acquired by Sandisk) This product is on the market! Advantage: CMOS process/materials, 4F 2 /n area/bit Disadvantage: only one time programmable Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 6 3

4 Programming = breakdown sensing Breakdown shunts the resistive SiO 2 layer, the polysi pn diode remains (rectification needed for select/unselect) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 7 Diode rectification In 2008, Sandisk claimed development of a rewritable 3D memory based on the same concept, that never surfaced Sandisk and Toshiba announced a cross-licensing agreement on 3D concepts in 2008 Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 8 4

5 RRAM crossbar (Samsung, 2005) 4x5 crossbar array No selection device sneakthrough Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 9 P/E characteristics Back-end compatible (room temperature) p- NiO/n-TiO 2 diode added to: Suppress sneakthrough Sustain ma-range reset current at 30x30 µm 2 Mar. 2, 2010 D. Ielmini, "Non volatile memories"

6 RRAM crossbar (Samsung, 2007) Progress at IEDM 2007: 2 layers + smaller area (F = 500 nm) thanks to higher forward current density Mar. 2, 2010 D. Ielmini, "Non volatile memories" D-1R characteristics Reset voltage higher than 2 V due to series resistance, diode onset voltage, etc. As the cell scales below 500 nm, no reset will be possible unless the forward current density is improved by diode technology Mar. 2, 2010 D. Ielmini, "Non volatile memories"

7 Forward current density Improvement mainly by band-gap/offset lowering Other constraint room temperature diode Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 13 Crossbar RRAM (Samsung, 2008) Si-based decoder cannot be stacked area benefit degrades with no. of layers oxide based stackable decoder Mar. 2, 2010 D. Ielmini, "Non volatile memories"

8 All-oxide RRAM integration Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 15 GaInZnO (GIZO) TFT transistors W/L = 160um/2um Mar. 2, 2010 D. Ielmini, "Non volatile memories"

9 CMOX memory (Unity, 2008) Individual cell in the crossbar array consists of stacked CMO (switching layer) + TO (select layer) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 17 Tunnel diode (non-rectifier) Current exponentially increases with TO thickness (SiO 2?) Relatively large current suggests TAT mechanism Mar. 2, 2010 D. Ielmini, "Non volatile memories"

10 Program/erase characteristics 3mA/25 mm 2 = 1.2x10 4 Acm -2 Analog bipolar switching Area-dependent switching Correlated changes of R and C suggest a parallel switching model with doping-dependent ε Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 19 Switching model Mar. 2, 2010 D. Ielmini, "Non volatile memories"

11 Ion migration and diffusion Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 21 CMOx device Ideal combination of crossbar + stacking + MLC Mar. 2, 2010 D. Ielmini, "Non volatile memories"

12 OTP RRAM (Samsung, 2009) t diode = 70 nm t Pt = 15 nm 0.5 um t Al2O3 = 2 nm 1D1R main advantage = room temperature (stackable) Issue = reset current stackable OTP (no reset needed!) Al 2 O 3 as active material (no reversible switching needed) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 23 Program and I-V characteristics J = 3x10 4 Acm -2 = record for oxide diode Mar. 2, 2010 D. Ielmini, "Non volatile memories"

13 PCM crossbar GST element + poly-si p-i-n diode Only one layer demonstrated Forward current 8MAcm-2 is enough for PCM reset Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 25 Diode characteristics PolySi diode compares well with epi-si p-n diode 50-nm intrinsic region to minimize reverse leakage Electrode optimization to optimize series resistance and diode contamination affecting reverse leakage Hitachi PCM, VLSI ma/(90 nm) 2 20 MAcm -2 Samsung PCM, IEDM 2006 Mar. 2, 2010 D. Ielmini, "Non volatile memories"

14 P/E characteristics episi I reset F 2 numonyx F 2 (µm 2 ) Note: does I reset really scale as F 2? Theory says I reset F (isotropic scaling) Experimental data show I reset F 1.4 (non isotropic scaling) Numonyx and Hitachi data reveals non-isotropic scaling Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 27 PCMS crossbar Concept: PCM addressed by an Ovonic threshold switch (OTS) PCMS Mar. 2, 2010 D. Ielmini, "Non volatile memories"

15 OTS Original invention by Ovshinsky in 1968 was not PCM but OTS = a diode with voltage snapback Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 29 Original Ovshinsky invention Mar. 2, 2010 D. Ielmini, "Non volatile memories"

16 Threshold and memory switching Threshold switching (an electronic process dictated by negative differential resistance) is ubiquitous for chalcogenide glasses For some chalcogenide glass (phase change materials), the dissipated power in the ON state is so large that crystallization takes place Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 31 Switching materials Threshold switching: AlAsTe*, AlGeAsTe, SiAsTe, GaSiGeAsTe, GeAsTe, GeSbTeS, GeSiAsPTe, Memory switching: InTe, GeSbTe, GeSb, SbTe, CuGeTe, AgGeTe, AlAsTe*, InSe, AgInSbTe * TS or MS depending on composition Mar. 2, 2010 D. Ielmini, "Non volatile memories"

17 Characteristics and read disturb Reset state Set state Rectifier only I read (set)=300ua Current [A] I leak I read (reset)=1ua V read /3 V read / Voltage [V] V read =3.6V The leakage from unselected bits (N-1)I leak must not exceed the sensing level I read (set)/10 Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 33 Program disturb Reset state Set state Rectifier only I read (set)=300ua Current [A] I leak I read (reset)=1ua V read /3 V read / Voltage [V] V read =3.6V Program voltage must exceed V T,reset, while inhibit voltage must be lower than V T,set Mar. 2, 2010 D. Ielmini, "Non volatile memories"

18 P/E and reliability V T window seems sufficient for read Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 35 No-select crossbar (Macronyx, 2003) Y.-C. Chen, et al., IEDM 905, 2003 PCM without OTS Rectifier provided by the amorphous phase in PCM Read is destructive, post-read refresh needed Mar. 2, 2010 D. Ielmini, "Non volatile memories"

19 Application: cross-point array WL,sel x10-4 I(1) 1x10-5 Current [A] State 1 I(0) State 0 BL,sel Voltage [V] Self-select PCM cross-point array (Y.-C. Chen et al., IEDM Tech. Dig., , 2003) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 37 Leakage 25C C Current [A] 1x10-4 1x10-5 I(1)/10 V/2 V/ Number of WLs [1] Mar. 2, 2010 D. Ielmini, "Non volatile memories"

20 C Leakage 85C Current [A] 1x10-4 1x10-5 I(1)/10 V/2 V/ Number of WLs [1] Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 39 Conclusions Crossbar is a nice idea, but many practical issues need to be solved Stackable diode: room temperature process + sufficient forward current Reset current limits NiO-RRAM to 30 um size CMOx and similar analog/uniform RRAMs seem most scalable (low I reset ) PCM crossbar seems not scalable Mar. 2, 2010 D. Ielmini, "Non volatile memories"