Passivation of SiO 2 /SiC Interface with La 2 O 3 Capped Oxidation

Transcription

1 Wednesday October 15, 214 WiPDA, Knoxville, Tennessee, USA Passivation of SiO 2 /SiC Interface with La 2 O 3 Capped Oxidation S. Munekiyo a, Y. M. Lei a, T. Kawanago b, K. Kakushima b, K. Kataoka b, A. Nishiyama b, N. Sugii b, H. Wakabayashi b, K. Tsutsui b, K. Natori a, H. Iwai a, M. Furuhashi c, N. Miura c, S. Yamakawa c a. Frontier Research Center, b. Department of Electronics and Applied Physics, c. Mitsubishi Electric Corp 1

2 Suppression of D it for higher channel mobility Interface state density (D it ) Y. K. Sharma et.al., IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 2, FEBRUARY 213 Correlation Channel mobility Lower interface defects provide better channel mobility 2

3 Resent reports on La-silicate dielectrics X. Yang et al., ICSCRM Th-2B-5 (213). Annealing after La 2 O 3 deposition formation of LaSiO x at interface Suppression of D it (< cm -2 /ev) Mobility improvement (134 cm 2 /Vs) Interface La atoms might be the key for D it reduction 3

4 Motivation of this study 1. The effect of La atoms for interface properties of SiO 2 /4H-nSiC 2. Post oxidation anneal (POA) for Lasilicate interface We try to understand the CV characteristics of SiC capacitors through comparative study of Si substrates 4

5 Outline of this presentation Introductions Understanding the CV characteristics of La 2 O 3 dielectrics on Si substrates SiO 2 /La 2 O 3 on SiC substrates CV characterization Post oxidation annealing Conclusions 5

6 Introductions Understanding the CV characteristics of La 2 O 3 dielectrics on Si substrates SiO 2 /La 2 O 3 on SiC substrates CV characterization Post oxidation annealing Conclusions 6

7 Reactively formed La-silicates La 2 O 3 reacts with Si substrates to form La-silicates 5 o C, 3 min W W W La 2 O 3 La-silicate k=23 k=8~14 La 2 O 3 silicate La 2 O 3 silicate 1 nm Si Si Higher temperature Thicker silicates with higher annealing temperature 7

8 Capacitance [F/cm 2 ] La-silicate/Si sub. on annealing temperature o C 3min 7 o C 3min 8 o C 3min 2 x 2m kHz 1kHz 1MHz Capacitance [F/cm 2 ] x 2m 2 1kHz 1kHz 1MHz Capacitance [F/cm 2 ] x 2m 2 1kHz 1kHz 1MHz Gate Voltage [V] silicon silicon silicon Gate Voltage [V] Gate Voltage [V] A hump from flatband to depletion regions appears at low frequency measurement At least 8 o C is needed to suppress the humps Also, reduction of stretching-out in CV at 8 o C 8

9 Stretch-out and humps in CV curves Capacitance density (F/cm 2 ) W/La 2 O 3 (4nm)/n-Si 6 o C, 3min 1kHz 1MHz V fb Cfb Gate voltage (V) 1. Measurement frequency dependent capacitance density 2. Difference from ideal V fb (V fb ) Reported models for humps - Localized state within the bandgap of Si (P b -like) P. Masson, et al., APL, 81, p.3392 (22). - States at deap level with phonon interaction B. Raeissi, et al., SSE, 52, p.1274 (28). Reconsider the physical origin of the CV curves 9

10 (x 1-6 ) E-E (x 1-9 i =.12 ev ) 3 5 Single level single trap response G p / (F/cm 2 ) Conductance peaks with La-silicate/Si sub Additional SiO 2 /Si SiO 2 では測定されな peak かったピーク La-Silicate/Si Frequency (Hz) Three models for conductance spectra G P qd it it 1 it 2 Continuum energy level GP q 2 Peak at low frequency corresponds to humps G P qd it ln1 it 2 Surface potential flucutaion Dit P it it 2 P ln 1 it 2 S d 1 S S exp S Spectra fitting using the above three equations S 2 1

11 Conductance spectra deconvolution G p / (x1-6 F/cm 2 ) 系列測定値 data1 系列界面 D it 2 系列膜中 D slow 3 系列界面 total4 + 膜中 E-E i =.1 ev Frequency (Hz) 1kHz~1kHz Surface potential fluctuation model (Same as SiO 2 /Si) Interface states at silicate/si ~1Hz (D it ) Single lever/trap spectrum no influence of surface potential fluctuation Slow state trap (D slow ) D slow : Trap states inside La-silicate layer 111

12 D it, D slow on annealing temperature G p / (F/cm 2 ) ( 1-6 ) 3.E E E E E E-7..E+ D slow E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E (rad/s) In FG) D it D it, D slow (cm -2 /ev) D it D slow 1 11 as Annealing temperature ( o C) D it Decrease with higher annealing temperature D slow Almost no change on annealing temperature Peak shifts to lowe frequency (longer time constant) 122

13 D slow : Traps located at La 2 O 3 and La-silicate V g C La2O3 La 2 O 3 silicate (t silicate ) D slow D it n-si Ef 3 basic evidences 1. single level/trap spectrum it, slow (cm 2 ) V fb (V) slow slow t exp silicate V fb =C La2O3 /qd slow D slow =2.8x1 13 cm -2 /ev -.3 as it =.8nm) Annealing temperature ( o C) 2. slow can be explained by the thickness of silicate layer 3.V fb can be reproduced with D slow at accumulation region Decrease in D slow Physical origin of D slow Convert all La 2 O 3 to silicates 133

14 D it reduction with high temperature annealing Absorbance (a.u.) 14 Si-O-Si La-O-Si Wavenumber (cm -1 ) Ge/La 2 O 3 /n-si ATR-FTIR 6 o Temperature ( o C) 3min La atom La-O-Si bonding Si sub. SiO 4 tetrahedron network At least 8 o C is required to suppress the stress in La-silicate S. D. Kosowsky, et al., APL, 73, p.3119 (1997). Lower than the glass transition temperature (T c ) of pure-sio 2 (~12 o C) Presence of La atoms might induce viscous flow to reduce the D it 144

15 Required process for reactively formed La-silicate dielectrics 1. Complete silicate reaction of La 2 O 3 not to leave D slow near the interface 2. Annealing over 8 o C, so as to relax the dielectrics Based on these message, process for SiC MOS capacitors are designed 155

16 Outline of this presentation Introductions Understanding the CV characteristics of La 2 O 3 dielectrics on Si substrates SiO 2 /La 2 O 3 on SiC substrates CV characterization Post oxidation annealing Conclusions 16

17 Device fabrication procedure W/SiO 2 /La 2 O 3 /4H-nSiC N d -N a =1 16 cm -3 SPM and HF(2%, 5min) cleaning EB-La 2 O 3 (nm, 4nm, 1nm) deposition Oxidation in 5%O 2, 1 o C, 3min TEOS-SiO 2 deposition (4nm) Oxidation in 5%O 2, 1 o C, 3min Gate metal(w) deposition (Sputtering) Reactive ion etching(rie)(cl 2 +O 2 ) of gate metal Backside Al contact FGA (H 2 : N 2 = 3% : 97%), 42 o C, 3min Measurement:CV W SiO 2 La 2 O 3 (, 4, 1nm) SiC epilayer (12m) SiC substrate Al 17

18 Capacitance (nf/cm 2 ) C-V characteristics with La 2 O 3 interface layer 1 8 Without La 2 O 3 La 2 O 3 (4nm) La 2 O 3 (1nm) (a) W/SiO 2 /SiC 1m/1m (b) W/SiO 2 /La 2 O 3 (4nm)/SiC 1m/1m (c) W/SiO 2 /La 2 O 3 (1nm)/SiC 1m/1m 6 5KHz 5KHz 5KHz 4 2 5kHz 5kHz 5kHz Gate voltage (V) Gate voltage (V) Gate voltage (V) Smaller humps in CV curves with La 2 O 3 Reduction in Hysteresis Interface improvements with La 2 O 3 insertion 18

19 Hysteresis voltage range (V) Hysteresis and V fb shift with La 2 O 3 insertion Flatband voltage (V) W/SiO 2 /La 2 O 3 /SiC N 2 (5%O 2 ) anneal:1 o C 1kHz no La 2 O 3 4nm La 2 O 3 thickness 1nm no La 2O 3 4nm La 2 O 3 thickness 1nm Large hysteresis reduction by one-third with La 2 O 3 insertion Negative shift in V fb ; elimination of negative charges in oxides 19

20 Capacitance density (F/cm2) D it improvements with La 2 O 3 insertion Interface state density, D it (ev -1 cm -2 ) 9.E-8 6.E-8 Tarman model 1 12 Tarman method Frequency : 5kHz 3.E-8.E+ 5kHz 1kHz 5kHz Presence of D slow Gate voltage (V) Surface potential (V) V g V fb = Q s ψ s + Q it ψ s + ψ s Tarman method : TEOS only : TEOS-SiO 2 + La 2 O 3 (4nm) : TEOS-SiO 2 + La 2 O 3 (1nm) C ox D it = Q it ψ s D it reduction by two third with La 2 O 3 insertion Little difference with the amount of insertion Concerns about the presence of D slow q

21 Rough interface but reduced D it 4 o off SiO 2 La-silicate 5nm 4H-SiC(1) Grains of La-silicate, 1nm apart from the interface, may not respond to CV curves (too long for tunneling) Trace amount of La atoms might be presented at the interface, resulting in lower D it (High solubility of La atoms in SiO 2 ) 21

22 Reports on post oxidation anneal for SiO 2 /SiC R. H. Kikuchi, K. Kita, Appl. Phys. Lett, 15, 3216 (214) Residual carbon in bulk SiO 2 When near the interface a hump appears Thermal SiO 2 POA at 8 o C SiC Residual carbon at interface (D it ) Post oxidation anneal (POA) at low temperature (<8 o C) removes carbons in bulk as well as interface, without additional SiC oxidation 22

23 Device fabrication with POA at 8 o C W/SiO 2 /La 2 O 3 /SiC SPM and HF(2%, 5min) cleaning EB-La 2 O 3 (nm, 1nm) deposition Oxidation in 5%O 2, 1 o C, 3min TEOS-SiO 2 deposition (4nm) Oxidation in 5%O 2, 1 o C, 3min POA in 5%O 2 at 8 o C, 3min Gate metal(w) deposition (Sputtering) SiC substrate Al N d -N a =1 16 cm -3 Reactive ion etching(rie)(cl 2 +O 2 ) of gate metal Backside Al contact FGA (H 2 : N 2 = 3% : 97%), 42 o C, 3min Measurement:CV W SiO 2 La 2 O 3 (, 1nm) SiC epilayer (12m) 23

24 Capacitance (nf/cm 2 ) Effect of Post Oxidation Anneal Capacitance (nf/cm 2 ) Without La 2 O 3 La 2 O 3 (1nm) w/o La 2 O 3 layer L/W=1/1μm 1kHz POA at 8 o C w/o POA La 2 O 3 = 1nm L/W=1/1μm 1kHz POA at 8 o C w/o POA Gate voltage (V) Gate voltage (V) No POA effect for deposited SiO 2 Better CV curves with La 2 O 3 inserted SiC capacitors 24

25 Interface state density, D it (ev -1 cm -2 ) Hysteresis voltage range (V) Hysteresis and D it improvements with POA Capacitance voltage (F/cm2) W/SiO 2 /La 2 O 3 /SiC N 2 (5%O 2 ) anneal:1 o C 1kHz 9.E-8 6.E no La 2 O 3 4nm 1nm La 2 O 3 thickness Tarman method Frequency : 5kHz 1nm(POA) 3.E-8.E Gate voltage (V) : TEOS only : TEOS-SiO 2 + La 2 O 3 (4nm) : TEOS-SiO 2 + La 2 O 3 (1nm) : TEOS-SiO 2 + La 2 O 3 (1nm) + POA Surface potential (V) D it reduction and D slow suppression La atoms in SiO 2 generate radical oxygen These active oxygen atoms may effectively eliminate the carbon at and near the interface 25

26 Conclusion La 2 O 3 insertion between SiO 2 /4H-nSiC have shown improved interface properties: D it of 1 11 cm -2 /ev (from 5x1 11 cm -2 /ev) Hysteresis.45 V (from 1.8V) La atoms at the interface to relax the SiO4 network might be the origin Post oxidation annealing at 8 o C Deposited SiO 2 /4H-nSiC Little improvement La 2 O 3 inserted SiO 2 /4H-nSiC Further D it reduction down to 1 11 cm -2 /ev Hysteresis down to.35 V Presumable the generation of radical oxygen by La-atoms to effectively eliminate the C at and near the interface 26