New conductors what are the options? Marleen van der Veen

Transcription

1 New conductors what are the options? Marleen van der Veen

2 Content Trends and roadmaps Dual damascene: multi-patterning and EUV Alternative conductors and examples of implementation Summary

3 Trend 1: scaling dimensions, new materials 36nm BEOL pitch Air gaps in memory and logic Co interconnects 10nm technology, Intel C. Auth et al. IEDM 2017 Intel/Micron 25nm node NAND using air gaps K. Prall/K. Parat IEDM2010 K. Fisher et al., Intel 14nm IITC2015 Self- aligned contact, C. Auth et al. Intel IEDM 2017 Reliability of Co, F. Griggo et al. Intel IRPS 2018 Co MOL as W replacement, J. Kelly et al. IBM/Globalfo undries, IITC2016

4 Trend 2: High performance logic transistor scaling

5 Trend 3: add scaling boosters

6 Circuit sensitivity to RC Mx (lower level) wire and via resistance remain critical with scaling

7 Track height scaling Track height scaling: wirelength decreases, but number of vias in critical path increases

8 Multi-patterning and EUV insertion

9 Relative cost i-saqp dual damascene Scaling: in7 => in5 Cost 16nm hp EUV hybrid All Immersion-1 All Immersion-2 EUV block EUV insertion reduces module cost B. Briggs (imec) et al. IITC 2017

10 EUV single print M2: 32nm pitch and CD~20nm short lines are functional, despite some defectivity, From MP34 and above good uniformity. S. Lariviere (imec) et al. SPIE 2018

11 Cost [a.u.] # Process steps Benefits of EUV insertion ~100 days 20% 3.2% ~33 days ~16 days All iarf EUV EUV metal All iarf EUV blocks&vias EUV metal &via single blocks&vias & via single Process simplification, Cost, Time to yield

12 Alternative conductors

13 What is this?

14 Resistivity What is this? Conductor Critical dimension (CD)

15 Figure of merit

16 Technical scorecard

17 Technical scorecard Note that for implementation not only resistivity will matter, but a number of other factors as well. For example, Recrystallization temperature Adhesion Cost Reliability Manufacturability...

18 Resistivity of If and Rh interconnects Both Rh and Ir outperform Co or Ru at areas between 40 and 100 nm 2 by about 30%. Rh and Ir with respect to Cu about 2X better in terms of resistivity at 7 nm CD. Electrical area (nm 2 ) C. Adelmann (imec) et al. IITC 2018

19 How much does it cost Ru Mo Source: infomine.com ELEMENT Rh Au Ir Ru Co W Mo Ni Cu PRICE 2425 USD/OZT 1226 USD/OZT 1480 USD/OZT 265 USD/OZT 27 USD/LB 15 USD/LB 12 USD/LB 6.5 USD/LB 2.8 USD/LB

20 Conductors in memory and logic Memory Logic 3D NAND Word line: Many layers, scaled Perhaps for 128 layers or later DRAM Buried wordline SCM Maybe at 30nm pitch, but today low volume W Mo Ru Compound W Cu Co Ru Mo, Ir,... Compound

21 Co, Ru, Cu benchmark Line resistance log scale Via resistance J Fuse Cu: Fill issues < 400nm 2 for Cu with 2nm barrier/ liner. Cu Co + barrier Co Ru Co, Ru, Cu benchmark to 12nm and below Ru intersection with Cu, Co ~12nm; Alternative metal has the biggest impact on via resistance Alternative metals have high current carrying capability M. van der veen (imec) et al. IITC 2018

22 Buried rail BPR resistance M1/V0/Mint/Vint/M0A/VBPR options A. Gupta (imec) et al. IITC 2018 Minimize BPR and access resistance

23 Buried rail No anneal Y-section along the line 650 o C anneal A. Gupta (imec) et al. IITC 2018 FEOL compatible with 33% resistivity decrease

24 Cumulative Probability Metal patterning Metal patterning combined with EUV single print results in uniform MP32 lines. Resistance (Ω) 14nm 16nm 18nm 20nm 22nm 24nm MP32 D. Wan (imec) et al. IITC 2018

25 Anything beyond pure elements? K. Shankaran (imec) et al. IITC 2018 Multiple MAX compounds are of interest on the longer term

26 Summary Conductors alternative to conventional metallization are emerging Both memory and logic require better and cost effective metals R&D pipeline is defined even beyond pure elements