ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

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1 ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential

2 Things you should know when you leave Key Questions What are the necessary steps to fabricate a p-n junction? Why should you use ion implantation? Why is reactive ion etching used over chemical etching? What is the contact potential qualitatively?

3 Thus far, we have only discussed how devices work We have completely neglected how these devices are made. We had alluded to some part of fabrication and processing when we discussed MBE. ELECTRON- DIFFRACTION SOURCE CHAMBER WALLS COOLED WITH LIQUID NITROGEN KNUDSEN CELLS CONTAINING Ga, Al, As & Si 600 C TEM IMAGES OF EPITAXIALLY GROWN GaAs/AlGaAs UHV PUMP ELECTRON- DIFFRACTION DETECTOR

4 So, let s talk about how to make a semiconductor device Many different steps require heating the wafer to enhance or catalyze a chemical process. An important example of this is the process of thermal oxidation. Thermal oxidation is the process of heating Silicon to grow SiO2. Can either be done in oxygen (dry, O 2 ) or in the presence of water (wet, H 2 O). Very high temperatures ( C o ) in ceramic lined furnaces. Oxygen or water is flowed into the furnace. For every 1000 nm of SiO 2, 440 nm of Si is consumed.

5 Another important thermal process is diffusion After SiO 2 is grown on the surface using the process of oxidation, we need to introduce dopants. To introduce dopant atoms, we need to use photolithography and etching steps to open holes in the SiO 2. Dopants are introduced in a high temperature furnace using either a gas, vapor or solid source. Dopants are transported from the high concentration gasses to the low concentration wafers via diffusion. The diffusion of different dopants has a very strong temperature dependence. Diffusion length: Thermal Budget

6 We must control the temperature very precisely Dopant diffusion is blocked in SiO 2 regions because their diffusivity in SiO 2 is very small. The difficulty in controlling the dopant diffusion process led to the eventual replacement of dopant diffusion from sources to ion implantation. Locations of the impurity atoms can be calculated at any point in time by solving the diffusion equation with the appropriate boundary conditions. What we end up with is a graded rather than step junction where the junction is formed when the acceptor concentration equals the background donor doping concentration. We want this Time and temperature control the depth of the junction. Cleanliness is important use HF and expensive cleanrooms We get this

7 The thermal budget is extremely important, how can we minimize this number? Normally in a diffusion furnace the wafers are kept at high temperatures for hours. This is not helpful to the thermal budget. Failure to keep the thermal budget down results in a loss of control over the doping profile which is critical in ultra-small Must watch temperature and uniformity! devices. One way to maximize the thermal budget is to use low temperature processes. Another popular way is to use a high temperature process but for a short duration. This is called Rapid Thermal Processing.

8 Diffusing dopants in a furnace requires lots of effort, isn t there an easier way? We can use ion implantation Direct implantation of ions into a semiconductor via a high energy beam (~kev - MeV). Impurities enter the lattice and give up excess energy by scattering coming to rest at an average penetration depth or projected range. How does it work? Gas is ionized within the source. Ions are accelerated in the accelerator tube. Passed through a mass separator to make sure the beam is pure. Then focused on the surface.

9 Ion implantation has clear advantages and disadvantages Range Straggle Advantages: Can be done at low temperatures. Ions can be blocked by metal or photoresist layers. Precise control over doping concentration. Disadvantages: Implantation will damage the surface of the wafer and lattice due to collisions. Damage can mostly be reversed by annealing. Annealing is heating the crystal lattice after ion implantation to repair the lattice. Care must be exercised so as to not exceed the thermal budget. 2 φ x R N ( x) = 2π 2 ( R + 2Dt) P 1 2 exp 1 2 ( ) R 2 P P + 2Dt Dose of boron atoms per cm 2 injected at 140 kev.

10 What if we don t want to use thermal oxidation? We can still deposit materials that we desire by using chemical vapor deposition Normally used to deposit thin films of semiconductor, insulator and metals. We can deposit SiO 2 onto a surface at much lower temperatures and without consuming any of the underlying silicon. SiO 2 is not as good of quality as in the case of the thermally grown samples. Chemical reaction using SiH 4 with an O 2 precursor begins reaction leading to SiO 2 growth.

11 We use photolithography to transfer patterns from a mask to the semiconductor surface The first step in transferring a pattern to the surface comes by creating a quartz reticle. The opaque regions are made of an ultra-violet light absorbing material like Fe 2 O 3. Wafers are coated with photoresist which undergoes a chemical change when it is exposed to ultra-violet light. This is normally done via spinning. Light shines on exposed regions and causes the resist to acidify. Developer solution (a base e.g. NaOH) is used to remove the photoresist from the exposed regions. Light is shone on surface with a stepper.

12 Fabricating a P- N Junction But we still need to pattern the SiO 2 that we ve grown This process of patterning the underlying oxide layer is called etching. For many years, chemical etching (wet) was used to pattern the oxide. The resultant etch is normally isotropic which meant it removed films laterally as well as vertically. To overcome this, reactive ion etching (RIE) is now used. Chloroflurocarbons are introduced into the chamber at low pressures and a plasma is formed by applying an RF voltage across a cathode and an anode. The voltage accelerates the light electrons into heavy ions forming radicals. The radicals bombard the surface and unselectively etch the surface.

13 Fabricating a P- N Junction Let s top it off by adding a metal to the mix The metallization step is normally accomplished using sputtering Sputtering of Al is accomplished by immersing an Al target in an Ar plasma. Ar atoms physically dislodge the Al atoms by momentum transfer. Many of the Al atoms are transferred to the silicon wafer which is sitting near the target. The Al is then patterned using RIE.

14 Fabricating a P- N Junction Let s summarize the fabrication process

15 Contact Potential Now let s start analyzing the p-n junction We want to form a compromise between a very detailed description of the physics of the p-n junction and a solid qualitative understanding of its operation We have two different models: P-type N-type 1. Step junction (alloyed and epitaxial junctions) 2. Graded junctions (diffused junctions where N d N a varies over a significant distance across the junction) Our plan: Explore the step junction and extend the understanding to deal with the graded junction. Our starting point: We are starting in equilibrium with no external excitation and no external currents.

16 Contact Potential What do we expect to happen when we join them together? P-type N-type We expect to find the following when we connect the p-type semiconductor with the n-type semiconductor: The potential difference between the two regions resulting from the doping discrepancy will cause a potential difference between the two regions. There should be four components of current across the junction due to drift and diffusion. The four components must add to give zero net current at equilibrium.

17 Contact Potential But we already know what will happen when we join them together P-type N-type W Contact Potential φ p (diff) φ p (drift) φ n (diff) φ n (drift) J p (diff) J p (drift) J n (diff) J n (drift) Dashed Arrows = Particle Flow Solid Arrows = Resulting Currents