Deuterium pressure dependence of characteristics and hot-carrier reliability of CMOS devices

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1 Microelectronic Engineering 56 (001) locate/ mee Deuterium pressure dependence of characteristics and hot-carrier reliability of CMOS devices a, a b a a Kangguo Cheng *, Jinju Lee, Zhi Chen, Samir Shah, Karl Hess, Joseph W. Lyding *, Young-Kwang Kim, Young-Wug Kim, Kuwang Pyuk Suh a, c c c a Beckman Institute for Advanced Science and Technology, University of Illinois at Urbana-Champaign, 405 N. Mathews Ave., Urbana, IL 61801, USA b Department of Electrical Engineering, University of Kentucky, Lexington, KY 40506, USA c CPU Division, Samsung Electronics Company, Ltd., Kyungki-Do , South Korea Received 1 February 001; accepted May 001 Abstract Deuterium annealing has been widely demonstrated to be an effective way to improve the hot-carrier reliability of MOS devices. In this paper, we present a thorough study of the effect of deuterium pressure on the characteristics and hot-carrier reliability of MOS devices. N-channel submicron MOS transistors were annealed in deuterium with various pressures, temperatures and annealing times. It is found that device reliability initially improves as deuterium pressure is increased. It reaches a maximum and then begins to degrade with further increase of pressure. For the devices after hydrogen anneal, device reliability constantly degrades as the hydrogen pressure increases. It is concluded that the benefit of high pressure deuterium processing on device reliability is attributed to improved deuterium incorporation, while annealing-induced interface trap creation can negate the benefit at extreme high pressure. It is further shown that the processing temperature can be lowered with high pressure while still maintaining the deuteration benefit. This is particularly significant for future CMOS technology that requires a reduced thermal budget. 001 Elsevier Science B.V. All rights reserved. Keywords: Hot-carrier effects; CMOS devices; Reliability; Deuterium; Interface trap; Silicon oxide 1. Introduction As the feature sizes of CMOS devices shrink into deep submicron range without a proportional reduction in operation voltage, hot-carrier effects have become one of the most important concerns for device reliability [1]. It has been found that device lifetimes due to hot-carrier effects can be significantly improved by incorporating deuterium at the silicon oxide/ silicon interface [ 4]. Compared with other approaches to reduce hot-carrier effects, deuteration has the advantage that it is *Corresponding author. addresses: cheng@us.ibm.com (K. Cheng), j-lyding@uiuc.edu (J.W. Lyding) / 01/ $ see front matter 001 Elsevier Science B.V. All rights reserved. PII: S (01)0057-X

2 354 K. Cheng et al. / Microelectronic Engineering 56 (001) completely compatible with current device technology and thus is easily implemented. The major practical issue associated with using deuterium processing is to incorporate significant levels of deuterium at the oxide silicon interface. On approach is to switch from hydrogenated to deuterated chemistries at various fabrication steps [5]. A more straightforward way to improve deuterium incorporation is to increase processing temperature and/ or time. Unfortunately, high temperature annealing conflicts with the use of new materials such as low-k dielectrics in state-of-the-art CMOS technology. Increased processing time means lower production efficiency and higher cost. Our initial study shows that deuterium incorporation is significantly enhanced by a high pressure deuterium annealing process [6]. In this paper, we present a thorough study of high pressure deuterium and hydrogen annealing on device characteristics and reliability. The use of high pressure in conjunction with lower processing temperature is also presented.. Devices and experimental Devices used in this study were n-channel MOS transistors with n poly Si gate fabricated at Samsung Electronics by 0.35 mm CMOS technology. The gate length at the mask level is 0.30 mm and the gate width is 8.75 mm. The gate oxide thickness is 55 A. Transistors from one wafer were divided into two groups. One group was annealed in hydrogen and the other group was annealed in deuterium. Annealing variables include annealing pressure (1 15atm), annealing temperature ( C) and annealing time (0.5 0 h). Interface trap density N, and device characteristics, such as it the threshold voltage Vt and transconductance G m, were measured before and after annealing. The charge pumping technique [7] was used to measure N it. For charge pumping measurements, the gate was pulsed by a rectangular waveform with a frequency f khz, amplitude DV5 3 V, and rise 7 and fall times of tr5 tf5 10 s. A reverse bias of 0.1 V was applied to the source and drain and the base was swept from 5 to 1 V. The drain current I d, was measured as a function of gate voltage Vg with a fixed drain voltage 0.1 V to determined Vt and G m. Vt is defined as the gate voltage to introduce a drain current I 5 5 ma. G was evaluated as the maximum slope of the I V curve. d m d g The device reliability was tested by standard hot-carrier stressing at the peak substrate current condition with the bias conditions Vds V, Vgs V and the grounded source and substrate. Interface trap density and device characteristics were measured periodically during hot-carrier stress. All electrical testing was performed by using a HP4155A semiconductor parameter analyzer Results and discussion Most interface traps in CMOS devices are believed to be silicon dangling bonds at the silicon dioxide/ silicon interface [8]. For effectiveness of deuteration, deuterium must reach the interface by diffusion through the interconnection metal and dielectric layers. The deuterium concentration at the interface can be expressed as ]] n 5 C? P? [1 erf(x/ 4D t)] (1) D D œ D Where PD is the deuterium pressure, x is the total thickness of metal and dielectric layers, t is the annealing time, D is the deuterium diffusion constant which is assumed to have the same value for D

3 K. Cheng et al. / Microelectronic Engineering 56 (001) all metal and dielectric layers, and C is a constant. The passivation of silicon dangling bonds at the interface can be represented by Si? 1 D Si D () where Si? represents an unpassivated silicon dangling bond. The passivation rate k for reaction () can be expressed as Si? nd k 5 n where n Si is the density of silicon dangling bonds. Combining Eq. (1) and Eq. (3) one can obtain ]] k 5 C? n? P? [1 erf(x/ 4D t)] (4) Si D œ D Eq. (4) indicates that the passivation rate is proportional to the deuterium pressure. Although Eq. (4) might be too simple to describe the complicated passivation process at the oxide/ silicon interface, it provides reasonable guideline at least at primary state. Fig. 1 shows the annealing time dependence of interface trap density at different deuterium pressures. The interface trap density before annealing 10 was 3310 cm. For a given annealing time, more dangling bonds are passivated by deuterium with higher pressure annealing. For instance, the interface trap density after annealing at 6 atm is about 50% lower than that after annealing at 1 atm. Since device performance degrades with interface trap buildup, device performance is also improved by high pressure annealing. Fig. confirms that, for the same annealing time, significant transconductance improvement is achieved after high pressure annealing. 1 Even the best oxide growth techniques still result in 10 cm silicon dangling bonds at the 10 interface. However, the interface trap density in our fresh devices was 3310 cm, indicating that most interface traps had already been passivated before deuterium annealing. This is due to the ubiquitous presence of hydrogen in modern CMOS processing technology. Consequently, effective deuteration requires not only the delivery of deuterium to the SiO Si interface but also replacement (3) Fig. 1. Passivation of interface traps by deuterium at various pressures.

4 356 K. Cheng et al. / Microelectronic Engineering 56 (001) Fig.. Transconductance as a function of deuterium annealing time at various pressures. of the previously bonded hydrogen by deuterium. The replacement can be expressed by the following reaction: Si H 1 D Si D 1 HD (5) And the reaction rate, k 5, is obtained ]] k 5 n? n 5 C? n? P? [1 erf(x/ 4D t)] (6) 5 Si H D Si H D œ D Eq. (6) indicates that the replacement rate of hydrogen by deuterium, k, increases at high 5 deuterium pressure. The enhanced deuterium incorporation suggests reduced interface trap creation under hot-carrier stress. This is demonstrated in Fig. 3 for deuterium pressures up to 6atm. Fig. 3. Deuterium pressure dependence of hot-carrier-induced interface trap creation. Annealing condition: 4508C/3 h. Stress conditions: Vds53.8 V, Vgs51.4 V for 10,000 s.

5 K. Cheng et al. / Microelectronic Engineering 56 (001) Fig. 4. Hydrogen pressure dependence of hot-carrier-induced interface trap creation. Annealing condition: 4508C/ 3 h. Stress conditions: Vds53.8 V, Vgs51.4 V for 10,000 s. It is interesting to note that device reliability gets worse after annealing at 15atm (see Fig. 3). We speculate that some Si Si and Si O bonds can be broken by deuterium (or hydrogen), causing excessive traps at the interface. Although these new interface traps can also be passivated by deuterium, annealing-induced interface trap creation gives rise to a higher initial density of Si D bonds which are broken during the subsequent stressing. To confirm this conjecture, we annealed several identical devices in hydrogen at same temperature (4508C) and for the same time (3 h) but at different pressures. The devices were then stressed and the time dependence of interface trap creation is shown in Fig. 4. The deterioration of device reliability after high pressure hydrogen annealing supports the hypothesis of annealing-induced interface trap creation. Therefore, we conclude that high pressure deuterium annealing has two opposing effects on device reliability. The efficient replacement of hydrogen by deuterium through the high pressure deuterium process improves device reliability, while the generation of interface trap precursor negates this benefit. The competition of these two effects suggests that process optimization is necessary to achieve the maximum device reliability improvement by high pressure deuterium annealing process. Fig. 5 shows that a transistor after annealed in deuterium at 4008C/6 atm exhibits even better reliability than one annealed in deuterium at 4508C/ 1 atm. Therefore, high pressure deuterium processing is potentially significant for future CMOS technology that requires a reduced thermal budget for the use of low-k dielectric materials. 4. Conclusions A study of the effect of high pressure deuterium processing on the characteristics and hot-carrier reliability of MOS devices has been presented. High pressure processing improves device performance due to the enhanced passivation of interface traps by deuterium. However, prolonged processing at high pressure produces additional interface traps that degrade the hot carrier reliability. The effectiveness of using high pressure to reduce processing temperature has also been demonstrated.

6 358 K. Cheng et al. / Microelectronic Engineering 56 (001) Fig. 5. Threshold voltage shift (VtV t0) and transconductance degradation (Gm0 G m)/gm0for transistors annealed in hydrogen at 4008C/ 1 atm (square symbols), annealed in deuterium at 4508C/ 1 atm (triangle symbols) and annealed in deuterium at 4008C/6 atm (circle symbols). Annealing time was 3 h and stress conditions were Vds53.8 V, Vgs51.4 V for all transistors. Acknowledgements This work was supported by the Office of Naval Research under Grants N and N and the Beckman Institute for Advanced Science and Technology at the University of Illinois at Urbana-Champaign. The authors also thank Ronald Rattray of Spectra Gases Inc. for providing the deuterium used in these experiments. References [1] E. Takeda, C.Y. Yang, A. Miura-Hamada, in: Hot-carrier Effects in Mos Devices, Academic Press, San Diego, CA, 1995, p. 1. [] J.W. Lyding, K. Hess, I.C. Kizilyalli, Appl. Phys. Lett. 68 (1996) 56. [3] I.C. Kizilyalli, J.W. Lyding, K. Hess, IEEE Electron Dev. Lett. 18 (1997) 81. [4] K. Hess, I.C. Kizilyalli, J.W. Lyding, IEEE Trans. Electron Dev. 45 (1998) 406. [5] T.G. Ference, J.S. Burnham, W.F. Clark, T.B. Hook, S.W. Mittl, K.M. Watson, L.K.K. Han, IEEE Trans. Electron Dev. 46 (1999) 747. [6] J. Lee, K. Cheng, Z. Chen, K. Hess, J.W. Lyding, Y.-K. Kim, H.-S. Lee, Y.-H. Lee, K.-P. Suh, IEEE Elec. Dev. Lett. 1 (000) 1. [7] P. Heremans, J. Witters, G. Groeseneken, H.E. Maes, IEEE Trans. Electron Dev. 36 (1989) [8] S. Pantelides (Ed.), Proceedings of the International Topical Conference On the Physics of SiO and Its Interfaces, Pergamon, New York, NY, 1980.