A Proposal of Schottky Barrier Height Tuning Method with Interface controlled Ni/Si stacked Silicidation Process

Transcription

1 222 nd ECS Meeting A Proposal of Schottky arrier Height Tuning Method with Interface controlled Ni/Si stacked Silicidation Process Y. Tamura 1, R. Yoshihara 1, K. Kakushima 2, P. Ahmet 1, Y. Kataoka 2, A. Nishiyama 2, N. Sugii 2, K. Tsutsui 2, K. Natori 1, T. Hattori 1, H. Iwai 1 1 Frontier Research Center, Tokyo Institute of Technology 2 Interdisciplinary Graduate School of Science and Engineering 1

2 Silicide Schottky source/drain (S/D) FETs Scaling in MOSFET Issue: short-channel effect Silicide Schottky S/D Reports on Ni silicide W. Mizubayashi et al., VLSI symp., 88 (2011). N. Mise et al., TED, 55, 1244 (2008). Advantage of silicide Schottky S/D - abrupt and shallow junction - robust against short-channel effect - low resistance - low temperature process J. M. Larson et al., TED, 53, 1048 (2006). Silicide Schottky S/D is a candidate for scaled FETs. a) Gate Hard mask Source Drain Source Drain Gate Dopant Conc. Conventional doping S/D (b) Gate Metal Metal Metal Metal Gate Metal Conc. Metal S/D δ σ L phy Gate δ σ y position L phy = L eff Gate y position 2

3 Issues in silicide reaction Thickness dependent silicide phase change Pattern dependent interface reaction t Ni (nm) Morphology problem due to agglomeration NiSi NiSi + Ni atom diffusion STI (111) facet Si STI 50nm (111) facet Si(100) 4nm Ni-rich phase Ni Lateral Ni atom diffusion Annealing temperature ( o C) K. Tsutsui et al., Microele. Eng., 85, 315 (2008). L. Knoll et al., EDL, 31, 350, (2010). OX Ni source silicide encroachment 200nm M. Koyama et al., ESSDERC, 231 (2011). Control of silicide phase and interface reaction with wide process window is required for silicide Schottky S/D FETs. 3

4 Schottky barrier height (φ n ) modulation Dopant segregation with silicidation Dopant segregation by activation anneal A. Kinoshita et al., IWJT, 34 (2009). W. Mizubayashi et al., VLSI symp. (2011). Control of dopants and junction position are the key. 4

5 Contents of presentation 1. Introduction 2. Stacked silicidation process 3. φ n modulation 4. Demonstration of SOI-silicide Schottky S/D FET 5. Conclusion 5

6 Our approach Purpose For future scaled silicide Schottky S/D FETs - position control of silicide/si interface - φ n modulation by impurity incorporation Our approach: Ni/Si stacked silicidation process Si(1.9nm)/ Ni(0.5nm) Ni/Si stack structure annealing Impurity incorporation Si(1.9nm)/ Ni(0.5nm) impurity - Ni and Si deposition to limit consumption Si Sub to the first Ni layer - Ni and Si layers with an atomic ratio of 1:2 to form Impurity position and amount are controllable. 6

7 Schottky diode fabrication process Sub with 400 nm SiO 2 (3x10 15 cm -3 ) SPM and HF cleaning Diode patterning Ni/Si stacked structure Si(1.9nm)/ Ni(0.5nm) x 8 layers HF etching of SiO 2 Deposition by RF sputtering (Ni:0.5nm/Si:1.9nm) x 8 (Ni:0.5nm/Si:1.9nm) x 7 + (Ni 3 P:0.68nm/Si:1.9nm) (Ni:0.5nm/Si:1.9nm) x 8 + :0.13nm Si/Ni x 7 layers Impurity incorporating Si/Ni x 8 layers ackside Al contact RTA: 1min in N 2 (silicidation) Ni 3 P 7

8 Interface reaction of stacked silicidation process as deposited 8 sets of Si(1.9nm)/Ni(0.5nm) 10nm Cross sectional TEM Si(100) RTA: 500 o C 10nm Si(100) Ni OX OX Ni silicide - atomically flat interface and smooth surface Si Si Fin Ni silicide encroachment Ni No encroachment - no thickness change before and after annealing - interface position can be well-defined Silicidation with narrow Fins 500nm 500nm Si Fin Ni silicide encroachment 500 o C Ni Ni case stack case Ni/Si stack No encroachment 500 o C Si Fin Stacked silicidation process is candidate for silicide Schottky S/D. 8

9 XPS analysis of Ni/Si stacked silicide film XPS Angle resolved XPS hν= ev RTA : 1min hν= ev RTA: 500 o C Intensity (a.u.) Ni2p 3/2 as depo t Ni : 3.0 nm 500 o C Ni/Si stack Ni Intensity (a.u.) Ni2p 3/2 Ni/Si stack TOA 30 o 40 o 52 o 80 o inding energy (ev) inding energy (ev) 851 Ni/Si stacked silicide is uniform films at 500 o C. 9

10 Thermal stability of stacked silicidation process Sheet resistance Surface roughness Sheet resistance ρ sh (Ω/sq) RTA : 1min in N 2 agglomeration wide process window Annealing temperature ( o C) Ni:5.5nm Roughness (nm) RTA : 1min in N agglomeration wide process window Annealing temperature ( o C) Ni:5.5nm with stacked silicidation process is stable from 350 o C to 850 o C. 10

11 Interface reaction of impurity incorporation Cross sectional TEM RTA: 500 o C, 1min P incorporated incorporated Si/Ni x 7 layers anneal anneal Si/Ni x 8 layers Ni 3 P Si(100) Si(100) 10nm 10nm - atomically flat interface and smooth surface - no thickness change before and after annealing Even with impurity incorporation, the interface reaction with stacked silicidation process are also maintained. 11

12 SIMS impurity profiles with stacked silicidation process P concentration (cm -3 ) as depo Si Sub. P 500 o C P concentration (cm -3 ) as depo Si Sub. RTA:1min in N o C Depth (nm) Depth (nm) - some impurities diffused into - impurities reside in the interface Impurity position can be controlled by stacked silicidation process. 12

13 Current density (A/cm 2 ) φ n modulation by P or incorporation Diode characteristics RTA : 500 o C, 1min in N 2 P: Ohmic Control: 0.63 ev : 0.68 ev Applied voltage (V) φ n modulation is confirmed. P Dependence of annealing temperature φ n (ev) n-factor RTA : 500 o C, 1min in N 2 P: Ohmic Control Control Annealing temperature ( o C) Stable property with wide process window φ n modulation is achieved by impurity incorporation at interface with stacked silicidation process. 13

14 Fabrication process stacked silicide SOI-silicide Schottky S/D FET SOI patterning Gate oxide (1000 o C) Stacked silicide for S/D (with or P) TEOS (200 o C) Gate metal depo./etch. Contact FG anneal (500 o C) Drain current (A) metal oxide OX SOI The process temperature was set below 500 o C except for gate oxide formation P V d = 3 V I d -V g characteristics W/L=6.0/1.5µm T Si =30nm T ox =76nm V d = 3 V V d = 0.1 V V d = 0.1 V Gate voltage (V) Ambipolar characteristics is suppressed by P incorporating. φ n modulation was also confirmed with FET operation. P 14

15 Conclusions Ni/Si stacked silicidation process - atomically flat silicide/si interface - junction position is well-defined - stable property up to 850 o C annealing Schottky barrier height (φ n ) modulation - φ n modulation is achieved by P or incorporation at interface (ohmic ~ 0.68 ev) - suppression of ambipolar characteristics with silicide Schottky S/D FET The authors would like to thank Prof. H. Nohira with Tokyo City University for XPS measurement. 15