MEMS 製造技術與元件發展 : 晶圓代工觀點

Transcription

1 MEMS 製造技術與元件發展 : 晶圓代工觀點 MEMS Manufacture Platform and Device Development : Aspect from MEMS foundry Presenter : Vincent Lin Ph.D 探微科技 Touch Micro-system Technology Vincent_lin@tmt-mems.com P. 1

2 Outline Foundry aspect of MEMS Biz CMOS & MEMS integration approaches: - Multi-Chips integration: MCM packaging - Monolithic integration: CMOS-MEMS - Multi-Wafer integration: Wafer bonding & WLP Basic skill sets CMOS/MEMS integration: -Essential elements - Bonding technology - Deep-Si machining - Standard cells - Summary of the integration paths Manufacturing challenge of Application-Specific MEMS : - Sensor domain: Si-Microphone, accelerometer - RF integrated passives - Silicon optical bench Conclusion remarks P. 2

3 tmt Company Introduction CKS Intl Airport TAIPEI Yang-Mei HsinChu The First Professional MEMS Foundry in Taiwan (2001) The 200mm MEMS Foundry provide BE and WLP solution in Taiwan (Few in the World) Strategic Position Professional MEMS Technology Developer & Manufacturing Platform Provider (Co-Development) (Foundry Service) The Profitable MEMS Foundry in Taiwan MEMS Manufacturing Platform Available P. 3

4 Walsin Group Core Business Global over 50,000 Employees 2006 Group Revenue 36 Plants in Greater China 8 Listed Companies within the Group 8,143 Million USD USD Million 9000 SemiConductor Walsin Group Core Biz Passive System Alliance Basic Material & Machining MOEMS Biz development Group Optical Electronic Basic Materials Optical Electronics Semiconductor PSA P. 4

5 IC & MEMS integration-history Semiconductor IC Discrete Optoelectronic -Transistor Memory Analog Logic Micro- -Diode component -HBT -PHEMT -LED/LD -PD -CCD 2 to 6 Si or Compound 6 BiCMOS >8 CMOS process Surface Post CMOS Bulk Smart Substrate/IPD micromachining micromachining micromachining /MEMS actuator PZR Emerging MEMS Sensor product From 1970 From Integrated + DLP/Inkjet/CIS Sensor From 1980 From 1990 SoC Technology + + SiP Technology P. 5

6 IC & MEMS monolithic- The must Interconnection is the key: a) Array MEMS: Millions MEMS to millions transistors b) Sensing MEMS: Small S/N ratio T/M = Number of Transistors, T DLP 106 Integrated sensors 10-4 Ink jet Majority of existing MEMS devices Adapted from Gabriel, Kaigham. Engineering Microscopic Machines. Scientific American, September Number of Mechanical Components, M 108 P. 6

7 IC & MEMS integration- Three approaches Microsystems IC Multi-chips integration: - Only for large signal MEMS - Need special PKG MEMS PKG IC/MEMS monolithic: - Direct interconnection - Need special PKG MEMS/PKG monolithic: - Low noise Flip-chip bonding - Easy to PKG Cap MEMS MEMS CMOS Cavity PKG CMOS/MEMS Cavity PKG CMOS Standard PKG DRIE and bonding technologies become the key of IC/MEMS integration P. 7

8 Alternative solution (WLP) Define the essential elements: CMOS wafer, MEMS wafer, Cap wafer (C) Cap/Smart substrate wafer Solder ball for SMT Through Silicon Via, TSV Head space for MEMS Thick-metal redistribution Eutectic seal ring Flip-chip bumping Redistribution & bonding High A/R Structure for S/A Redistribution & bonding (B) High A/R Si MEMS wafer Redistribution & bonding Surface-MEMS structure CMOS/Bi-CMOS or BCD Sacrificial release (A) CMOS/MEMS wafer P. 8

9 Outline Foundry aspect of MEMS Biz CMOS & MEMS integration approaches: - Multi-Chips integration: MCM packaging - Monolithic integration: CMOS-MEMS - Multi-Wafer integration: Wafer bonding & WLP Basic skill sets CMOS/MEMS integration: -Essential elements - Bonding technology - Deep-Si machining - Standard cells - Summary of the integration paths Manufacturing challenge of Application-Specific MEMS : - Sensor domain: Si-Microphone, accelerometer - RF integrated passives - Silicon optical bench Conclusion remarks P. 9

10 Bonding Technology 8 Electro-plating Eutectic CD:100um Bonding media 8 Electro-plating Eutectic CD:50um 8 photo-patterned adhesive CD:100um 8 Screen-print Glass frit CD:500um 8 Screen-print Glass frit CD:300um 8 Thin-film Eutectic CD:100um Bonding process Inspection/ Testing W2W (8 )-Thermal /compression />1Hr W2W (8 )-Thermal /compression /<0.8Hr W2W (8 ) -Localize heating /<0.5Hr C2B -Thermosonic C2W -Thermosonic SEM/C-SAM/X-ray/IR Shear test/ Stud-pull Leak test Available In-situ PCM P. 10

11 Deep-Si machining Point etch Surface etch Line etch Dynamic Structure Static Structure 4 /6 KOH (20+/-1 um) Diaphragm 6 ICP (4+/-0.4um) /Thin wafer 8 Grinding+ICP (100+/-3um) 8 KOH (20um+/-1) 8 Grinding + ICP (100+/-1um) Window Cap with eutectic bonding ring Cap wafer Cap with eutectic bonding ring 8 A/R> 10, Dim.<100um, pitch<200um TSV TSV Cap with eutectic bonding ring 8 A/R> 20, Dim.<50um, pitch<100um 8 A/R> 30, Dim.<30um, pitch<60um 6 THK 50um / CD 40um 8 THK 40um / CD 30um 8 A/R> 10, CD.<10um, pitch<20um 8 A/R> 15, CD.<5um, pitch<10um THK 100um / CD 80um Torsionspring 4 THK 40um / CD 40um Bendingspring/ Comb Available P. 11

12 Sensing Standard cells (Sensing and Actuation) Piezo-resistor Capacitance 4 PZR 6 out-of-plane (parallel-plate) Actuation 8 in-plane (comb) 8 out-of-plane (comb) 8 in-plane (comb) Electro-static Electromagnetic 8 PZR 6 PZR 8 out-of-plane (comb) 4 move-coil 6 move-coil 8 move-coil move-magnetic Electro- thermal 8 in-plane (bimorph) Available P. 12

13 tmt s IC & MEMS WLP - integration paths Cap wafer/ Smart substrate Cap wafer Window Cap wafer Window TSV Cap wafer TSV Cap wafer High A/R structure for sensing and actuation MEMS wafer Smart substrate Bulk micromachined structure Active device CMOS/ Bi-CMOS/BCD CMOS/ MEMS Discrete Device: LED/LD/HBT Bonding technologies Wafer to Wafer Chip to wafer Chip to board Final packaging Applications Traditional packaging Sensors Ex: Cavity/Hermetic packaging Display Others SiOB IPD Cap MEMS CMOS LEDs/ LD / Drive IC SiOB Standard PKG P. 13

14 Outline Foundry aspect of MEMS Biz CMOS & MEMS integration approaches: - Multi-Chips integration: MCM packaging - Monolithic integration: CMOS-MEMS - Multi-Wafer integration: Wafer bonding & WLP Basic skill sets CMOS/MEMS integration: -Essential elements - Bonding technology - Deep-Si machining - Standard cells - Summary of the integration paths Manufacturing challenge of Application-Specific MEMS : - Sensor domain: Si-Microphone, accelerometer - RF integrated passives - Silicon optical bench Conclusion remarks P. 14

15 MEMS market info. Source: Yole development P. 15

16 Capping on CMOS wafer ADI/ADXL330 Capping wafer bond on MEMS/BiCMOS wafer Bonding by Pb doped glass frit material Bonding line width: 200um Source: Chipworks P. 16

17 Capping on pure MEMS wafer ST Micro/ Robert Bosch/ Kionix. Capping wafer bond on pure MEMS wafer Bonding by glass frit material Bonding line width: um Source: Chipworks P. 17

18 Bonding for final packaging P. 18

19 Si-Mic.: The integration approaches Si-Mic. IC MEMS PKG < 0.04USD < 0.05USD >0.1USD Multi-chips integration: - Only for large signal MEMS - Need special PKG (Knowles) ASP: 0.4USD IC/MEMS monolithic: MEMS/PKG monolithic: - Direct interconnection - Need special PKG - Low noise Flip-chip bonding - Easy to PKG (Akustica) (SonionMEMS) P. 19

20 Other challenge of Si-MiC packaging Diaphragm on top or backplate on top configuration P. 20

21 Outline Foundry aspect of MEMS Biz CMOS & MEMS integration approaches: - Multi-Chips integration: MCM packaging - Monolithic integration: CMOS-MEMS - Multi-Wafer integration: Wafer bonding & WLP Basic skill sets CMOS/MEMS integration: -Essential elements - Bonding technology - Deep-Si machining - Standard cells - Summary of the integration paths Manufacturing challenge of Application-Specific MEMS : - Sensor domain: Si-Microphone, accelerometer - RF integrated passives - Silicon optical bench Conclusion remarks P. 21

22 Alternatives of Passive Components Passive Components Discrete Integrated/Embedded (SMD) Embedded into organic board Embedded into ceramic substrate (Laminate) (LTCC) Fabrication as Thin Film on Silicon/Glass wafer Integrated into IC (AIC) (IPD-LC-G) P. 22

23 Benefits of Thin Film Tech. Cost Saving Cheaper than GaAs/SiGe substrate Module size shrinking Form factor and profile are shrank RF performance enhancing Precise L/C High Q Loss reduction Reduce I/O number Less external wiring P. 23

24 Structure of IPD-LC-G (tmt) tmt's IPD-LC-G is a pure passive process. It is targeted at high performance, small size passive-only circuits and utilized over 10um of copper metal. High-Q inductors, high-density MIM capacitors and interconnections are available with thin glass substrate. The IPD-LC-G process is available on 200-mm (8 inch) wafers! P. 24

25 Advantages of Thin film IPD: Precision Measurement data highly match to design & simulations! Customers can reduce the cycle time & cost of design! P. 25

26 Design Kits and Tools (Post NDA) A. Design rules (PDF.) B. Reference kits (PDF./ web base) P. 26

27 Service Sets Shuttle service Prototyping Service Shared mask Periodic run Hot lot cycle time DC/RF testing offering Customer-specific masks and schedule 2 wafers delivered Mass production service Quantity>100 pcs/month Contract manufacturing P. 27

28 Outline Foundry aspect of MEMS Biz CMOS & MEMS integration approaches: - Multi-Chips integration: MCM packaging - Monolithic integration: CMOS-MEMS - Multi-Wafer integration: Wafer bonding & WLP Basic skill sets CMOS/MEMS integration: -Essential elements - Bonding technology - Deep-Si machining - Standard cells - Summary of the integration paths Manufacturing challenge of Application-Specific MEMS : - Sensor domain: Si-Microphone, accelerometer - RF integrated passives - Silicon optical bench Conclusion remarks P. 28

29 Si optical bench for Solid state lighting Low Rth- Si-substrate - High thermal conductivity (Si:K>150 C-m/W), low thickness (250um min.) EZ-dispensing - Precision ring, well defined Phosphor gel shape, improve the color uniformity Precision-cavity - 5um X,Y,Z accuracy, max depth 400um, improve the die bonding accuracy, and reflect the side-light. Bright- mirror coating - >90% reflectivity of thin film mirror coating U-bond - Thin film eutectic bonding pad ( Au or Au/Sn alloy), improve Die bond quality and reduce Rth. Thin-isolation - Electrical isolation by a thin, integrity oxide film (<1um, BV>50V), contribute small Rth(< 0.3C/W). Multi-interconnector - Chip to substrate wire bonding, chip to chip interconnect by metal pattern, improve reliability. polymer ring PCB P. 29

30 SEM of Si optical bench P. 30

31 Application : washer of standard emitter Low Rth- Si-substrate - High thermal conductivity (Si:K>150 C-m/W), low thickness (250um min.) EZ-dispensing - Precision ring, well defined Phosphor gel shape, improve the color uniformity Bright- mirror coating - >90% reflectivity of thin film mirror coating Thin-isolation - Electrical isolation by a thin, integrity oxide film (<1um, BV>50V), contribute small Rth(< 0.3C/W). chip 5.5mm 1mm 8mm Precision ring (arbitrary shape) 2mm 3+/-0.1mm P. 31

32 CCT U% comparison EZ-dispensing - Well-defined phosphor gel shape, reduce the difference of light travel distance - ΔCCT could be reduce to 1/3. Standard emitter Emitter with OPS Conformal like gal dispensing, uniform blue light travel distance Different blue light travel distance of standard emitter (CCT) (CCT) ΔCCT> ΔCCT< (off-axis angle, deg) (off-axis angle, deg) P. 32

33 Conclusion remarksthe potential advantages and challenges of WLP Potential advantages: Lower cost - Decouple MEMS & IC process: faster to develop. - Batch packaging/testing process: dramatic cost reduction for small die size product. Smaller form factor - For mobile applications. - Small foot print and thin. Limitations and Challenges: Over all - Hard to define the technology roadmap: MEMS rule> one product, one process, one packaging. - But, there still have two essential technologies of WLP: DRIE and bonding. DRIE - We need to have clear picture of the equipment/process technology roadmap. - We need to continue improving E/R, A/R and U%. Bonding: - Wafer bonding is still a low throughput process. - Limited bonding media due to the process compatibility and reliability. - Combined yield problem. Thanks for your attention, and please request the detail foundry service through the tmt website: P. 33