OPTIMIZATION OF ULTRA-THIN BODY, FULLY- DEPLETED-SOI DEVICE, WITH RAISED SOURCE/DRAIN OR RAISED EXTENSION

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1 OPTIMIZATION OF ULTRA-THIN BODY, FULLY- DEPLETED-SOI DEVICE, WITH RAISED SOURCE/DRAIN OR RAISED EXTENSION J. L. (Skip) Egley 1, Anne Vandooren 2, Brian Winstead 3, Eric Verret 3, Bruce White 2, Bich-Yen Nguyen 2 1 Advanced Product Research & Development Lab, Motorola Inc. Tempe, AZ Advanced Product Research & Development Lab, Motorola Inc. Austin, TX Front End Technology Simulation, Motorola Inc. Austin, TX Abstract. Raised source/drain (S/D) or raised extension in fully depleted SOI (FDSOI) is necessary to boost saturation current, because of increased resistance from the very thin film. We demonstrate that the choice, of raising the extension versus the S/D, will depend upon the maximum achievable mobility in the structure at a 60 nm physical gate length. INTRODUCTION We report on an ultra-thin body, fully depleted SOI device (FDSOI), with metal gate, raised source/drain or raised extension, and its structural optimization via simulation. Successful fabrication of a long channel device of this nature was recently reported in (1). The physical gate length is 60 nm, the film thickness under the gate is 10 nm, and is undoped. The gate electrode is mid-gap, i.e., a workfunction of 4.6 ev. The source and drain regions are constant doping. The overlap region possesses a Gaussian profile with a junction depth defined as the point at which the doping concentration drops to cm -3, which was 3 nm overlap in this case. Hydrodynamic simulations for capturing velocity overshoot were employed, with an energy relaxation time of 0.3 ps, and predicted I Dsat was checked with Monte Carlo (2,3). Silicide resistivity is also included via a distributed resistance on the S/D contacts (4). The mobility model is from (5). CV/I (speed of an unloaded device) is used as the criterion for optimization, as this parameter trends well with the speed of an inverter (6). Simulations include quantum effects via density-gradient (7) for the continuum solver, while Monte Carlo uses Schrodinger s equation for quantization. Throughout this paper we refer to raised S/D and epi after spacer interchangeably, as well as raised extension and epi before spacer.

2 DISCUSSION Figure 1 displays the simulated structure for the continuum solver, and defines the various geometrical properties of the device. Figure 1. a) the basic structure starts with a lightly doped substrate (~ 5 x cm -3 p-type), followed by a 50 nm buried oxide (BOX) and a 10 nm thin film of silicon (undoped). An epi of various thickness is deposited outside of the gate and liner (this particular picture shows the epi before spacer, or raised extension). Silicide consumes approximately 20 nm of the silicon outside the spacer, hence the notch in the S/D contacts. The S/D and extension regions are constant doped at various levels, and the overlap is a Gaussian profile, with junction defined as the point at which the doping drops to cm -3, b) is a zoom of the gate region. There is a thin layer of SiO 2 (too thin to see) 0.5 nm thick, and a layer of high-k material (5 nm), to give an equivalent oxide thickness of 1.5 nm. The relative dielectric constant of the high-k was taken to be 20. The Monte Carlo structure was essentially as in b), but truncated vertically at the spacer edge, with the S/D contacts running from the bottom of the spacer to the BOX. The geometrical parameters ranged from 5 25 nm for the liner, and nm for the epi thickness. The doping concentration took on values of 9 x 10 19, 1 x 10 20, and 2 x cm -3. The S/D silicide contact resistance was 2.4 x 10-8 Ω-cm 2 (for NMOS) and 2.6 x 10-8 Ω-cm 2 (for PMOS),, which corresponds to cobalt silicide at 5 x cm -3 (4). The doping around the silicide (1.5 nm out from the contact line) was set to 5 x cm -3 to include the effects from the increased doping near the contact. 2. The equivalent structure for the epi after spacer, or raised S/D, is shown in Figure

3 Figure 2. A zoom around the gate region of the epi after spacer structure. The raised S/D is clearly visible outside of the spacer. The deposited epi thickness was 40 nm, approximately half of which is consumed by silicide. RESULTS We present the results for the NMOS device first. Figure 3 displays the speed (CV/I) for the raised extension process, and Figure 4 is for the raised S/D with a 5 nm liner. Figure 3: Speed of the raised extension NMOS device (as illustrated in Figure 1). There are 3 sets of data for liner thickness, as indicated at the bottom (5, 15, and 25 nm). Each set had epi thicknesses of 10, 20, 40, or 60 nm as indicated inside the white boxes in the bars. The S/D doping densities are indicated by patterns, as shown in the legend.

4 Figure 4: Speed of NMOS for the raised S/D device with a 5 nm liner. Epi thicknesses, as well as S/D doping concentration are indicated identically as in Figure 3. The 5 nm liner case is the only one shown because the others scale inversely with the decrease in I DSat. In contrast to the epi before spacer deposition, in general, it can be said that the speed for this structure is dominated by the saturation current. Note the different scales for Figures 3 and 4. The fastest device between these structures is the raised S/D (Figure 4 results) with a 60 nm epi and doping of 2 x cm -3. This is in spite of the fact that the saturation current for this device is lower that that of the fastest device with a raised extension. The mobility is high enough, that the increased capacitance from the raised extension is playing a bigger role. The PMOS results are shown in Figure 5 for the raised extension, and Figure 6 for the raised S/D. The geometrical and doping parameters were varied in identical fashion as in the NMOS case.

5 Figure 5: Speed of PMOS for different epi and liner thicknesses, for the raised extension device (as illustrated in Figure 1). The thicknesses and doping concentrations are indicated in the same way as Figures 3 and 4 for NMOS. Figure 6: Speed of PMOS for the raised S/D device with a 5 nm liner. Epi thicknesses, as well as S/D doping concentration are indicated identically as above. The 5 nm liner case is the only one shown, because the others scale inversely with the decrease in I Dsat with increasing liner thickness. Note the different scales for Figures 5 and 6.

6 CONCLUSIONS The fastest PMOS structure is a raised extension device, while it is a raised S/D device for NMOS. There are only two differences between N and P as far as the continuum solver is concerned, mobility and effective mass. There is a slight dependence on effective mass in the density gradient for quantization (6), hence, indirectly an effect on capacitance. However, a plot of CV versus epi thickness is very much linearly proportional to epi thickness in the raised extension case, and constant in the raised S/D as would be expected. And the values are nearly identical for NMOS & PMOS, making the differences in CV minimal. The mobility disparity between electrons and holes is approximately a factor of two. Therefore, the final arbiter between the competing device geometries will be the obtainable mobility. These simulations assumed SiO 2 like mobilities in using (5). If a high-k insulator were used, on the other hand, then from indications so far of lower mobilities in high-k, the better choice may be to pursue the highest possible saturation current, which means the raised extension. There are, however, other caveats, which require mention. For the simplified structure mentioned in Figure 1b, MOCA (2,3) predicts a factor of two higher saturation current than the continuum solver employing the mobility of (5). Both reproduce the universal mobility curve (see 3 in the case of MOCA), yet in the case of very short channel lengths we have seen this discrepancy before in bulk simulation. The cause has not been determined, but the tendency is to trust the Monte Carlo simulations, with its better physics, and to adjust parameters in the mobility model. The chip temperature will certainly be higher than room temperature, as assumed here, which also has profound effects on mobility. However, the saturation current is dominated by surface roughness scattering, which does not have a temperature dependence in the models used here. If we assume that the MOCA I DSat is correct, and that the mobility parameters need adjusting to obtain a factor of two higher saturation current, it seems likely that the raised S/D would be the better candidate, and most likely for both NMOS and PMOS, at least for an SiO 2 -like gate. Since the high-k materials affect the mobility by very different amounts (but all appear to decrease it so far), it s not possible to say much about the optimal structure without knowing which material system is the final choice. REFERENCES 1.Vandooren et al, SOI Conf. 2002, pg A. Duncan, Ph. D. Dissertation, Univ. of Illinois, B. Winstead, Ph. D. Dissertation, Univ. of Illinois, Varahramyan and Verret, Solid-State Electronics, 39, pg. 1601, (1996). 5. Darwish et al, IEEE Trans. Elec. Dev., 44, 1529 (1997). 6. E. J. Nowak, IBM J. Res. & Dev., Vol. 46, No. 2/3, March/May Mario G. Ancona, IEEE Trans. Elec. Dev., 47, 1449 (2000).