Abstract. 1. Introduction. 2. Device Variation

Transcription

1 Device Variation and Its Influences on the LTPS TFT Circuits Ya-Hsiang Tai Department of Photonics & Display Institute, National Chiao Tung Univ., Hsinchu 300, Taiwan, R. O. C. Telephone: , Abstract At present, low temperature polycrystalline silicon (LTPS) tihn-film transistor (TFT) is the best candidate to realize system-on-panel (SoP). However, due to the grain structures, the behaviors of the LTPS TFTs are different, which is not yet be totally eliminated. In this paper, the simulation skills and circuit design to deal with the variation are also discussed. 1. Introduction Low temperature polycrystalline silicon(ltps) thin film transistors (TFTs) have attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) [1]-[4]. The significant advantages over amorphous silicon TFTs are in the higher driving current and better reliability. In poly-si TFT-controlled displays, poly-si TFT is used to implement pixel circuit and driving circuit on a single glass substrate to reduce system cost and posses compact module. One of the most promising approaches is to use excimer laser to recrystallize amorphous silicon, the poly-si TFTs can have very high performance. However, the resulting poly-si TFTs have poor uniformity and suffer from huge variations due to the narrow laser process window for producing large-grained poly-si thin film. The fluctuation of pulse-to-pulse laser energy and non-uniform laser beam profile make laser energy density hard to hit the super lateral growth regime everywhere. The random grain boundaries and trap density existing in the channel region [5]-[6]. This will lead to many problems in real product applications such as non-uniform brightness in panel, error reading in digital circuit, current gain mismatching in analogue circuit etc. Therefore, any circuit to be practicable, device-to-device uniformity must be controlled. It would be useful if a theory existed to quantify this variation [7]. In this paper, the device variation is described. Its Influences on the LTPS TFT circuits the simulation skills and circuit design to deal with the variation are also discussed. 2. Device Variation 2.1 Glance at the variation The lot trend and the distribution of the threshold voltage (Vth) at different sites for an LTPS TFT fabrication line are plotted in Fig. 1 and, respectively. There is no significant difference among the different sites, which depicts the non-uniformity arisen from regional changing factors such as thickness, doping, and critical dimension loss is less important than the non-reproducibility. Furthermore, the Vth deviation among the sites on the same glass is close to the overall deviation of all the devices. It reveals the dominate factors of the device variation can happen even with the nominally identical process, which should be related to the grain structures in the channel region. On the other hand, The Vth distribution is not symmetry and thus not in a Gaussian way. The tail of the Vth distribution stretches toward more positive and is not negligible. It results in the difficult dilemma of design for performance or for manufacturing yield. Average + 4σ Average + 3σ Average + 2σ Average + σ Average Average - σ 60% 50% 40% 30% 20% 10% 0% Average - 2σ Average - σ Average Threshold Voltage Threshold Voltage Average + σ Average + 2σ Average +3σ Average +4σ Site A Site B Site C Site D Site E Site F Site G Site H All Site A Site B Site C Site D Site E Site F Site G Site H Fig. 1. Site variation for an LTPS TFT fabrication line plotted in the format of lot trend and distribution In addition the Vth, other device parameters such as mobility and subthreshold swing will also be different from device to device, which makes the works of device modeling and circuit design even worse. 2.2 Matching devices The matching devices are widely applied in many circuits such as differential pairs. For matching LTPS TFTs, they are even used as a compensation technique for AMOLED pixel and analogue buffer circuits [1]-[4]. It is believed that TFTs in pairs placed very closely in the matching configuration will have identical characteristics. However, the micro variation in the grain structures can still make the discrimination between the two TFTs. The laser scanning direction can affect the grain structures [8]. Therefore, the matching pairs with their channels perpendicular or parallel to the long axis of the laser beam are compared with those of interdigitated arrangement. The dependences of threshold voltage mismatch factor on the active areas for LTPS TFT pairs are shown in Fig. 2. The mismatching factor of a pair is defined as the difference divided by the average absolute

2 value. grain structure after excimer laser irradiation is polygon-like but not stripe-like. The corresponding grain boundaries with the current flow are randomly located in the channel. The occurrence of grain boundaries is random and the defect density is difficult to control in each device even with well process control. Optimized design of the device layout can somehow reduce the variation of matching LTPS TFTs. 2.3 Temperature dependence 100% N type Mobility / Max(Mobility) 90% Temperature ( o C) 100% Mobility / Max(Mobility) P type 90% Temperature ( o C) (c) Fig. 2. The dependence of threshold voltage mobility and (c) subthreshold swing mismatch factors on the active areas for LTPS TFTs fabricated with different laser scan directions The worst mismatching factor is around 0.2 (20% mismatch) in device characteristics, and the usual mismatching factor is around 0.05 (5% mismatch) in device characteristics. It is observed that interdigitated arrangement has less area dependence than the perpendicular and the parallel ones. The large mismatch for the small area TFTs is consistent with the micro variation attributed to the grain distribution. As for the large area ones, no systematic trend is present in both perpendicular and parallel arrangement. This is because the Fig. 3. Many temperature dependences of the effective mobility for n-type and p-type LTPS TFTs Many n-type and p-type LTPS TFTs are measured at elevated temperatures. The effective mobility calculated from the maximum transconductance is extracted. The relative ratios are plotted in Fig. 3. The dependence trends for the n-type and p-type TFTs are firstly noticed. The dominant transport mechanisms for the electrons and holes are Coulomb and lattice scattering, respectively [9]. The larger number of free electrons results in the increase of mobility at higher temperatures. The decrease of the hole mobility at risen temperatures is attributed to the more significant lattice scattering. Furthermore, the variant range at the different temperatures can reconfirm the explanations. For the n-type TFTs, the variant range of the mobility is unchanging over the temperatures. The temperature less influences the charged defects, and the trap charges in the grain boundaries are divergent from device to device. On the other hand, for the p-type TFTs, the not only the variant range but also the variant ratio to its average value decrease with the temperature. It is explained by the similar lattice structures in the grains and the lattice scattering prevailing over the Coulomb one at higher temperature.

3 The temperature dependences for the devices are not exactly the same. It reveals the existence of other minor mechanisms. 2.4 Reliability Owing to the device variation, the LTPS TFTs behave diversely even under the same bias stress condition. Statistically, Fig. 4 presents the standard deviations among different devices under bias stress conditions of Vds = 20V and various Vgs. When Vgs = 10 V, the standard deviation is small. This is due to the small electric field near the drain side that creates much fewer hot carriers compared to the case for other bias stress conditions. Since the degradation is not severe, this explains why the variation is small. When Vgs = 12.5 V, the standard deviation is the largest under different stress times. This is because crystallized poly-si is generally full of weak Si-Si bonds and dangling bonds at grain boundaries. Furthermore, the hydrogenation process also creates a large amount of weak Si-H bonds in poly-si. These weak bonds can easily be broken under the device operation. The amount of grain boundaries existing in the channels of TFTs will result in the variation of device characteristics [10], [11]. However, performance of TFTs is limited by the amount of grain boundaries existing in the channel. When Vgs was increased to 15 V, these hot carriers near the drain side obtained enough energy to break not only weak Si-Si and Si-H bonds but nearly all of the Si-Si and Si-H bonds at grain boundaries. Hence, the variation under this condition was less than Vgs = 12.5 V. As the stress time was increased, most bonds at grain boundaries were broken so that the standard deviation decreased. When Vgs = 17.5 V, the standard deviation decreased then increased. This phenomenon may be due to the fact that holes inject into the buffer oxide, causing the short-channel effect [12], [13]. When Vgs = 20 V, the standard deviation was the smallest because the electric field in the channel under this condition was weak and the degradation was not severe. Standard Deviation of Mobility Ratio Vg=10 V Vg=12.5 V Vg=15 V Vg=17.5 V Vg=20 V Stress Time (sec) Fig. 4. Standard deviations of the mobility ratio of poly-si TFTs under different stress conditions 3. Influences on Circuits The concept for the design of TFT circuits requires to be reconsidered from the view point of device variation. In this section, the simulation skill and the concept of compensation are discussed. 3.1 Simulation skill If the characteristics of devices vary together, the corner models will be used in the simulation to evaluate the circuit performance at extreme cases. This simulation can properly reflect both the working ranges for the circuit and the requirements for the process control. However, only considering the extreme cases, this method might overstretch the operating range prediction for the circuit performance. Instead, Monte Carlo method may be better used to estimate the circuit performance of LTPS TFT circuit For example, a 20-stage shift register with VDD=3.3V operating at 10, 11, and 12MHz are simulated with Monte Carlo method for 100 times, which assuming the threshold voltage and mobility of the TFTs randomly distribute in a Gaussian way. The simulated output waveforms and the power distribution at 10MHz are shown in Fig. 5. The output failure can be identified by the V 0 and V 1 indicated in Fig. 5. The high voltage of V 0 and the low V 1 correspond to two types of the yield loss, which are indicated by LV 1 and HV 0, respectively. The 20th stage of output waveform in Fig. 5 has obvious variation. The distribution of power in Fig. 5 shows normal distribution, which is correspond to the assumption. 20th stage of output waveform (V) 4 V V 0 2.1u 2.2u 2.3u Time (us) Distribution of Power u 18.4u 18.8u 19.2u Power(uW) 20 stages Fig. 5. Results of 20 stages Monte Carlo simulation for 100 times of output waveform power distribution. Nevertheless, the Monte Carlo method suffers from too much time consumption. A new method to reduce the simulation time is important. We try to use the simulation results of 3-stage shift register to approximate those for the 20-stages one. Table I. Failure rate estimation for 20-stage Shift Register Failure Rate 10M 11M 12M Remark HV0MC3 1% 2% 5% 3-stage Monte Carlo LV1MC3 3% 10% 19% HV0E20 9% 17% 37% 1- [ 1- (HV0MC3 ) 9 ] LV1E20 24% 61% 85% 1- [ 1- (LV1MC3 ) 9 ] HV0MC20 3% 6% 7% 20-stage Monte Carlo LV1MC20 17% 61% 90% ERROR HV0 6% 11% 30% HV0MC3 - HV0MC20 ERROR LV1 7% 0% -5% LV1MC3 - LV1MC20 The failure rate of shift register circuit from 3 stages to 20 stages can be calculated by 1- [1- (LV 0 MC3) n ] and 1- [1- (LV 1 MC3) n ] which are correspond to two types of the yield loss of LV 1 and HV 0, where n= (N/2-1) and N is the number of stages, respectively. Table I shows the estimating results of 20-stage shift register. According to the proposed equation, the prediction error of LV 1 is lower than 10%. The same circuit is also simulated with the worst, typical, and best model. The typical, fast and slow operation frequencies of the shift register exceed 10MHz, 22.2MHz, and 3.2MHz, correspondingly. The best case of 22.2MHz seems to overestimate the upper limit in operating frequency, comparing

4 to the results of Monte Carlo simulation indicating the high failure rate at 12MHz. On the other hand, the worst case of 3.2MHz might be too conservative to operate the circuit. Furthermore, the corner simulation does not reveal information about the stage number of shift register, namely, the complexity of circuit. To design for production yield, the Monte Carlo simulation can provide better estimation than the corner method. Unfortunately, the difference between the TFT characteristic in the test keys and really within a circuit is obstructed by the device variation. Thus, the systematic correspondence between simulation result and the real product performance is yet to be established. device variation. 3.2 Circuits with compensation The device variation can directly affect the circuit performance, especially in the application of display products. For examples, in the pixel circuits of AMOLEDs and the output buffers of flat panel display column drivers, the variation will cause the real output voltage not the target value and lead to the wrong gray scale and results in the bad uniformity. Among the circuits, source follower consisted of one transistor is the simplest one, as shown in Fig. 6. Fig. 8. Simulation results of the source follower in Fig. 7. with an active load when input voltage 4V and 6V Cvt S3 Vbias S1 S2 S4 Fig. 6. The conventional source follower, output waveform simulation results S1 S2 S3 S4 Fig. 9. The proposed analogue buffer and its timing diagram, Simulation results of the proposed analogue buffer when input voltage 4V to 6V Vbias Fig. 7. The conventional source follower, output waveform simulation results It is observed that the final output voltage is not kept constant, but exceeds the value of V GS -Vt expected in principle. It is ascribed to the sub-threshold current. Consequently, it is will be sensitive to the charging time for various product specification. An active load shown in Fig. 7 is added to eliminate this phenomenon. It is distinct that unsaturated phenomenon of the output voltage is suppressed. Fig. 8 shows the simulation results of the conventional source follower with active load when input voltage 4V and 6V. It is clear that the circuit suffers from huge variations and output voltage is not due to the TFTs variation. Therefore, a new analogue buffer must be proposed for the compensation of the Fig. 10. Standard deviation of output voltage in the analogue buffer in Fig. 9 with compensation and that in Fig. 7 Fig. 9 shows a schematic of a newly proposed analogue buffer. It consists of two transistors, a capacitor, and four switches. The operating principles are as follows. The gate voltage of the TFTs as the active load is biased at Vbias. During first operating period, S1 and S2 are turned on sequentially, and S3 and S4 are turned off. There by, a constant-current voltage corresponding to the threshold voltage of driving TFT is stored in Cvt. During second operating period, S3 and S4 are turned

5 on and S1 and S2 are turned off, then the voltage at the gate of the driving TFT is hold. Thus, the output voltage is compensated by the voltage stored in Cvt. Fig. 9 shows that the output voltage variation of the new type source follower. Compared to Fig 8, the output voltage variation decreases drastically. Fig. 10 shows the standard deviation of output voltage in the proposed analogue buffer with compensation and the source follower in Fig. 7 with active load calculated from the Monte Carlo simulation results. The former has tighter distribution and less dependence of. For such a simple circuit, to compensate the large leakage and wide Vth variation of the TFT, one bias TFT, four switch TFTs, and one capacitor are added to a simple circuit. Moreover, the circuit operation becomes more complicate by inserting a period of compensation. Similar concepts are also applied to the AMOLED pixel circuits. The spatial limit within the fine pitch of pixels and the current-dependent brightness make the design even more difficult. This leads to a driving force to further reduce the variation of the TFTs. 4 Conclusions The device variations of TFTs in the initial state, the elevated temperatures, and after bias stress are profiled. The simulation skills and compensating concept of the circuit design to deal with the variation are demonstrated. 5. Acknowledgement The author would like to thank the Toppoly Optoelectronics Corp. for their technical support. This work has been sponsored by the National Science Council, Republic of China. (NSC E ). The application support of software from Cadence Design Systems is also acknowledged. 6. References [1] Y. W. Kim, S. R. Lee, O. K. Kwon, K. N. Kim, Y. S. Park, S. A. Yang, D. Y. Shin, B. H. Kim, and H. K. Chung, EURODISPLAY, pp , (2002) [2] S. H. Jung, J. H. Park, C. W. Han, and M. K. Han, SID Tech. Dig., pp , (2004) [3] S. H. Jung, W. J. Nam, and M. K. Han, IEEE Electron Device Lett., vol.25, pp , (2004) [4] T. Sasaoka, M. Sekiya, A. Yumoto, J. Yamada, T. Hirano, Y. Iwase, T. Yamada, T. Ishibashi, T. Mori, M. Asano, S. Tamura, and T. Urabe, SID Tech. Dig., pp , (2001) [5] G. A. Bhat, H. S. Kowk, and M. Wong, Solid-State Electron., vol. 44, pp , (2000) [6] V. W. C. Chan, P. C. H. Chan, and C. Yin, IEEE Electron Devices, vol.49, pp , (2002) [7] A. W. Wang, and K. C. Saraswat, IEEE Electron Devices, vol.47, pp , (2000) [8] K. Yoneda, Y. Segawa, T. Yamada, K. Kihara, and R. Yokoyama, Proceedings of the 17th Annual IDRC, pp. L1-L4, (1997) [9] H. Mori, K. Hata, T. Hsahimoto, I.-W. Wu, A. G. Lewis, and M. Koyanagi, Jap. J. Appl. Phys., vol. 30, No. 12B, pp [10] M. Hack, A. G. Lewis, and I.-W. Wu, IEEE Trans. Electron Devices, vol. 40, pp , (1993) [11] I.-W. Wu, W. B. Jackson, T.-Y. Huang, A. G. Lewis, and A. Chiang, IEEE Electron Device Lett., vol. 11, pp , (1990) [12] W.-Y. Guo, C.-Y. Meng, A. Shih and Y.-M. Tsai, SID Tech. Dig., pp. 1 4 (2003) [13] K. M. Chang, Y. H. Chung, and G. M. Lin, IEEE Electron Device Lett., vol. 23, pp , (2002)