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2 4.1 CHAPTER OBJECTIVES 1. Introduce the CMOS designer to the technology that is responsible for the semiconductor devices that might be designed 2. Understanding the potential and limitations of a given technology. 3. Gives some background for the geometric design rules that are the interface medium between designer and fabricator Samir kamal Spring 2018

3 - We know the transistor structure and the main color legend shown Fig. LCC. Fig. LCC Layout color code. Samir kamal Spring 2018

4 - Remember as already discussed in the introduction, the VLSI technology can be concluded as shown in Fig. VLST. Fig. VLST VLSI technology Tree. Samir kamal Spring 2018

5 4.2 SILICON SEMICONDUCTOR TECHNOLOGY - Silicon in its pure (intrinsic) state is a semiconductor, having a bulk electrical resistance somewhere between that of a conductor and an insulator. - The conductivity of silicon can be varied by introducing impurity atoms into the silicon crystal lattice. - These dopants or impurities may supply free el s / ho s (donor / acceptor elements). - Silicon that contains a majority of donors is known as n- type [phosphorous and arsenic are commonly used to create donor silicon]. Samir kamal Spring 2018

6 SILICON SEMICONDUCTOR TECHNOLOGY Cont Silicon that contains a majority of acceptors is known as p-type. [Boron is frequently used to create acceptor silicon]. - When n-type and p-type materials are brought together they produce a junction, PN junction. - By arranging junctions in certain physical structures and combining these with other physical structures, various semiconductor devices may be constructed. Samir kamal Spring 2018

7 4.2.1 Wafer Processing - The basic raw material in modern semiconductor plants is a wafer, disk or circular sheet of single-crystal silicon (The diameter = 6", 8", 10" or 12", thickness = mm). - Wafers are cut from ingots that result from converting sand into pure silicon through sophisticated chemical processes. - Slicing ingots into wafers is carried out using cutting-edge diamond blades and polish one face to a flat, scratch-free mirror finish. - The technology of wafer processing is beyond the scope of this course. Samir kamal Spring 2018

8 - The ingots of single-crystal silicon that have been pulled from a crucible melt of pure molten polycrystalline silicon. - This is known as the Czochralski, method (Fig. 4.1) and is currently the most common method for producing singlecrystal material. - The diameter of the ingot is determined by the seed withdrawal rate and the seed rotation rate. Growth rates range from 30 to 180 mm/hour. Samir kamal Spring 2018

9 Fig. 2.1 Czochralski method for manufacturing silicon ingots. Samir kamal Spring 2018

10 4.2.2 Manufacturing Process - Many of the structures and manufacturing techniques used to make silicon integrated circuits depends on the properties of the oxide of silicon properties. - These techniques or properties include: Oxidation, Epitaxy, Deposition, Ion-Implantation, and Diffusion (Refer to Fig.4.2). Samir kamal Spring 2018

11 Fig. 2.2 An nmos transistor showing the growth of field oxide below the silicon surface Samir kamal Spring 2018

12 A- Oxidation - Manufacture of silicon dioxide (SiO2) is very important. - Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere such as oxygen or water vapor. - The two common approaches are: * Wet oxidation: when the oxidizing atmosphere contains water vapor. The temperature is usually between 900 C and me 1000 c. This is a rapid process * Dry oxidation: when the oxidizing atmosphere is pure oxygen. Temperatures are in the region of 1200 C, to achieve an acceptable growth rate Samir kamal Spring 2018

13 B- Epitaxy, Deposition, Ion-Implantation, and Diffusion B1- Epitaxy: Epitaxy involves growing a single-crystal film on the silicon wafer by subjecting the silicon wafer surface to elevated temperature and a source of dopant material. B2- Deposition: Deposition might involve evaporating dopant material onto the silicon surface followed by a thermal cycle, which is used to drive the impurities from the surface of the silicon into the bulk. Samir kamal Spring 2018

14 B3- Ion-Implantation and Diffusion : - Ion implantation and diffusion involves subjecting the silicon substrate to highly energized donor or acceptor atoms, which travel below the surface of the silicon, forming regions with varying doping concentrations. - At any elevated temperature (> 800 C) diffusion will occur between any silicon that has differing densities of impurities. - Diffusion occurs from areas of high concentration to areas of low concentration. - It is important once the doped areas have been put in place to keep the remaining process steps at as low a temperature as possible. Samir kamal Spring 2018

15 Manufacturing process can be concluded as shown in this table. Samir kamal Spring 2018

16 How you can control this process: - Construction of transistors and other structures of interest depends on the ability to control where and how many and what type of impurities are introduced into the silicon surface. - What types of impurities are introduced is controlled by the dopant source. (Boron is used for creating acceptor silicon, while arsenic and phosphorous are used to create donor silicon). - How much is used is determined by the energy and time of the ion-implantation or the time and temperature of the deposition and diffusion step. Samir kamal Spring 2018

17 - Where it is used is determined by using special materials as masks. - In places covered by the mask ion-implantation does not occur or the dopant does not contact the silicon surface. - In areas where the mask is absent the implantation occurs, or the redeposit material is allowed to diffuse into the silicon. That is to say: Masks: are special materials used MOS processing. Masks function: They allow selective diffusion. - In places covered by the mask ion implantation does not occur. - In areas where the mask is absent the implantation occurs. Samir kamal Spring 2018

18 - As a conclusion the process control is defined as: Construction of any device other of interest depends on the ability to control where and how many and what type of impurities are introduced into the silicon surface. Samir kamal Spring 2018

19 - The common materials used as masks include: * Photoresist. * Polysilicon (polycrystalline silicon). * Silicon dioxide (SiO2). * Silicon nitride (SiN). - The ability of these materials to act as a barrier against doping impurities is a vital factor in this process, called selective diffusion. - The selective diffusion steps includes: * Patterning windows in a mask material on the surface of the wafer. * Subjecting exposed areas to a dopant source. * Removing any unrequited mask material. Samir kamal Spring 2018

20 Steps for patterning of silicon dioxide (SiO2) as shown in Fig a- Acid resistant coating (photoresist) spread evenly on surface. Note: The acid resistant coating is normally a photosensitive organic material called photoresist (PR), which can be polymerized by ultraviolet (UV) light. b- If the UV light is passed through a mask containing the desired pattern, the coating can be polymerized where the pattern is to appear. Note: Mask controls the exposed region. Samir kamal Spring 2018

21 Steps for patterning of SiO2 - Cont Fig. 2.3 Simplified steps involved in patterning of SiO2: (a) Bare silicon water; (b) Wafer with SiO2 and resist; Samir kamal Spring 2018

22 Steps for patterning of SiO2 - Cont c- The polymerized areas may be removed with an organic solvent. d- Etching of (removing) exposed SiO2 then may proceed. Note: - This is called a positive resist. - There are also negative resists where the unexposed PR is dissolved by the solvent. Samir kamal Spring 2018

23 Steps for patterning of SiO2 - Cont Fig. 2.3 Simplified steps involved in patterning of SiO2: (c) Exposing resist to UV light; and (d) Final etched SiO2; Samir kamal Spring 2018

24 Steps for patterning of SiO2 - Cont Fig. 2.3 Simplified steps involved in patterning of SiO2: (a) Bare silicon water; (b) Wafer with SiO2 and resist; (c) Exposing resist to UV light; and (d) Final etched SiO2. Samir kamal Spring 2018

25 Steps for patterning of SiO2 - Cont That is to say, steps of silicon patterning summarized as: a- PR is acid resist coating. b- UV light polymerizes the window which can be removed by organic solvent. c- Etching of SiO2. d- PR is dissolved by a solvent. Positive resist: Exposed photoresist removed. Negative resist: Unexposed photoresist removed. Samir kamal Spring 2018

26 Electron beam lithography (EBL) - In established processes using PRs in conjunction with UV light sources, diffraction around the edges of the mask patterns and alignment tolerances limit line widths to around 0.8 µm. - During recent years another way, electron beam lithography (EBL) is used for pattern generation and imaging where line widths of the order of 0.5 µm with good definition are achievable. Samir kamal Spring 2018

27 The main advantages of EBL pattern generation are as follows: * Patterns are derived directly from digital data. * There are no intermediate hardware images such as masks; that is, the process can be direct. * Different patterns may be accommodated in different sections of the wafer without difficulty. * Changes to patterns can be implemented quickly. The main disadvantage prevents using of EBL method commercially is: The cost of the equipment and the large amount of time required to access all points on the wafer. Samir kamal Spring 2018

28 4.3 SILICON GATE FABRICATION STEPS - Silicon may also be formed in a polycrystalline form (not having a single-crystalline structure) called Polysilicon. - This is used as an interconnect in silicon ICs and as the gate electrode on MOS transistors. - The reason of using Polysilicon as the gate electrode is its ability to be used as a further mask to allow precise definition of source and drain electrodes. - This is achieved with minimum gate-to-source/drain overlap, which improves circuit performance. - Figure 4.4 shows the processing steps of the silicon gate fabrication steps.

29 Silicon Gate Fabrication Steps - Cont - Patterning of SiO2 as shown in Fig. 4.3 and Fig. 4.4(a). - A thin, highly controlled layer of SiO2 is generated (gateoxide or thinox) and a thick layer of SiO2 to isolate the individual transistors (field oxide) Fig 4.4(b).

30 Silicon Gate Fabrication Steps - Cont - Polysilicon is deposited over the wafer surface and etched to form interconnections and transistor gates, Fig. 4.4(c). - The exposed gate oxide (not covered by poly) is etched and then exposed to a dopant source or is ion-implanted. Diffusion junctions form the drain and source of MOS transistor, Fig. 4.4(d).

31 Silicon Gate Fabrication Steps - Cont - The complete structure is covered by SiO2 and contact holes are etched, Fig. 4.4(e). - Aluminum or other metallic interconnect is etched to complete the final connection of elements, Fig. 4.4(f).

32 Silicon Gate Fabrication Steps - Cont Fig. 4.4 Fabrication steps for a silicon gate nmos transistor.

33 Other form - The wafer is covered with SiO2 with at least two different thicknesses, Fig. 4.4b. A thin, highly controlled layer of SiO2 is required where active transistors are desired. This is called the gate-oxide or thinox. A thick layer of SiO2 is required elsewhere to isolate the individual transistors. This is normally called the field oxide. - The exposed gate oxide (not covered by Polysilicon) is then etched and the wafer is then exposed to a dopant source or is ionimplanted, resulting in two actions (Fig. 4.4d). Diffusion junctions form the drain and source of the MOS transistor. They are formed only in regions where the poly silicon gate does not shadow the underlying substrate. This is referred to as a self-aligned process because the source and drain do not extend under the gate.

34 Parasitic transistors: Note that: - Parasitic MOS transistors exist between unrelated transistors, as shown in Fig The source and drain of the parasitic transistor are existing source/drains and the gate is a metal or Polysilicon interconnect overlapping the two S / D regions. - The gate-oxide is in the thick field oxide. - The threshold voltage of this transistor is much higher than that of a regular transistor. - This device is commonly called a field device.

35 Parasitic transistors - Cont Fig. 4.5 A parasitic MOS transistor or field device.

36 Parasitic transistors - Cont - The high threshold voltage is usually ensured by: Making the field oxide thick enough and introducing a channel-stop diffusion, which raises the impurity concentration in the substrate in areas where transistors are not required, thus further increasing the threshold voltage. - These devices do have some useful purposes where the fact that they turn on at voltages higher than normal operating voltages may be used to protect other circuitry.

37 [4] nmos transistors structure Fig. a nmos Transistor structure

38 4.4 BASIC CMOS TECHNOLOGY - CMOS is recognized as the leading VLSI systems technology, which provides lower power-delay product than other technologies (Bipolar, nmos, or GaAs, ). - The four main CMOS technologies are: * N-well process. * P-well process. * Twin-tub process. * Silicon on insulator.

39 BASIC CMOS TECHNOLOGY - Cont During the discussion of CMOS technologies, process cross-sections and layouts will be presented. - Figure 4.6 summarizes the drawing conventions.

40 BASIC CMOS TECHNOLOGY - Cont - 2 Fig. 4.6 CMOS process and layout drawing conventions.

41 4.4.1 n-well CMOS Process - Depending on the choice of starting material (substrate), CMOS processes can be identified as n- well, p-well, or twin-well processes. - The n-well is required wherever p-type MOSFETs are to be placed. - The typical process flow is as shown in Fig A minimum of seven masking layers are necessary.

42 n-well CMOS Process Cont - 1 The main masks used in n-well CMOS Process are: - Mask-1: Definition of the n-well diffusion - Mask-2: Definition of the active regions. - LOCOS oxidation - Mask-3: Polysilicon gate. - Mask-4: n+ diffusion. - Mask-5: p+ diffusion. - Mask-6: Contact holes. - Mask-7: Metallization.

43 n-well CMOS Process Cont The n-well process begins with n-well diffusion, Fig. 4.7a. - A thick SiO2 layer is etched to expose the regions for n- well diffusion. - The unexposed regions will be protected from the phosphorous impurity. Fig. 4.7 (a) Define n-well diffusion (mask 1)

44 n-well CMOS Process Cont Phosphorous is usually used for deep diffusion since it has diffusion coefficient and can diffuse faster into the substrate than can arsenic. Q # N1: Why Phosphorous is usually preferred than arsenic for n-well doping?

45 n-well CMOS Process Cont The second step is to define the active region (region where transistor are to be placed) using a technique called local oxidation (LOCOS). - A silicon nitride (Si3N4) layer is deposited and patterned relative to the previous n-well regions, Fig. 4.7b. Fig. 4.7 (b) Define active regions (mask 2)

46 n-well CMOS Process Cont The nitride-covered regions will not be oxidized. - After a long wet oxidation step, thick field oxide will appear in regions between transistors, Fig. 4.7c. - The thick field oxide is necessary for isolating the transistors. Fig. 4.7 (c) LOCOS oxidation

47 n-well CMOS Process Cont The next step is the formation of the Polysilicon gate, Fig. 4.7d. - This is one of the most critical steps in the CMOS process. Fig. 4.7 (d) Polysilicon gate (mask 3)

48 n-well CMOS Process Cont The Polysilicon gate is a self-aligned structure, because the separation between the source and drain diffusions -channel length- is defined by Polysilicon gate mask alone, hence the self-aligned property. Q # N2: Why the Polysilicon gate is a self-aligned structure?

49 n-well CMOS Process Cont A Polysilicon layer, usually arsenic doped (n-type), is deposited and patterned. - The Polysilicon gate also acts as a barrier for this implant to protect the channel region.

50 n-well CMOS Process Cont A layer of Photoresist can be used to block the regions where p-mosfets are to be formed, Fig. 4.7e. - The thick field oxide stops the implant and prevents n+ regions from forming outside the active regions. Fig. 4.7 (e) n+ diffusion (mask 4)

51 n-well CMOS Process Cont A reversed photolithography step can be used to protect the n-mosfets during the p+ boron source and drain implant for the p-mosfets, Fig. 4.7f. Fig. 4.7 (f) p+ diffusion (mask 5)

52 n-well CMOS Process Cont Before contact holes are opened, a thick layer of CVD (Chemical Vapor Deposition) oxide is deposited over the entire wafer. - A photo-mask is used to define the contact window opening, Fig. 4.7g, followed by a wet or dry oxide etch. Fig. 4.7(g) Contact holes (mask 6)

53 n-well CMOS Process Cont The thick layer of CVD oxide is deposited over the entire wafer to serve as a protective layer.

54 n-well CMOS Process Cont A thin aluminum layer is then evaporated onto the wafer. - A final masking and etching step is used to pattern the interconnection, Fig. 4.7h. Fig. 4.7(h) Metallization (mask 7)

55 n-well CMOS Process Cont - 14 Fig. 4.7 A typical n-well CMOS process flow

56 n-well CMOS Process Cont - 15 Fig. 4.7 Continued.

57 n-well CMOS Process Cont - 16 Figure 4.8 shows the cross-sectional diagram of an n- and p-mosfet Fig. 4.8 Cross-sectional diagram of an n- and p-mosfet

58 n-well CMOS Process Cont - 17 The main masks used in n-well CMOS Process are: - Mask-1: Definition of the n-well diffusion - Mask-2: Definition of the active regions. - LOCOS oxidation - Mask-3: Polysilicon gate. - Mask-4: n+ diffusion. - Mask-5: p+ diffusion. - Mask-6: Contact holes. - Mask-7: Metallization.

59 n-well CMOS Process Cont The corresponding schematic (for an inverter) is; shown in Fig. 4.11(a). - The layout of the n-well CMOS transistors corresponding to this cross-section is illustrated in Fig. 4.11(b). - The cross-section of the finished n-well process is shown in Fig. 4.11(c).

60 n-well CMOS Process Cont - 21 Fig Cross section of a CMOS inverter in an n-well process

61 n-well CMOS Process Cont In an n-well process, the p-type substrate is normally connected to the negative supply (VSS) through substrate contacts, while the well has to be connected to the positive supply (VDD) through VDD substrate contacts. - As the substrate is accessible at the top of the wafer and the bottom, connecting the substrate may be accomplished from the backside of the wafer. - Topside connection is preferred because it reduces parasitic resistances that could cause latch up.

62 n-well CMOS Process Cont Substrate connections formed by placing n+ regions in the n-well (VDD contacts) and p+ in the p-type substrate (VSS contacts) are illustrated by Fig. 4.12(a). Fig. 4.12a Substrate and well contacts in an n-well process.

63 n-well CMOS Process Cont The corresponding layout is shown in Fig. 4.12(b). Fig. 4.12b Substrate and well contacts in an n-well process.

64 n-well CMOS Process Cont - 25 Fig Substrate and well contacts in an n-well process.

65 n-well CMOS Process Cont Other terminology for these contacts include: well contacts, body ties, or tub ties for the VDD substrate connection. - It should be noted that these contacts are formed during the implants used for the p-channel and n-channel transistor formation.

66 4.4.2 p-well CMOS Process - n-well processes have emerged in popularity in recent years. - Prior to this, p-well processes were one of the most commonly available forms of CMOS. - Typical p-well fabrication steps are similar to an n-well process, except that a p-well is implanted rather than an n-well.

67 p-well CMOS Process Cont The first masking step defines the p-well regions. - This is followed by a low-dose boron implant driven in by a high-temperature step for the formation of the p-well. - The next steps are to define the devices and other diffusions; to grow field oxide; contact cuts; and metallization.

68 p-well CMOS Process Cont A p-plus (p+) mask may be used to define the p-channel transistors and VSS contacts. - Alternatively, we could use an n-plus mask to define the n-channel transistors, because the masks usually are the complement of each other. Fig p-well process.

69 p-well CMOS Process Cont P-well processes are preferred in caces where the characteristics of the n- and p-transistors are required to be more balanced than that achievable in an n-well process. - Because the transistor that resides in the native substrate tends to have better characteristics, the p-well process has better p-devices than an n-well process. - Because p-devices have lower gain than n-devices, the n-well process increase this difference while a p-well process moderates the difference.

70 4.4.3 Twin-Tub CMOS Process - Twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors, thus making it possible for threshold voltage, body effect, and the gain associated with n- and p-devices to be independently optimized. - The starting, material is either an n+ or p+ substrate with a lightly doped epitaxial or epi layer, which is used for protection against latch up. - The aim of Epitaxy is to grow high-purity silicon layers of controlled thickness with accurately determined dopant concentrations distributed homogeneously throughout the layer.

71 Twin Tub CMOS Process Cont The electrical properties of this layer are determined by the dopant and its concentration in the silicon. - The process sequence, which is similar to the n-well process where both p-well and n-well are utilized, include the following steps: * Tub formation. * Thin-oxide construction. * Source and drain implantations. * Contact cut definition. * Metallization.

72 Twin Tub CMOS Process Cont Since this process provides separately optimized wells, balanced performance n-transistors and p-transistors may be constructed. - Note that the use of threshold adjust steps is included in this process. - The cross-section of a typical twin-tub structure is shown in Fig The substrate contacts (both of which are required) are also included.

73 Twin Tub CMOS Process Cont - 3 Fig Twin-well CMOS process cross section.

74 4.4.4 Silicon On Insulator (SOI) - Rather than using silicon substrate, technologists use an insulating substrate to improve process characteristics such as latch up and speed. - Silicon can be grown on: * Sapphire or * SiO2 which in turn has been grown on silicon. - In SOl process a thin layer of single-crystal silicon film is epitaxially grown on an insulator such as sapphire or SiO2 that has been in turn grown on silicon.

75 SOI CMOS Process Cont Various masking and doping techniques (Fig. 4.15) are then used to form p-channel and n-channel devices. - Unlike the more conventional CMOS approaches, the extra steps in well formation do not exist in this technology.

76 SOI CMOS Process Cont The steps used in typical SOl processes are: (1) A thin film (7-8 µm) of very lightly-doped n-type Si is grown over an insulator. Sapphire or SiO2 is a commonly used insulator (Fig. 4.15a). Fig. 4.15a A thin film of n-type Si is grown over an insulator.

77 SOI CMOS Process Cont - 3 (2) An anisotropic etch is used to etch away the Si except where a diffusion area (n or p) will be needed, (Fig. 4.15b & c). Fig. 4.15b &c SOI process flow.

78 SOI CMOS Process Cont - 4 (3) The p-islands are formed next by masking the n- islands with a photoresist, Fig. 4.15d. - A p-type dopant, boron, for example-is then implanted. - It is masked by the photoresist, but forms p-islands at the unmasked islands. - The p-islands will become the n-channel devices. Fig. 4.15d p-island formation

79 SOI CMOS Process Cont - 5 (4) The p-islands are then covered with a photoresist and an n-type dopantphosphorus, for example is implanted to form the n-islands, Fig. 4.15e. - The n-islands will become the p-channel devices. Fig. 4.15e n-island formation.

80 SOI CMOS Process Cont - 6 (5) A thin gate oxide (around A 0 ) is grown over all of the Si structures. A Polysilicon film is deposited over the oxide, (Fig. 4.15f). Fig. 4.15f Growing of the thin gate oxide and deposition of Polysilicon.

81 SOI CMOS Process Cont - 7 (6) The Polysilicon is then patterned by photomasking and is etched, (Fig. 4.15g). Fig. 4.15g Polysilicon patterning and etching.

82 SOI CMOS Process Cont - 8 (7) The next step is to form the n-doped S and D of the n-channel devices in the p-islands, Fig.4.15h. - The n-islands are covered with a photoresist and an n- type dopant, normally phosphorus, is implanted. - After this step the n-channel devices are complete. Fig. 4.15h Forming of the S and D of the n-channel device

83 SOI CMOS Process Cont - 9 (8) The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant such as boron, Fig. 4.15i. Fig. 4.15i Forming of the S and D of the p-channel device.

84 SOI CMOS Process Cont - 10 (9) A layer of phosphorus glass or some other insulator such as silicon dioxide is then deposited over the entire structure. The glass is etched at contact-cut locations, Fig. 4.15j. Fig. 4.15j Glassing and metallization.

85 SOI CMOS Process Cont - 11 (9-2) The metallization layer is formed next by evaporating aluminum over the entire surface and etching it to leave only the desired metal wires. - The aluminum will flow through the contact cuts to make contact with the diffusion or Polysilicon regions. Fig. 4.15j Glassing and metallization.

86 SOI CMOS Process Cont - 12 Fig. 4.15j Glassing and metallization.

87 SOI CMOS Process Cont - 13 (10) A final Passivation layer of phosphorus glass is deposited and etched over bonding pad locations (not shown). - Because the diffusion regions extend down to the insulating substrate, only "sidewall" areas associated with S and D diffusions contribute to the parasitic junction capacitance. - Since sapphire and SiO2 are extremely good insulators, leakage currents between transistors and substrate and adjacent devices are almost eliminated.

88 SOI CMOS Process Cont - 14 Sol technology advantages: - Closer packing of p- and n-transistors due to the absence of wells. Also direct n -to- p connections may be made. - Lower substrate capacitances provide the possibility for faster circuits. * This because, only "sidewall" areas of S and D diffusions contribute to parasitic junction capacitance, faster devices.

89 SOI CMOS Process Cont - 15 Sol technology advantages Cont - There is no latch up because of the isolation of the n- and p-transistors by the insulating substrate. - Because there is no conducting substrate, there are no body-effect problems. - Leakage currents to substrate and adjacent devices almost eliminated.

90 SOI CMOS Process Cont - 16 Sol technology disadvantages: - Due to absence of substrate diodes, the inputs are somewhat more difficult to protect. - Because device gains are lower, I/O structures have to be larger. - Single crystal sapphire, and silicon on SiO2 are considerably more expensive than silicon substrates, and their processing techniques tend to be less developed than bulk silicon techniques.

91 SOI CMOS Process Cont - 17 SOI CMOS Process ABSTRACT

92 4.5 Layout Design Rules Deign Rules 1- The interface (Contract) between designer and process engineer, i. e., provide a communication channel between the IC designer and the fabricator. 2- Design rules specify geometric constraints on the layout artwork. 3- Guidelines for constructing process masks. 4- Unit dimension: Minimum line width. a- Scalable design rules: lambda parameter. b- Absolute dimensions (micron rules).

93 Layout Design Rules - Cont Objective: a- To obtain a circuit with optimum yield. b- To minimize the area of the circuit. c- To provide long term reliability of the circuit. (1) Design rules represent the best compromise between performance and yield: (a) More conservative rules increase yield. (b) More aggressive rules increase performance. (2) Design rules represent a tolerance that ensures high probability of correct fabrication - rather than a hard boundary between correct and incorrect fabrication.

94 Layout Design Rules - Cont Two approaches to describing design rules: a- Lambda-based rules (λ-rules): known as scalable rules as they allow first order scaling (1) Moving from one process to another requires only a change in λ. e. g., to move a design from 4 micron to 2 micron, simply reduce the value of λ. (2) Worked well for 4 micron processes down to 1.2 micron processes. (3) In general, processes rarely shrink uniformly. (4) Probably not sufficient for submicron processes.

95 Layout Design Rules - Cont - 3 b- Micron rules: All minimum feature sizes and spacings for all masks specified in microns. e.g., 3.25 microns for contact-poly-contact (transistor pitch) and 2.75 micron metal 1 contact -to- contact pitch. (1) Rules don't have to be multiples of λ. (2) Micron rules can result in as much as a 50% size reduction over λ rules. (3) Normal style for industry. Note: Pitch: The repeat distance between objects

96 Layout Design Rules - Cont Stick Diagram (symbolic Layout) 1- The initial phase of layout design can be simplified significantly by the use of Stick Diagrams or the socalled symbolic Layout. 2- In the stick diagrams, the detailed layout design rules are simply neglected and the main features (active areas, Polysilicon lines, metal lines) are represented by constant width rectangles or simple sticks. 3- The purpose of the stick diagram is to provide the designer a good understanding of the topological constraints, and to quickly test several possibilities for the optimum layout without actually drawing a complete mask diagram.

97 Layout Design Rules - Cont - 5 Stick Diagram - Cont 4- Finally, stick diagrams may be seen as: a- Abstract version of layout. b- Dimensionless layout entities. c- Workout topology without details: (1) Lines (wires) drawn in color to denote a particular layer. (2) Lines on the same layer cannot cross. (3) Lines drawn with no thickness. (4) Approximate relative spacing. d- Used colored pencil.

98 Layout Design Rules - Cont Layout 1- The physical layouts of CMOS gates are studied to examine the impact of the physical structure on the behavior of the circuit. 2- In the layout we note that: a- Lines drawn between devices represent connections. b- Any non-planar situation is dealt-with by simply crossing two lines. c- In physical layout, we have to concern ourselves with the interaction of physically different interconnection layers. 3- Final layout generated by compaction program.

99 Layout Design Rules - Cont - 7 Example 4.1: For the CMOS Inverter Draw: - Circuit schematic. - Stick Diagram. - Layout diagram. - Cross-section in an n-well process. Example 4.2: For the CMOS NAND Gate Draw: - Circuit schematic. - Stick Diagram. - Layout diagram. Example 4.3: For the CMOS NOR Gate Draw: - Circuit schematic. - Stick Diagram. - Layout diagram.

100 Layout Design Rules - Cont - 8

101 Layout Design Rules - Cont - 14 [4] nmos transistors structure Fig. a nmos Transistor structure