Silicon VLSI Technology. Fundamentals, Practice and Modeling

Transcription

1 Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D. Deal, and P. B. Griffin

2 THERMAL OXIDATION SiO 2 and the Si/SiO 2 interface are the principal reasons for silicon s dominance in the IC industry. Oxide Thickness µm 0 nm Thermally Grown Oxides Field Oxides 0. µm Masking Oxides nm Pad Oxides Gate Oxides Tunneling Oxides Chemical Oxides from Cleaning Native Oxides Deposited Oxides Backend Insulators Between Metal Layers Masking Oxides SiO 2: Easily selectively etched using lithography. Masks most common impurities (B, PAs P, As, Sb). Excellent insulator ( ρ>0 6 Ωcm, E g > 9 ev ). High breakdown field ( 0 7 Vcm - ) Excellent junction passivation. Stable bulk electrical properties. Stable and reproducible interface with Si. No other known semiconductor/insulator combination has properties that approach hthe Si/SiO 2 interface. 2

3 SIA NTRS Roadmap Year of Production Technology Node (half pitch) 250 nm 80 nm 30 nm 90 nm 65 nm 45 nm 32 nm 22 nm 8 nm MPU Printed Gate Length 00 nm 70 nm 53 nm 35 nm 25 nm 8 nm 3 nm 0 nm DRAM Bits/Chip (Sampling) 256M 52M G 4G 6G 32G 64G 28G 28G MPU Transistors/Chip (x0 6 ) ,000 Gate Oxide T ox Equivalent (nm) MPU Gate Oxide T ox Equivalent (nm) Low Operating Power Gate Dielectric Leakage 00 C) MPU Thickness Control (% 3σ ) < ±4 < ±4 < ±4 < ±4 < ±4 < ±4 Min Supply Voltage (volts) SiO 2 is not the gate dielectric of the future High-K dielectrics are now being used to reduce leakage C κ ε A d = 0 3

4 Si and SiO 2 Oxidation occurs at the Si/SiO 2 interface A pure Si layer will oxidize at room temperature Rapid growth to 0.5 to nm (5-0 Angstroms) Final growth of -2 nm Oxidation involves a volume expansion SiO 2 is 30% larger than Si Volume expansion.3 3 ~ 2.2 Induces stress where confined, especially in 2D and 3D structures, stress effects play a dominant role. Volume Expansion Deposited Polysilicon SiO 2 Original Si Surface Location of Si 3 N 4 Mask Si Substrate 4

5 Basic Concept O 2 or H 2 0 diffuse to Si interface Oxidation reaction consumes silicon moving the interface down and the SiO 2 up as material is consumed and the volume increases SiO2 volume expansion can cause stress on the surface 30 % expansion in all directions when unconstrained Stress induced when volume constrained Si substrate.3 Si substrate 5

6 SEM of LOCOS Volume Expansion Bird s Beak Topology lateral growth Deposited Polysilicon Volume Expansion SiO 2 Original Si Surface Location of Si 3 N 4 Mask Si Substrate Stress at the Si/Si 3 N 4 interface 6

7 Structure of Silica Glass Short range order Amorphous hd hydrogen maintained material Non-bridging oxygen in fused Silica (not present in crystalline SiO 2 ) Network modifier ----> Q m Si can be replaced by deposits. B,P,As or Sb = network formers. SiO 2 is amorphous even though it grows on a crystalline substrate (Figure 3-5) Based on SiO4 tetrahedra shown above. Bridging oxygen atoms share to form crystal like quartz Time to form appropriate rotational forms for full crystallization not available; therefore, forms rarely observed in IC Lattice doesn t match Si, but there is a short range order 7

8 Si/SiO 2 Stresses Compressive stress due to constrained growth region Grow upward Stress as large as 5 x 0 9 dyne cm -2 At high temperature, viscous flow may reduce stress There is a large difference in the thermal expansion coefficients Stress as large as -2 x 0 9 dyne cm -2 Wafer curvature can be produced from unbalanced stress between the top and bottom of a wafer Selective etching of one surface will produce curvature 8

9 Oxide Layer: Intel 90 nm Process SiO 2 is amorphous even though it grows on a crystalline substrate Lattice doesn t match Si There is a short range order Intel SiO 2 of approx. 3-5 atomic layers Deal and Grove (965) showed that SiO 2 growth follows a linear parabolic law. Where model inadequate: thin oxides, oxides grown in mixed ambient, oxides grown on 2D and 3D Si surfaces, oxides grown on heavily doped substrates 9

10 Oxide Growth Charges Transition Region K+ Q m SiO Na Four charges are associated with Q ot insulators and insulator/semiconductor - interfaces. x + x + x + + x x + x Q f Q f - fixed oxide charge Q it - interface trapped charge Q m - mobile oxide charge Silicon Q it Q ot - oxide trapped charge Deal defined nomenclature in 980 for electrical charge defects Processing to reduce charges: High temperature inert anneals in Ar or N 2 toward the end of process flow. Moderate temperature anneal (400 ºC) in H 2 or forming gas (N 2 /H 2 ) 0

11 Wafer Fabrication Equipment Quartz Tube Wafers Resistance Heating Quartz Carrier Oxidation systems are conceptually very simple. Dry or wet, ºC In practice today, vertical furnaces, RTO systems and fast ramp furnaces all find use. O 2 H 2 Gate Oxides LOCOS or STI DRAM Dielectrics Thermal oxidation can potentially be used in many places in chip fabrication. In practice, deposited SiO 2 layers are increasingly being used (lower Dt).

12 Conventional Oxidation System Wafer loading should use cantilever or elavators (perpendicular) to avoid touching the walls. 3 zones Vertical furnaces are also used. Better uniformity, easier automation, cleaner - no contact with the tub C Dry or wet oxidation Ramping of T from/to 800 C ( 0 C/sec) Add HCl or TCA for gettering purpose (metals, Na + ) At 000 C, in wet O 2 is approx. 0. nm per second. It approx. doubles for every 00 C rise, 2

13 Rapid Thermal Oxidation Reduced time for temperature ramp 00 ºC per second vs. <0 ºC per second Reduced size chamber for smaller number of wafers Single wafer vs. multiple boats of 0-50 wafers Simple temperature feedback Pyrometer monitors wafer vs. multiple zones with thermocouple that are preset at installation (need +/- 0.5 ºC control) 3

14 Measurement Methods Physical Optical Electrical Devices (MOS Capacitor gate) 4

15 Physical Step Height Measurement By etching away part of the SiO 2, the resulting step height between the original Si and new SiO 2 height can be made. Atomic Force Microscope Technique to visual Figure -3 Cross section wafer and use an SEM As in Figure 6-4 or a TEM in Figure 3-5 Deposited Polysilicon Volume Expansion SiO 2 Original Si Surface Location of Si 3 N 4 Mask Si Substrate 5

16 Optical Measurement Optical (usually non destructive): thick oxides (color chart, ellipsometry, reflectance) but for thin oxides: ellipsometry REFLECTANCE white or monochromatic light Rf Refraction indexes For monochromatic light minima and maxima in the reflected beam allows to determine x ox (fringes, spectrometers with sweeping wavelength λ for fixed φ we can find extrema). [Good for a few tens of nm] Ellipsometry uses polarized light and detect the change in polarization of the reflected light due to a film (thickness, index of refraction) Color chart (x ox > 50nm) > not destructive interference will affect the reflected light > color correlated with thickness of a dielectric layer (0-20 nm accuracy) 6 ( β ) 2 n x0 cos λ = m maxima at m =,2,3, L 3 5 minima at m =,,, L n ( ) ) 0 sin φ β = arcsin n

17 Optical Methods Optical color pattern Color Chart description in Table A.7 on p

18 Electrical Measurements Direct electrical measurement of device type parameters Oxides are typically used as the dielectric layer in a capacitor Doped silicon conductor, SiO 2 dielectric, doped polysilicon or metal conductor layers similar to an MOS transistor. Typically Capacitance-Voltage or C-V measurements are taken A DC bias with an AC voltage source to measure changes in impedance with frequency Widely used for MOS devices, gate oxide parameters, and carrier lifetimes 8

19 DC bias + small AC high frequency signal applied. C-V Measurements DC bi + ll AC a) + VG C C = dq dv e - N Silicon Doping = N D CO - + CO VG a) Accumulation majority carrier drawn to surface ox A Cox = ε x ox Charge Density Q = Q = G D N D x D b) c) - VG e - -- VG x D CO CD - C + C CO V G b) Depletion minority carrier drawn to surface majority carriers repelled C D A = ε Si x D Q = N x + Q G D D I Q G Q I Q D e - Holes x DMax 9 CO C DMin CO c) Inversion minority carrier layer exists - V + TH V G

20 C-V Plot C Ideal LF Q I follows Q Low freq C =C OX inversion Q D follows Q High freq C ~ f(c OX, C D ) CMin Ideal HF Deep Depletion depletion Cox accumulation DC Gate Voltage VTH LF curve - inversion layer carriers can be created and recombine at AC signal frequency so C inv is just C ox. HF curve (00 khz to MHz) - inversion layer carriers cannot be generated fast enough to follow the AC signal so C inv is C ox + C D. Deep depletion - DC voltage is applied fast enough that inversion layer carriers cannot follow it, so C D must expand to balance the charge on the gate. C-V measurements can be used to extract quantitative values for: t ox - oxide thickness N A - the substrate doping profile Q f, Q it, Q m, Q ot - oxide, interface charges 20

21 MOS C-V Band Diagram X D = X Dmax Q D fixed X D > X Dmax * To avoid deep depletion*: Holes generated in the depletion layer and attracted by the gate source the DL when V G increases ni qnw i U =, J gen = τ G τ G dv J gen J gen qnw i = dt C C τ C OX A OX 0.V 2 / sec High frequency AC signal changes faster than Q I can respond (generation is slow) ΔQ G = ΔQ D x D = x D max C D = C D max

22 Charges Derived Q m, Q ot have similar effect as Q f (shift characteristics) Due to traps Traps cannot charge or discharge - do not respond to HF signal Q i respond to DC voltage stretch out change in E F (V G ), charges at E it. Stress of the oxide (ex. charge injection, radiation) C-V Vdegradation d ( time to breakdown, charge to breakdown)

23 Models and Simulation Deal-Grove Model Plots ÞC.5 00 ÞC ÞC 000 ÞC ÞC ÞC ÞC 800ÞC Time - hours ÞC 700 ÞC Time - hours Oxidation rate for (00) silicon in dry O 2. Oxidation rate for (00) silicon in wet O 2. 2

24 Deal Grove Model µm µm x O CG CO CS The basic model for oxidation was developed in 965 by Deal and Grove. A linear parabolic model Gas Oxide CIC I Silicon Si + O 2 SiO 2 (2) () Si + 2H 2 O SiO 2 + 2H 2 (3) F F 2 F 3 F: Transport of Oxygen to oxide surface Gas phase diffusion through stagnant boundary layer Equilibrium i concentration ti in a solid (based on partial pressures) F2: Diffusion of oxidant through the oxide F3: Reaction with the Silicon surface In steady-state, F = F2 = F3 where flux is in molecules cm -2 sec - 3

25 Deal Grove Model µm µm x O CG C S Diffusion of oxidant through the oxide CO Fick s Law - Diffusivity CIC I Gas Oxide F F 2 F 3 Silicon F 2 C = D x C = D O C x O I The gradient is approx. a constant Transport of Oxygen to oxide surface Ideal Gas Law F = h G ( C C ) Mass transport coefficient Surface Henry s Law C C * G = H O P S = H P P P S P G G S C O F C C G S P = G P = S hg = H kt kt kt * ( C C ) O Reaction with the Silicon surface Interface reaction rate F = k C 3 S I 4

26 Deal-Grove Model (2) Under steady state t conditions, F = F 2 = F 3 so F F 2 = h C = D * ( C ) O C O C x O F = k C 3 S I I C I * C = ks ks x + + h D C O O * ks xo C + D = k k S x + S + h D * C ks x + D O O C * h very large and can be neglected Note that the simplifications are made by neglecting /h where h large. This results in is a very ygood approximation. Combining the above, we have dx = dt F N Oxygen molecules incorporated per unit volume of oxide grown F = k C 3 S I dx dt = F N = * ks C ks N + + h ks x D O 5

27 Deal-Grove Model (3) + + = = D x k h k N C k N F dt dx O S S S * X = + + t S X X O S S dt C k dx D x k h k N O I 0 * t x x x x i O i O = t A B B = + / where (parabolic rate constant, F 2 dominant) * 2 N DC B = * * N k C h k N C A B S S + = (linear rate constant, F 3 dominant) and Defining initial conditions of the interface: A B x B x i i / 2 + = τ x x 2 6 +τ = + t A B x B x O O /

28 Deal-Grove Model (4) Solving for oxide thickness as a function of time. x 2 O B xo + = t B / A + τ x 2 O ( t + ) = 0 + A x B τ O x O () t A t + τ = A / 4B For thin oxide, x small For thick oxide, x large x 2 O B xo xo + = t +τ B / A B / A x O A = t B ( +τ ) 2 xo B 2 xo xo + = t +τ B / A B x O 2 = B t ( +τ ) 7

29 Deal-Grove Model (5) x O 2DC B = N A t + τ = A / 4B * 2 xi xi τ = + B B / A F 2 dominant B A = * * C C k N N + ks h S F 3 dominant k s x 0 /D << C I C* Diffusion fast compared to chemical reaction for thin oxides. k s x 0 /D >> For about nm. ks, D(T) 2 A x O = B ( t +τ ) x O = ( t +τ ) B 8 C I 0 Fast reaction - diffusion limits oxidation (thick oxides)

30 The rate constants B and B/A have physical meaning (oxidant diffusion and interface reaction rate respectively). Ambient B B/A Dry O 2 C = 7.72 x 0 2 µ 2 hr - E =.23 ev Wet O 2 C = 2.4 x 0 2 µ 2 hr - E = 0.7 ev H 2 O C = 3.86 x 0 2 µ 2 hr - E = 0.78 ev T (ÞC) C 2 = 6.23 x 0 6 µ hr - E 2 = 2.0 ev C 2 = 8.95 x 0 7 µ hr - E 2 = 2.05 ev C 2 =.63 x 0 8 µ hr - E 2 = 2.05 ev 800 ( E kt ) B = C exp / B A = C ( E / kt ) exp 2 2 Numbers are for () silicon, for (00) divide C 2 by B/A H 2 O B µm 2 hr - B/A µm hr B Dry O 2 B/A Dry O 2 B H 2 O Plots of B, B/A using the values in the above Table /T (Kelvin) 9

31 Deal-Grove Model ÞC ÞC ÞC 000 ÞC ÞC ÞC ÞC 800ÞC Time - hours ÞC 700 ÞC Time - hours Oxidation rate for (00) silicon in dry O 2. Oxidation rate for (00) silicon in wet O 2. Wet O 2 rate is significantly higher than dry O 2. The oxidant solubility is higher. Dry O 2 used for thin oxides and controlled depths, wet O 2 for thicker films. 20

32 Example Problem ÞC.5 00 ÞC c) a) 900ÞC 00ÞC 000ÞC 800ÞC Time - hours Calculated (00) silicon dry O 2 oxidation rates using Deal Grove b) 000 ÞC 900 ÞC 800 ÞC 700 ÞC Time - hours Calculated (00) silicon H 2 O oxidation rates using Deal Grove. Example: Problem 6.3 in the text: a) 3 hrs in O 00 C = 0.2 µm + b) 2 hrs in H C = 0.4 µm + c) 2 hrs in O 200 C = 0.5 µm total oxide thickness. 2

33 Volume Mismatch in Si/SiO2 System; Recessed LOCOS Example: H 2 O@000 C; Find time to get planar surface? y Si 2.2X 2X volume expansion -> 45%y ox =y Si so y ox =y Si /.45 Total oxide thickness to be grown: y ox =y Si /0.45=y Si +0.5µm y Si =0.4µm y ox =0.9µm For H 2 O Time for dry oxidation would be unrealistically long 22

34 Thin Oxide Growth Models A major problem with the Deal Grove model was recognized when it was first proposed - it does not correctly model thin O 2 growth kinetics. Experimentally O 2 oxides grow much faster for 20 nm than Deal Grove predicts. MANY models have been suggested in the literature.. Reisman et. al. Model x = at+ t b or x = at+ x i O ( i) O a Power law fits the data for all oxide thicknesses. a and b are experimentally extracted parameters. Physically - interface reaction controlled, volume expansion and viscous flow of SiO 2 control growth. b b 23

35 Thin Oxide Growth Models 2. Han and Helms Model B B 2 dx O = + dt 2x O + A 2x O + A 2 Second parallel reaction added - fits the data for all oxide thicknesses. Three parameters (one of the A values is 0). Second process may be outdiffusion of O V and reaction at the gas/sio 2 interface. 3. Massoud et. al. Model dx O B = dt 2x O + A + Cexp x O L Second term added to Deal Grove model - higher dx/dt during initial growth. L 7 nm, second term disappears for thicker oxides. Easy to implement along with the DG model, used in process simulators. Data agrees with the Reisman, Han and Massoud models. (800 C dry O 2 model comparison below.) 24

36 Thin Oxide Growth Models 25

37 Additional Growth Considerations Dependence on Pressure If Henry s Law holds, the growth coefficients are dependent on the oxidant just inside the oxide at the gas/sio 2 interface. This is dependent upon gas pressure 26

38 Additional Growth Considerations Dependence on Crystal Orientation Oxidation rates are faster on () silicon as compared to (00) silicon. Many current structures uses trench etching and growth. The effect may be due to differences in the number of available bonds at the surface. 27

39 a) Etched dsiri Ring Side Views 2D SiO2 Growth Kinetics Si Substrate Top Views These effects were investigated in detail experimentally by Kao et. al. about 5 years ago. Typical experimental results below. b) c) Polysilicon SiO 2 Si d) 28 (Kao et.al)

40 2D SiO2 Growth Kinetics Difference in volume -> problems when expansion is restricted (SiO 2 confined) Poly-Si for contrast Experiments by Kao et al.: Retardation at sharp corners (2X for 500 nm SiO 2 ) Retardation low T (no 200 C) Interior (concave) corners oxidize slower than exterior (convex) but both slower than flat Si Reasons Crystal orientation Diffusion of oxidant through amorphous SiO 2 is the same -> no dependence on direction Stress (volume difference): SiO 2 under large compressive stress -> affect both oxidant transport and reaction at the Si surface 29

41 . Norm malized Oxide Th hickness ÞC 000 ÞC 900 ÞC 800 ÞC 200 ÞC 900 ÞC Stress Effects 00 ÞC 000 ÞC Convex Radii Concave Radii µm 0.2 µm 0.25 µm (Kao et.al) /r µm - Several physical mechanisms seem to be important: Crystal orientation 2D oxidant diffusion Stress due to volume expansion To model the stress effects, Kao et. al. suggested modifying the Deal Grove parameters. k S σ = nvr σ V t ( stress) ks exp exp kt kt ( P )( V ) D( stress) = D exp kt C * D ( P)( ) = * V ( stress ) C exp kt where σ n and σ t are the normal and tangential stresses at the interface. V R, V T and V S are reaction volumes and are fitting parameters. 30 S T

42 Simulating Stress In addition, the flow properties of the SiO 2 need dto be described dby a stress dependent viscosity σ η(stress ) =η(t) S V C /2kT sinh σ S V C /2kT ( ) where is the shear stress in the oxide and V C is again a fitting parameter. σ S -0.4 Parameter Value SiO V R nm 3 0 V D nm 3 V S, V T V C 0.3 nm C nm 050 C η(t) - SiO x 0 0 exp(2.9 ev/kt) poise 0.6 η(t) - Si 3 N x 0 0 exp(.2 ev/kt) poise 0.8 Microns -0.2 SiO 2 Si 3 N 4 Silicon Microns These models have been implemented in modern process simulators and allow them to predict shapes and stress levels for VLSI structures (above right). ATHENA simulation: Left - no stress dependent parameters, Right including stress dependence Microns

43 Point Defect Based Models The oxidation models we have considered to this point are macroscopic models (diffusion coefficients, chemical reactions etc.). O 2 H 2 O Diffusion I * * I V There is also an atomistic ti picture of oxidation that has emerged in recent years. Most of these ideas are driven by the volume expansion occurring during oxidation and the need for free volume. Oxide Silicon In Chapter 3 we described internal oxidation in the following way when discussing SiO 2 precipitates as gettering sites (p.4-2): ( + 2γ ) Si + 2O + 2βV SiO + 2γI stress Si I 2 + Surface oxidation can be thought of in the same way. Vacancies drawn to the surface, Interstitials titi created and move into the bulk silicon (causing other effects?! OED and ORD) 32

44 Oxidation Enhanced/Retarded Diffusion The connection between oxidation and other processes can then be modeled as shown below. O2 Surface Recombination Bulk Recombination * G I R Micro ons Si 3 N 4 SiO 2 Inert Diffusion OED Inert Diffusion Buried Dopant Marker Layer OED Microns Example - ATHENA simulation of OED. Oxidation injects interstitials to create free volume for the oxidation process. Oxidation can also consume vacancies for the same reason. These processes increase I concentrations and decrease V concentrations in nearby silicon regions. Any process (diffusion etc) which occurs via I and V will be affected. 33

45 Substrate Doping Effects Concentration Enhanced Oxidation (CEO) 5x faster due to dopant 2x faster N Dopant P -> oxide growth by B/A not by B; low T about 3-4X due to concentrations Low T High T CEO stronger for N + than P + (B/A grows, B does not) CEO for Boron changes B but not B/A due to incorporation in the oxide Properties of oxide do not change for P but change for B Oxidation needs V for volume expansion so for dopant concentrations, charged V (V -, V = -N + -type; V + -P + -type) -> B/A Dopant segregation N + -> >tosi P + -> SiO 2 Interface changes during oxidation -> growth rate changes 34

46 . Mic crons Micron ns Complete Process Simulation of Oxidation Many of these models (and others in Chapter 6), have been implemented in programs like SUPREM Simulation of an advanced isolation structure (the SWAMI process originally developed by Hewlett-Packard), using SSUPREM IV. The structure prior to oxidation is on the top left. A 450 min H 2 O oxidation at 000 C is then performed which results in the structure on the top right. An experimental structure fabricated with a similar process flow is shown on the bottom right. The stress levels in the growing - 0 SiO 2 are shown at the end of Microns the oxidation on the bottom 35 left.

47 Recessed LOCOS ATHENA Simulation 36

48 Summary of Key Ideas Thermal oxidation has been a key element of silicon technology since its inception. Thermally, chemically, mechanically and electrically stable SiO 2 layers on silicon distinguish silicon from other possible semiconductors. The basic growth kinetics of SiO 2 on silicon are controlled by oxidant diffusion and Si/SiO 2 interface chemical reaction. This simple Deal-Grove model has been extended to include 2D effects, high dopant concentrations, mixed ambients and thin oxides. Oxidation can also have long range effects on dopant diffusion (OED or ORD) which are modeled through point defect interactions. Process simulators today include all these physical effects (and more) and are quite powerful in predicting oxidation geometry and properties. 37