CMP for Thru-Silicon Vias TSV Overview & Examples March 2009

Transcription

1 CMP for Thru-Silicon Vias TSV Overview & Examples March 2009

2 Packaging Evolution Source: Yole Dev

3 3D Integration Source: Yole Dev 2007 Growth rates for 3D integration Flash continues to drive the market DRAM leading new growth Units (000) CAGR RF SiP (8" eq.) % CIS (12" eq.) % Flash (12" eq.) % DRAM (12" eq.) % MEMS (8"eq.) % 3D SiP (12" eq.) % 3

4 3D Scenerios 4

5 Wafer Thinning Engineering Technology Development Wafer Grind Grind Thickness CMP Polish Thickness Thickness Ratio Etch (Optional) TSV Exposure Etch Thickness Process Guidelines Optimal Parameters 5

6 Background CMP modules for advanced packaging have been developed at Entrepix for over 6 years. Vias can be filled with any of several conductive materials Common options include copper, polysilicon, tungsten Final choice depends on dimensions, operating voltage and current, plus other integration factors Vias can be completely filled or left partially hollow depending on current load, operating voltage, etc. 6

7 Experienced Approach CMP Development Sequence Generate Test Wafers Consumables Screening Process DOE's Optimize Uniformity Optimize Planarity Optimize Defectivity Repeatability (multiple runs) Stability (marathon) Release for Device Qualification CMP process development is critical to success with most new integrations Experience with broad range of materials, pads, and slurries is key to efficiency Test wafer availability and quality often impact timeline, validity of results, etc. Initial process DOE s generally focus on removal rate and surface quality Optimization stages can be interchanged or executed in parallel Planarity can mean step height, dishing, recess, roughness, etc. depending on the material and intended application Metrics are specific to each integration and can be adjusted as required 7

8 TSV Summary Table TSV Fill Material Deposition Thickness Demonstrated CMP Polish Rate Dishing / Recess (Angstroms) Copper 5 ka 60 µm 1 ka/min 8 µm/min 10 A 0.3 µm Polysilicon 4 ka 30 ka 2 ka/min 15 ka/min Ang Tungsten 3 ka 9 ka 3 ka;/min 8 ka/min Ang NiFe or NiFeCo 1.5 µm 8 µm 3 ka/min 7 ka/min Ang 8

9 Copper Vias Source: IBM Numerous customers are using plated copper for TSV s Typical via sizes µm and plating thicknesses 3 40 um Cu recess below 0.4 um achieved for multiple trials Characterized CMP interactions with cumulative film stress, wafer shape, annealing, etc. 2 nd Example: Cu (stop on TEOS) Intended integration = Direct Wafer Bonding Goal of <200 A total topography Flat across Feature POST-CMP TOPOGRAPHY ACHIEVED Angstroms 9

10 Tungsten Vias Technology adapted from proven CMOS device integrations Typical via sizes are sub-micron but many vias can be ganged in parallel for higher current Typical W recess achieved is below 500 Ang Center Relatively mature CMP approach, but integration can be difficult, esp. stress control Edge 10

11 Multiple Materials Challenging integration Final surface is comprised of oxide, polymer, and two different metals Goals of CMP process: High rate on oxide and polymer Low Ra on all materials Planar surface across all materials Initial focus: Slurry screening RR (Ang/min) Material Removal Rates by Formulation Baseline Sample A Sample B Sample C Sample D Sample D+ Sample E+ sample delaminated. Oxide Rate Polymer Rate Metal #1 Rate Metal #2 Rate Data Removal Rate Roughness (Ra) Run Order Slurry Oxide Rate Polymer Rate Metal #1 Rate Metal #2 Rate Oxide Ra (Ang) Polymer Ra (Ang) Metal #1 Ra (Ang) Metal #2 Ra (Ang) 1 Baseline n/a 5 2 Sample A Sample B Sample C Sample D Sample D n/a n/a 7 Sample E

12 Summary Developing new device or packaging integrations requires expertise in each critical unit process, especially CMP Entrepix has extensive experience in via processing Copper, polysilicon, tungsten, NiFe, and more Process optimization requires strong understanding of pad/slurry/recipe interactions and how they impact both wafer and device level metrics CMP of virtually any material on any wafer size Entrepix 12