Section 11: Process Integration

Transcription

1 Sectio 11: Process Itegratio Jaeger Chapters 9, 11 EE143 Ali Javey Slide 11-1 Process Itegratio Self-aliged Techiques LOCOS- self-aliged chael stop Self-aliged Source/Drai Lightly Doped Drai (LDD) Self-aliged silicide (SALICIDE) Self-aliged oxide gap MEMS Release Techiques Sacrificial Layer Removal Substrate Udercut Example IC Process Flows NMOS - Geeric NMOS Process Flow CMOS - The MOSIS Process Flow Advace MOS Techiques Twi Well CMOS, Retrograde Wells, SOI CMOS EE143 Ali Javey Slide 11-2

2 Self-aliged Source ad Drai Perfect Aligmet poly-si gate As Off Aligmet As * The S/D always follows gate EE143 Ali Javey Slide 11-3 Commet: No self-aliged Alterative Chael ot liked to S/D Stray capacitace. Solutio: Use gate overlap to avoid offset error. Disadvatages: Two lithography steps, excess gate overlap capacitace EE143 Ali Javey Slide 11-4

3 Lightly Doped Source/Drai MOSFET CVD oxide spacer SiO 2 p-sub The -pockets (LDD) doped to medium coc (~1E18) are used to smear out the strog E-field betwee the chael ad heavily doped S/D, i order to reduce hot-carrier geeratio. EE143 Ali Javey Slide 11-5 LDD Process implat for LDD CVD coformal depositio SiO 2 CVD SiO 2 SiO 2 Directioal RIE of CVD Oxide EE143 Ali Javey Slide 11-6

4 LDD Process (cot d) μm 0.25μm Spacer left whe CVD SiO 2 is just cleared o flat regio. implat EE143 Ali Javey Slide 11-7 Salicide Itegratio Ti depositio Ti SiO 2 Si Ti o heat treatmet ( > 700 C) TiSi 2 Ti 2 Si TiSi Ti 2 Ti Ti will ot react with SiO 2. Selective etch to remove ureacted Ti oly EE143 Ali Javey Slide 11-8

5 CMOS: Basic sigle-well process EE143 Ali Javey Slide 11-9 Sigle-well process (cot d) Patter mask opeig For p-well implat Shallow implatatio of boro Diffusio drive-i To form p-well i oxidizig ambiet Remove maskig oxide EE143 Ali Javey Slide 11-10

6 Sigle-well process (cot d) Pad oxide growth ad CVD Si 3N 4. Patter field oxide regios Blaket implat of Boro for p chael stop iside p-well Protect p-well regios with photoresist. LOCOS Oxidatioxxx Thermal oxidatio of gate SiO 2 EE143 Ali Javey Slide Sigle-well process (cot d) CVD poly-si!! Patter poly-si gates Protect ALL -chael trasistors with photoresist. Boro implatatio to form source/drai of p- chael trasistors t ad cotacts to p-well EE143 Ali Javey Slide 11-12

7 Protect ALL p-chael trasistors t with photoresist. t Arseic implatatio to form source/drai of -chael trasistors ad cotacts to - substrate CVD SiO 2 (Low-temperature oxide) Sigle-well process (cot d) Patter ad etch cotact opeigs to source/drai, well cotact, t ad substrate t cotact. t EE143 Ali Javey Slide Sigle-well process (cot d) Metal 1 depositio Patter ad etch Metal 1 itercoects CVD SiO 2 EE143 Ali Javey Slide 11-14

8 Sigle-well process (cot d) Patter ad etch cotact opeigs to Metal 1. Metal 2 depositio. Patter, ad etch Metal 2 itercoects. EE143 Ali Javey Slide Twi-well CMOS Techology EE143 Ali Javey Slide 11-16

9 Shallow Trech Isolatio Shallow trech isolatio i a twiwell process It Itercepts t depletio lti layers permittig tighter spacig Reduces the chace of latchup EE143 Ali Javey Slide MEMS - Diaphram Formatio Diaphrams formed by aisotropic backside etchig of the silico wafer (a) SiO 2 layer/diaphram used as a etch stop (b) Buried SiO 2 or p layer ca be used as a etch stop to form thi diaphrams (c) Ofte used i pressure sesors EE143 Ali Javey Slide 11-18

10 MEMS - Sealed Cavity Formatio EE143 Ali Javey Slide Surface Micromachiig - Rotary Structures EE143 Ali Javey Slide 11-20

11 MEMS - Hige Formatio EE143 Ali Javey Slide 11-21