A Nano-thick SOI Fabrication Method

Transcription

1 A Nano-thick SOI Fabrication Method C.-H. Huang 1, J.T. Cheng 1, Y.-K. Hsu 1, C.-L. Chang 1, H.-W. Wang 1, S.-L. Lee 1,2, and T.-H. Lee 1,2 1 Dept. of Mechanical Engineering National Central University, Chungli, Taiwan, R.O.C. 2 Institute of Materials Sci. & Eng., National Central University, Chungli, Taiwan, R.O.C. ABSTRACT A nano-thick SOI fabrication method is proposed by a thermal oxidized silicon wafer with a polysilicon cladding layer as a device wafer. Hydrogen molecular ions were implanted by 4 x ions/cm 2 on the device wafer surface at energy of160 KeV. After hydrogen ion implantation, the implanted device wafer was then joined to a Pyrex 7740 glass wafer as a handle wafer by anodic bonding process. The layer with polysilicon-oxide-silicon sandwich structure was successfully split from the device wafer and transferred onto the handle wafer after treated at a constant temperature, 200 with irradiating by microwave with power of 500W for 10 minutes. From the simulation data, the thickness of the top silicon can be about 100 nm at the splitting off. This demonstrates a fabrication method of one-step nano-thick SOI materials without an additional layer thinning step. INTRODUCTION For the decade, silicon-on-insulator (SOI) has become a key material to substitute for bulk silicon in reducing tremendous energy consumption for nano-scale high speed IC devices [1]. In the mainstream SOI wafer manufacturing, the most widespread method now for producing ultra-thin SOI wafer are Smart-Cut R and SIMOX processes. Smart-Cut R process, it may be now the most advanced SOI fabrication method is based on two basic techniques: hydrogen ion implantation and wafer bonding [2]. Ion implantation induces the formation of in-depth weakened layer filled with hydrogen ions, located at the mean ion penetration depth, which leads to split a thin film from the original substrate in following thermal treatment. In Smart-Cut R process, the fragile layer is created by using the lightest ion, i.e. hydrogen ion, which limited the nano-scale thickness of top silicon film [3]. However, the implant depth due to the light mass of hydrogen results in excessive thickness of top silicon film in SOI wafers. Additional thinning is usually needed but degrades thickness uniformity of the film further.

2 The thickness of top thin silicon layer can be decided by choosing the implantation energy in Smart-Cut R process. Terreault et al. [4, 5] modified a regular Smart-Cut process by co-implanting hydrogen ion with sufficient low implant energy (5 to 8 KeV) and heavier helium with high dose to get a thinner top silicon layer for FD SOI wafer fabrication. Helium is trapped in silicon and segregates in gas-vacancy complexes and forms bubbles just after implantation. During annealing at 700 C and above, the He-filled bubbles as well as voids microcavities, and platelets are created but besides the above voids creating, typically of up to a few tens of nanometer dimension, numerous point and extended defects are formed in Si:He layer at annealing [6]. However, the nanometer defects created by helium ions may not to be completely eliminated by absorbing at high temperature annealing due to the inertia of helium ions. To improve the thickness issue of Smart-Cut R processes, IBM employs an etch-back technique [7] combining with Smart-Cut process to etch and then thin the transferred layer to be nano-scale thick. The high quality of the nano-thick epitaxial silicon layer on etch-stop layer is difficult to be acquired and may be degraded by the following removal of etch-stop layer step. Usenko et al. [8] also develops so called Si-Sandwich TM process trying to solve the thickness issue. First of all, the silicon wafers are implanted with silicon ions to form a crystal disorder layer filled with defects as a buried hydrogen trap layer. Then the as-implanted wafers are hydrogenated by an electrolysis step. This process may have a surface contamination from the electrolysis step and the defects created by silicon implantation in the nano-thick silicon device layer. The aim of this investigation is to find out a simple nano-thick SOI fabrication method. The study includes a polysilicon cladding layer deposition step to format the polysilicon-oxide-silicon structure on the surface in a silicon wafer as a handle wafer, a ion implantation step to format a hydrogen-rich buried layer, an anodic bonding step to join the implanted device wafer with a Pyrex 7740 glass wafer, an annealing step to split the polysilicon-oxide-silicon layer from device wafer and then transfer this layer onto the glass wafer, and a transfer layer characteristic examination to compare the nano-scale thin film fabrication study. EXPERIMENTAL 4-in, p-type silicon wafers covered with 0.3μm silicon dioxide layer as a source wafers were used. The steps of this designed process are shown in Figure 1. The first step: thermally oxidizing a silicon wafer to be covered with a 0.3 m oxide layer as a source wafer; the second step: forming a 0.3μm polysilicon clapping layer on the source wafer; the third step: implanting hydrogen molecular ions into the polysilicon clapping surface

3 with dose of 4*10 16 /cm 2 at implant energy of 160KeV to form a hydrogen-rich buried layer therein as a device wafer; the forth step: bonding the device wafer to a Pyrex 7740 glass wafer as a handle wafer with anodic bonding process with the bonding control parameters of temperature (350 C), bias voltage (500 voltage) and time (40 minutes); the fifth step: annealing the bonded wafer pair and then separating and transferring a polysilicon-oxide-silicon layer from the device wafer onto the handle wafer; the polysilicon clapping layer was bonded onto the surface of the Pyrex 7740 glass wafer and the silicon layer was the top surface of the SOI substrate with an oxide layer between the polysilicon layer and the silicon layer. The investigation improves the thickness issue of transfer layer by using a polysilicon layer padding the top surface of oxide layer in conjunction with the Smart-Cut based layer transfer technique. Three samples were experimented with a regular Smart-Cut method and the nano-thick SOI fabrication approach in this study. Wafer Preparation The bare silicon wafers were 4-inh, p-type, ohm-cm and were thermally oxidized to grow 0.3μm silicon dioxide layer on the surface of this wafers by dry-oxidation process. After the oxidation process, undoping polysilicon clapping layers (1000 and 3000 Å, respectively) were deposited on the surfaces of the thermally oxidized silicon wafers in a low-pressure silane (SiH 4 ) CVD reactor at 620 o C. There are two device wafers with different thickness of polysilicon clapping layer to be used in the study: one is the 1000 Å thick polysilicon-3000 Å thick oxide silicon wafer and another one is the 3000 Å thick polysilicon-3000 Å thick oxide silicon wafer. + These device wafers were treated with the hydrogen molecular ion implantation, H 2 with dose of 4*10 16 /cm 2 at implant energy of 160KeV, and the hydrogen peak was created about at 7000 Å depth underneath the implanted surface. This defined the desired silicon transfer layer thickness is 3000 Å and 1000 Å from the 1000 Å thick polysilicon Å thick oxide silicon wafer and from the 3000 Å thick polysilicon Å thick oxide silicon wafer respectively. Wafer Bonding Process The roughness of the as-deposited CVD polysilicon surface was greater than 10 nm,

4 and caused the failure of the direct wafer bonding approach even through using plasma activated bonding technique. There are two ways to improve the roughness of the polysilicon surface for direct wafer bonding method if requirement: one is to employ the chemical-mechanical planarization (CMP) process on the polysilicon surface [9] to ensures a bondable surface and another one is to etch out the 0.3 m polysilicon by using tetramethyl ammonium hydroxide (TMAH) plus IPA etching solution [10]. TMAH+IPA etching solution is CMOS-compatible and a good choice for etching polysilicon without attacking exposed oxide. The surface of the exposed oxide layer after TMAH etching is not damaged because the etching time is very short due to the thickness of polysilicon clapping layer is less than one micrometer and polysilicon layer is easily etched out. However, in this study, we applied the anodic bonding method to overcome the high roughness barrier to bond the two wafers to verify the feasibility of the polysilicon padding concept. Layer Transfer Process The thickness of transferred layer is defined by the hydrogen ion implantation process: the implantation of hydrogen molecular ions, H 2 +, with the dosage of 4*10 16 /cm 2 and implant energy at 160KeV, into the device wafer to create a hydrogen concentration peak at about 7000 Å depth underneath the wafer surface. After the thermal-microwave hybrid treatment to exactly control the implant-peak layer-split, nano-scale thicknesses of the top silicon layer transferred of all samples were well controlled by different polysilicon thicknesses. The bonded pairs was treated in a microwave chamber at a constant temperature, 200, for 20 minutes and then annealing at the same temperature with microwave irradiating with power of 500W for 10 minutes. The microwave irradiation step can greatly reduce the annealing temperature for layer split from 500 C or above to 200 C. After 10 minutes, the layer split occurred and transferred from the device wafer onto the handle wafer to obtain a transferred silicon layer of precise thickness, good uniformity and high quality. RESULT AND DISCUSSION The distribution of hydrogen molecular ion implantation in the polysilicon clapping layer oxidized silicon substrate for the nano-thick SOI fabrication was simulated by the SRIM TM program. For regular Smart-Cut process, implanting hydrogen molecular ions with implant energy of 160Kev and tilt angle of seven into the device wafer, the simulated implantation profile is shown in Figure 2. The implant peak of hydrogen

5 molecular ions is at the depth from top surface about 680 nm. That means after the separating step, the top silicon layer is about 300 nm thick on the 300 nm oxide layer. To obtain the final 100 nm thick silicon device layer, the extra-transferred layer of 200 nm has to be removed by touch polishing or etch-stop technique. The implantation profile of the nano-thick SOI fabrication process in this study is as shown in Figure 3 and Figure 4. In Figure 3, the implant peak of hydrogen ions is at the depth from top surface about 690 nm and the thicknesses of polysilicon clapping layer and oxide layer are 100 nm and 300 nm. That means after the separating step, the top silicon layer is about 200 nm thick. In Figure 4, both of the polysilicon clapping layer and silicon-dioxide layer grown in 300nm, the implant peak of hydrogen ions is at the depth from top surface about 710 nm. The thickness of the top silicon layer about 100 nm can be obtained without any further thinning process. The device wafer and handle wafer were cleaned by RCA1 cleaning process in the class 1000 cleanroom. Because of the lack of appropriate spin-dry equipment; these wafers were dried by blow with nitrogen gas. Figure 5 shows the bonding image of the implanted 300 nm polysilicon clapping layer nm oxide layer covered device wafer and the glass handle wafer. The spots shown on the bonding image are unbonded area due to the particles contamination during the blow drying process after the RCA1 cleaning. After keeping at 200C for 20 minutes, the bonded pair was irradiated with microwave for 10 minutes at the same temperature; the sandwich structure layer was successfully transferred onto the handle wafer. Figure shows the transferred layer on the handle wafer as shown in Figure 6. SUMMARY Nano-thick SOI fabrication was shown the feasible for producing a 100 nm top silicon device layer without additional thinning step. The nano-thick SOI fabrication makes it possible to choose various nano-scale thickness of the top silicon layer by changing the thickness of polysilicon clapping layer. This process is quite simple without additional thinning step so it can keep the uniformity and exactness of the transferred silicon layer. After the implantation step, the poly-silicon clapping layer can be removed by etching prior to bonding process or can be directly bonded with bare silicon and then be recrystallized by an appropriate heat treatment.

6 ACKNOWLEDGES Authors would like to thank Prof. Pei-Wen Li of Department of Electrical Engineering, National Central University for her help in the silicon process of this study. REFERENCE 1. H. Mukai, Approaches for System LSI's- Meaning of SPA and its Strategy, Oki Technical Review No. 3 Vol. 67 (2000) 2.C. Malevile and C. Mazure, Smart-Cut technology: from 300nm ultrathin SOI production to advanced engineered substrates, Solid-State Electronics 48, 1005 (2004). 3. X.-Q. Feng and Y. Huang, Mechanics of Smart-Cut technology, International Journal of Solids and Structures 41, 4299 (2004). 4. C. Qian and B. Terreault, Blistering of silicon crystals by low kev hydrogen and helium ions, Journal of Applied Physics 90, pp (2001). 5. C. Qian, B. Terreault and S.C. Gujrathi, Layer splitting in Si by H + He ion co-implantation: channeling effect limitation at low energy, Nuclear instr. And Meth. In Phys. Res. B, Vol , pp (2001). 6. E. Oliviero, M.F. Beaufort and J.F. Barbot, J. Appl. Phys (2001). 7. K. V. Srikrishnan et al., Smart-Cut process for the production of thin semiconductor material films, US Patent (1999). 8. A. Usenko et al., Process for lift-off a layer from a substrate, US Patent (2002). 9. J. Steigerwald, S. P. Murarka, and R. J. Gutman, Chemical Mechanical Planarization of Microelectronic Materials, John Wiley & Sons: New York, F. S.-S. Chien et al., Silicon nanostructures fabricated by scanning probe oxidation and tetra-methyl ammonium hydroxide etching, J. of Appl. Phys. Vol. 91, No. 12 (2002)

7 FIGURES Figure 1: Nano-thick SOI fabrication method: forming a poly-silicon clapping layer first, and the implanting hydrogen molecular ions. After hydrogen implanting, the wafer boned with a Pyrex 7740 glass wafer by anodic bonding technique. Thermal-microwave hybrid treatment was used to split layer from the device wafer and then transfer layer onto the handle wafer. Figure 2: the implantation profile of hydrogen ions in silicon covered with 300 nm SiO 2 layer. Figure 3: the implantation profile of hydrogen ions in then silicon covered with 300 nm SiO 2 and 100nm poly-silicon layer.

8 Figure 4: the implantation profile of hydrogen ions in then silicon covered with 300 nm SiO 2 and 300nm poly-silicon layer. Figure 5: the bonding image of the implanted polysilicon clapping layer silicon wafer and the glass handle wafer. The spots in the bonding interface are unbonded area due to the particles contamination. Figure 6: The transferred nano-scale silicon layer on the glass handle wafer.