We are moving to 155 Donner Lab From Thursday, Feb 2 We will be able to accommodate everyone!

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1 -Spring 006 Digital Integrated Circuits Lecture 4 CMOS Manufacturing Process Design Rules EECS141 1 Good News! We are moving to 155 Donner Lab From Thursday, Feb We will be able to accommodate everyone! Lab starts on Monday! No swapping labs We are trying to add another section Homework #1 is due on Thursday Homework # to be posted tomorrow, due next Thursday EECS141 1

2 Class Material Last lecture Brief introduction to CMOS inverter operation Today s lecture CMOS manufacturing process (Ch..1-.) Design rules (Ch..) Reading (.1-.,..1-..) EECS141 The MOS Transistor Polysilicon Aluminum EECS141 4

3 MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D S NMOS Depletion D G G B PMOS Enhancement S S NMOS with Bulk Contact EECS141 5 A Modern CMOS Process gate-oxide TiSi AlCu Tungsten SiO n+ p-well p-epi poly n-well p+ SiO p+ Dual-Well ShallowTrench-Isolated CMOS Process EECS141 6

4 Transistor Layout Cross-Sectional View SiO poly p-well SiO n+ poly Layout View EECS141 p-well 7 The Manufacturing Process For a complete walk-through of the process (64 steps), check the Book web-page EECS

5 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development spin, rinse, dry acid etch EECS141 9 Patterning of SiO Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Chemical or plasma etch Hardened resist SiO (d) After development and etching of resist, chemical or plasma etch of SiO (e) After etching Hardened resist SiO SiO (f) Final result after removal of resist EECS

6 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers EECS CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with optional p-epi layer p-epi p+ SiN 4 SiO (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask EECS

7 CMOS Process Walk-Through SiO (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants EECS141 1 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO (i) After deposition of SiO insulator and contact hole etch. EECS

8 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO (k) After deposition of SiO insulator, etching of via s, deposition and patterning of second layer of Al. EECS Advanced Metallization EECS

9 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) EECS Design Rules Intra-layer Widths, spacing, area Inter-layer Enclosures, distances, extensions, overlaps Special rules (sub-0.5µm) Antenna rules, density rules, (area) EECS

10 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation EECS Layers in 0.5 μm m CMOS process EECS

11 Intra-Layer Design Rules Well Active Select Same Potential 10 0 or 6 Different Potential 9 Contact or Via Hole Polysilicon Metal1 Metal 4 EECS141 1 Transistor Layout Transistor 1 5 EECS141 11

12 Vias and Contacts 1 Metal to Active Contact 1 Via 1 Metal to Poly Contact 4 5 EECS141 Select Layer Select 1 5 Substrate Well EECS

13 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A n p-substrate Field n + p + Oxide (b) Cross-Section along A-A EECS141 5 Layout Editor EECS

14 Design Rule Checker EECS141 7 Sticks Diagram V DD In Out Dimensionless layout entities Only topology is important GND 1 Stick diagram of inverter EECS

15 Circuit Under Design V DD V DD M M4 V in V out V out M1 M EECS141 9 CMOS Inverter N Well V DD V DD PMOS λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND EECS

16 Two Inverters Share power and ground Abut cells V DD Connect in Metal EECS141 1 Next Lecture Operation and modeling of the MOS transistor EECS141 16